1 2019-05-21 Sudakshina Das <sudi.das@arm.com>
3 * arm-dis.c (emun mve_instructions): Updated for new instructions.
4 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
5 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
6 uqshl, urshrl and urshr.
7 (is_mve_okay_in_it): Add new instructions to TRUE list.
8 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
9 (print_insn_mve): Updated to accept new %j,
10 %<bitfield>m and %<bitfield>n patterns.
12 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
14 * mips-opc.c (mips_builtin_opcodes): Change source register
17 2019-05-20 Nick Clifton <nickc@redhat.com>
19 * po/fr.po: Updated French translation.
21 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
22 Michael Collison <michael.collison@arm.com>
24 * arm-dis.c (thumb32_opcodes): Add new instructions.
25 (enum mve_instructions): Likewise.
26 (enum mve_undefined): Add new reasons.
27 (is_mve_encoding_conflict): Handle new instructions.
28 (is_mve_undefined): Likewise.
29 (is_mve_unpredictable): Likewise.
30 (print_mve_undefined): Likewise.
31 (print_mve_size): Likewise.
33 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
34 Michael Collison <michael.collison@arm.com>
36 * arm-dis.c (thumb32_opcodes): Add new instructions.
37 (enum mve_instructions): Likewise.
38 (is_mve_encoding_conflict): Handle new instructions.
39 (is_mve_undefined): Likewise.
40 (is_mve_unpredictable): Likewise.
41 (print_mve_size): Likewise.
43 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
44 Michael Collison <michael.collison@arm.com>
46 * arm-dis.c (thumb32_opcodes): Add new instructions.
47 (enum mve_instructions): Likewise.
48 (is_mve_encoding_conflict): Likewise.
49 (is_mve_unpredictable): Likewise.
50 (print_mve_size): Likewise.
52 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
53 Michael Collison <michael.collison@arm.com>
55 * arm-dis.c (thumb32_opcodes): Add new instructions.
56 (enum mve_instructions): Likewise.
57 (is_mve_encoding_conflict): Handle new instructions.
58 (is_mve_undefined): Likewise.
59 (is_mve_unpredictable): Likewise.
60 (print_mve_size): Likewise.
62 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
63 Michael Collison <michael.collison@arm.com>
65 * arm-dis.c (thumb32_opcodes): Add new instructions.
66 (enum mve_instructions): Likewise.
67 (is_mve_encoding_conflict): Handle new instructions.
68 (is_mve_undefined): Likewise.
69 (is_mve_unpredictable): Likewise.
70 (print_mve_size): Likewise.
71 (print_insn_mve): Likewise.
73 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
74 Michael Collison <michael.collison@arm.com>
76 * arm-dis.c (thumb32_opcodes): Add new instructions.
77 (print_insn_thumb32): Handle new instructions.
79 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
80 Michael Collison <michael.collison@arm.com>
82 * arm-dis.c (enum mve_instructions): Add new instructions.
83 (enum mve_undefined): Add new reasons.
84 (is_mve_encoding_conflict): Handle new instructions.
85 (is_mve_undefined): Likewise.
86 (is_mve_unpredictable): Likewise.
87 (print_mve_undefined): Likewise.
88 (print_mve_size): Likewise.
89 (print_mve_shift_n): Likewise.
90 (print_insn_mve): Likewise.
92 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
93 Michael Collison <michael.collison@arm.com>
95 * arm-dis.c (enum mve_instructions): Add new instructions.
96 (is_mve_encoding_conflict): Handle new instructions.
97 (is_mve_unpredictable): Likewise.
98 (print_mve_rotate): Likewise.
99 (print_mve_size): Likewise.
100 (print_insn_mve): Likewise.
102 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
103 Michael Collison <michael.collison@arm.com>
105 * arm-dis.c (enum mve_instructions): Add new instructions.
106 (is_mve_encoding_conflict): Handle new instructions.
107 (is_mve_unpredictable): Likewise.
108 (print_mve_size): Likewise.
109 (print_insn_mve): Likewise.
111 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
112 Michael Collison <michael.collison@arm.com>
114 * arm-dis.c (enum mve_instructions): Add new instructions.
115 (enum mve_undefined): Add new reasons.
116 (is_mve_encoding_conflict): Handle new instructions.
117 (is_mve_undefined): Likewise.
118 (is_mve_unpredictable): Likewise.
119 (print_mve_undefined): Likewise.
120 (print_mve_size): Likewise.
121 (print_insn_mve): Likewise.
123 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
124 Michael Collison <michael.collison@arm.com>
126 * arm-dis.c (enum mve_instructions): Add new instructions.
127 (is_mve_encoding_conflict): Handle new instructions.
128 (is_mve_undefined): Likewise.
129 (is_mve_unpredictable): Likewise.
130 (print_mve_size): Likewise.
131 (print_insn_mve): Likewise.
133 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
134 Michael Collison <michael.collison@arm.com>
136 * arm-dis.c (enum mve_instructions): Add new instructions.
137 (enum mve_unpredictable): Add new reasons.
138 (enum mve_undefined): Likewise.
139 (is_mve_okay_in_it): Handle new isntructions.
140 (is_mve_encoding_conflict): Likewise.
141 (is_mve_undefined): Likewise.
142 (is_mve_unpredictable): Likewise.
143 (print_mve_vmov_index): Likewise.
144 (print_simd_imm8): Likewise.
145 (print_mve_undefined): Likewise.
146 (print_mve_unpredictable): Likewise.
147 (print_mve_size): Likewise.
148 (print_insn_mve): Likewise.
150 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
151 Michael Collison <michael.collison@arm.com>
153 * arm-dis.c (enum mve_instructions): Add new instructions.
154 (enum mve_unpredictable): Add new reasons.
155 (enum mve_undefined): Likewise.
156 (is_mve_encoding_conflict): Handle new instructions.
157 (is_mve_undefined): Likewise.
158 (is_mve_unpredictable): Likewise.
159 (print_mve_undefined): Likewise.
160 (print_mve_unpredictable): Likewise.
161 (print_mve_rounding_mode): Likewise.
162 (print_mve_vcvt_size): Likewise.
163 (print_mve_size): Likewise.
164 (print_insn_mve): Likewise.
166 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
167 Michael Collison <michael.collison@arm.com>
169 * arm-dis.c (enum mve_instructions): Add new instructions.
170 (enum mve_unpredictable): Add new reasons.
171 (enum mve_undefined): Likewise.
172 (is_mve_undefined): Handle new instructions.
173 (is_mve_unpredictable): Likewise.
174 (print_mve_undefined): Likewise.
175 (print_mve_unpredictable): Likewise.
176 (print_mve_size): Likewise.
177 (print_insn_mve): Likewise.
179 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
180 Michael Collison <michael.collison@arm.com>
182 * arm-dis.c (enum mve_instructions): Add new instructions.
183 (enum mve_undefined): Add new reasons.
184 (insns): Add new instructions.
185 (is_mve_encoding_conflict):
186 (print_mve_vld_str_addr): New print function.
187 (is_mve_undefined): Handle new instructions.
188 (is_mve_unpredictable): Likewise.
189 (print_mve_undefined): Likewise.
190 (print_mve_size): Likewise.
191 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
192 (print_insn_mve): Handle new operands.
194 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
195 Michael Collison <michael.collison@arm.com>
197 * arm-dis.c (enum mve_instructions): Add new instructions.
198 (enum mve_unpredictable): Add new reasons.
199 (is_mve_encoding_conflict): Handle new instructions.
200 (is_mve_unpredictable): Likewise.
201 (mve_opcodes): Add new instructions.
202 (print_mve_unpredictable): Handle new reasons.
203 (print_mve_register_blocks): New print function.
204 (print_mve_size): Handle new instructions.
205 (print_insn_mve): Likewise.
207 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
208 Michael Collison <michael.collison@arm.com>
210 * arm-dis.c (enum mve_instructions): Add new instructions.
211 (enum mve_unpredictable): Add new reasons.
212 (enum mve_undefined): Likewise.
213 (is_mve_encoding_conflict): Handle new instructions.
214 (is_mve_undefined): Likewise.
215 (is_mve_unpredictable): Likewise.
216 (coprocessor_opcodes): Move NEON VDUP from here...
217 (neon_opcodes): ... to here.
218 (mve_opcodes): Add new instructions.
219 (print_mve_undefined): Handle new reasons.
220 (print_mve_unpredictable): Likewise.
221 (print_mve_size): Handle new instructions.
222 (print_insn_neon): Handle vdup.
223 (print_insn_mve): Handle new operands.
225 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
226 Michael Collison <michael.collison@arm.com>
228 * arm-dis.c (enum mve_instructions): Add new instructions.
229 (enum mve_unpredictable): Add new values.
230 (mve_opcodes): Add new instructions.
231 (vec_condnames): New array with vector conditions.
232 (mve_predicatenames): New array with predicate suffixes.
233 (mve_vec_sizename): New array with vector sizes.
234 (enum vpt_pred_state): New enum with vector predication states.
235 (struct vpt_block): New struct type for vpt blocks.
236 (vpt_block_state): Global struct to keep track of state.
237 (mve_extract_pred_mask): New helper function.
238 (num_instructions_vpt_block): Likewise.
239 (mark_outside_vpt_block): Likewise.
240 (mark_inside_vpt_block): Likewise.
241 (invert_next_predicate_state): Likewise.
242 (update_next_predicate_state): Likewise.
243 (update_vpt_block_state): Likewise.
244 (is_vpt_instruction): Likewise.
245 (is_mve_encoding_conflict): Add entries for new instructions.
246 (is_mve_unpredictable): Likewise.
247 (print_mve_unpredictable): Handle new cases.
248 (print_instruction_predicate): Likewise.
249 (print_mve_size): New function.
250 (print_vec_condition): New function.
251 (print_insn_mve): Handle vpt blocks and new print operands.
253 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
255 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
256 8, 14 and 15 for Armv8.1-M Mainline.
258 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
259 Michael Collison <michael.collison@arm.com>
261 * arm-dis.c (enum mve_instructions): New enum.
262 (enum mve_unpredictable): Likewise.
263 (enum mve_undefined): Likewise.
264 (struct mopcode32): New struct.
265 (is_mve_okay_in_it): New function.
266 (is_mve_architecture): Likewise.
267 (arm_decode_field): Likewise.
268 (arm_decode_field_multiple): Likewise.
269 (is_mve_encoding_conflict): Likewise.
270 (is_mve_undefined): Likewise.
271 (is_mve_unpredictable): Likewise.
272 (print_mve_undefined): Likewise.
273 (print_mve_unpredictable): Likewise.
274 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
275 (print_insn_mve): New function.
276 (print_insn_thumb32): Handle MVE architecture.
277 (select_arm_features): Force thumb for Armv8.1-m Mainline.
279 2019-05-10 Nick Clifton <nickc@redhat.com>
282 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
283 end of the table prematurely.
285 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
287 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
290 2019-05-11 Alan Modra <amodra@gmail.com>
292 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
293 when -Mraw is in effect.
295 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
297 * aarch64-dis-2.c: Regenerate.
298 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
299 (OP_SVE_BBB): New variant set.
300 (OP_SVE_DDDD): New variant set.
301 (OP_SVE_HHH): New variant set.
302 (OP_SVE_HHHU): New variant set.
303 (OP_SVE_SSS): New variant set.
304 (OP_SVE_SSSU): New variant set.
305 (OP_SVE_SHH): New variant set.
306 (OP_SVE_SBBU): New variant set.
307 (OP_SVE_DSS): New variant set.
308 (OP_SVE_DHHU): New variant set.
309 (OP_SVE_VMV_HSD_BHS): New variant set.
310 (OP_SVE_VVU_HSD_BHS): New variant set.
311 (OP_SVE_VVVU_SD_BH): New variant set.
312 (OP_SVE_VVVU_BHSD): New variant set.
313 (OP_SVE_VVV_QHD_DBS): New variant set.
314 (OP_SVE_VVV_HSD_BHS): New variant set.
315 (OP_SVE_VVV_HSD_BHS2): New variant set.
316 (OP_SVE_VVV_BHS_HSD): New variant set.
317 (OP_SVE_VV_BHS_HSD): New variant set.
318 (OP_SVE_VVV_SD): New variant set.
319 (OP_SVE_VVU_BHS_HSD): New variant set.
320 (OP_SVE_VZVV_SD): New variant set.
321 (OP_SVE_VZVV_BH): New variant set.
322 (OP_SVE_VZV_SD): New variant set.
323 (aarch64_opcode_table): Add sve2 instructions.
325 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
327 * aarch64-asm-2.c: Regenerated.
328 * aarch64-dis-2.c: Regenerated.
329 * aarch64-opc-2.c: Regenerated.
330 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
331 for SVE_SHLIMM_UNPRED_22.
332 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
333 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
336 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
338 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
339 sve_size_tsz_bhs iclass encode.
340 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
341 sve_size_tsz_bhs iclass decode.
343 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
345 * aarch64-asm-2.c: Regenerated.
346 * aarch64-dis-2.c: Regenerated.
347 * aarch64-opc-2.c: Regenerated.
348 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
349 for SVE_Zm4_11_INDEX.
350 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
351 (fields): Handle SVE_i2h field.
352 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
353 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
355 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
357 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
358 sve_shift_tsz_bhsd iclass encode.
359 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
360 sve_shift_tsz_bhsd iclass decode.
362 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
364 * aarch64-asm-2.c: Regenerated.
365 * aarch64-dis-2.c: Regenerated.
366 * aarch64-opc-2.c: Regenerated.
367 * aarch64-asm.c (aarch64_ins_sve_shrimm):
368 (aarch64_encode_variant_using_iclass): Handle
369 sve_shift_tsz_hsd iclass encode.
370 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
371 sve_shift_tsz_hsd iclass decode.
372 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
373 for SVE_SHRIMM_UNPRED_22.
374 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
375 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
378 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
380 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
381 sve_size_013 iclass encode.
382 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
383 sve_size_013 iclass decode.
385 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
387 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
388 sve_size_bh iclass encode.
389 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
390 sve_size_bh iclass decode.
392 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
394 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
395 sve_size_sd2 iclass encode.
396 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
397 sve_size_sd2 iclass decode.
398 * aarch64-opc.c (fields): Handle SVE_sz2 field.
399 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
401 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
403 * aarch64-asm-2.c: Regenerated.
404 * aarch64-dis-2.c: Regenerated.
405 * aarch64-opc-2.c: Regenerated.
406 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
408 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
409 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
411 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
413 * aarch64-asm-2.c: Regenerated.
414 * aarch64-dis-2.c: Regenerated.
415 * aarch64-opc-2.c: Regenerated.
416 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
417 for SVE_Zm3_11_INDEX.
418 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
419 (fields): Handle SVE_i3l and SVE_i3h2 fields.
420 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
422 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
424 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
426 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
427 sve_size_hsd2 iclass encode.
428 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
429 sve_size_hsd2 iclass decode.
430 * aarch64-opc.c (fields): Handle SVE_size field.
431 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
433 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
435 * aarch64-asm-2.c: Regenerated.
436 * aarch64-dis-2.c: Regenerated.
437 * aarch64-opc-2.c: Regenerated.
438 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
440 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
441 (fields): Handle SVE_rot3 field.
442 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
443 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
445 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
447 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
450 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
453 (aarch64_feature_sve2, aarch64_feature_sve2aes,
454 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
455 aarch64_feature_sve2bitperm): New feature sets.
456 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
457 for feature set addresses.
458 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
459 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
461 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
462 Faraz Shahbazker <fshahbazker@wavecomp.com>
464 * mips-dis.c (mips_calculate_combination_ases): Add ISA
465 argument and set ASE_EVA_R6 appropriately.
466 (set_default_mips_dis_options): Pass ISA to above.
467 (parse_mips_dis_option): Likewise.
468 * mips-opc.c (EVAR6): New macro.
469 (mips_builtin_opcodes): Add llwpe, scwpe.
471 2019-05-01 Sudakshina Das <sudi.das@arm.com>
473 * aarch64-asm-2.c: Regenerated.
474 * aarch64-dis-2.c: Regenerated.
475 * aarch64-opc-2.c: Regenerated.
476 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
477 AARCH64_OPND_TME_UIMM16.
478 (aarch64_print_operand): Likewise.
479 * aarch64-tbl.h (QL_IMM_NIL): New.
482 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
484 2019-04-29 John Darrington <john@darrington.wattle.id.au>
486 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
488 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
489 Faraz Shahbazker <fshahbazker@wavecomp.com>
491 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
493 2019-04-24 John Darrington <john@darrington.wattle.id.au>
495 * s12z-opc.h: Add extern "C" bracketing to help
496 users who wish to use this interface in c++ code.
498 2019-04-24 John Darrington <john@darrington.wattle.id.au>
500 * s12z-opc.c (bm_decode): Handle bit map operations with the
503 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
505 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
506 specifier. Add entries for VLDR and VSTR of system registers.
507 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
508 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
509 of %J and %K format specifier.
511 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
513 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
514 Add new entries for VSCCLRM instruction.
515 (print_insn_coprocessor): Handle new %C format control code.
517 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
519 * arm-dis.c (enum isa): New enum.
520 (struct sopcode32): New structure.
521 (coprocessor_opcodes): change type of entries to struct sopcode32 and
522 set isa field of all current entries to ANY.
523 (print_insn_coprocessor): Change type of insn to struct sopcode32.
524 Only match an entry if its isa field allows the current mode.
526 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
528 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
530 (print_insn_thumb32): Add logic to print %n CLRM register list.
532 2019-04-15 Sudakshina Das <sudi.das@arm.com>
534 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
537 2019-04-15 Sudakshina Das <sudi.das@arm.com>
539 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
540 (print_insn_thumb32): Edit the switch case for %Z.
542 2019-04-15 Sudakshina Das <sudi.das@arm.com>
544 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
546 2019-04-15 Sudakshina Das <sudi.das@arm.com>
548 * arm-dis.c (thumb32_opcodes): New instruction bfl.
550 2019-04-15 Sudakshina Das <sudi.das@arm.com>
552 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
554 2019-04-15 Sudakshina Das <sudi.das@arm.com>
556 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
557 Arm register with r13 and r15 unpredictable.
558 (thumb32_opcodes): New instructions for bfx and bflx.
560 2019-04-15 Sudakshina Das <sudi.das@arm.com>
562 * arm-dis.c (thumb32_opcodes): New instructions for bf.
564 2019-04-15 Sudakshina Das <sudi.das@arm.com>
566 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
568 2019-04-15 Sudakshina Das <sudi.das@arm.com>
570 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
572 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
574 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
576 2019-04-12 John Darrington <john@darrington.wattle.id.au>
578 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
579 "optr". ("operator" is a reserved word in c++).
581 2019-04-11 Sudakshina Das <sudi.das@arm.com>
583 * aarch64-opc.c (aarch64_print_operand): Add case for
585 (verify_constraints): Likewise.
586 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
587 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
588 to accept Rt|SP as first operand.
589 (AARCH64_OPERANDS): Add new Rt_SP.
590 * aarch64-asm-2.c: Regenerated.
591 * aarch64-dis-2.c: Regenerated.
592 * aarch64-opc-2.c: Regenerated.
594 2019-04-11 Sudakshina Das <sudi.das@arm.com>
596 * aarch64-asm-2.c: Regenerated.
597 * aarch64-dis-2.c: Likewise.
598 * aarch64-opc-2.c: Likewise.
599 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
601 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
603 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
605 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
607 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
608 * i386-init.h: Regenerated.
610 2019-04-07 Alan Modra <amodra@gmail.com>
612 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
613 op_separator to control printing of spaces, comma and parens
614 rather than need_comma, need_paren and spaces vars.
616 2019-04-07 Alan Modra <amodra@gmail.com>
619 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
620 (print_insn_neon, print_insn_arm): Likewise.
622 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
624 * i386-dis-evex.h (evex_table): Updated to support BF16
626 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
627 and EVEX_W_0F3872_P_3.
628 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
629 (cpu_flags): Add bitfield for CpuAVX512_BF16.
630 * i386-opc.h (enum): Add CpuAVX512_BF16.
631 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
632 * i386-opc.tbl: Add AVX512 BF16 instructions.
633 * i386-init.h: Regenerated.
634 * i386-tbl.h: Likewise.
636 2019-04-05 Alan Modra <amodra@gmail.com>
638 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
639 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
640 to favour printing of "-" branch hint when using the "y" bit.
641 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
643 2019-04-05 Alan Modra <amodra@gmail.com>
645 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
646 opcode until first operand is output.
648 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
651 * ppc-opc.c (valid_bo_pre_v2): Add comments.
652 (valid_bo_post_v2): Add support for 'at' branch hints.
653 (insert_bo): Only error on branch on ctr.
654 (get_bo_hint_mask): New function.
655 (insert_boe): Add new 'branch_taken' formal argument. Add support
656 for inserting 'at' branch hints.
657 (extract_boe): Add new 'branch_taken' formal argument. Add support
658 for extracting 'at' branch hints.
659 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
660 (BOE): Delete operand.
661 (BOM, BOP): New operands.
663 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
664 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
665 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
666 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
667 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
668 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
669 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
670 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
671 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
672 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
673 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
674 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
675 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
676 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
677 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
678 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
679 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
680 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
681 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
682 bttarl+>: New extended mnemonics.
684 2019-03-28 Alan Modra <amodra@gmail.com>
687 * ppc-opc.c (BTF): Define.
688 (powerpc_opcodes): Use for mtfsb*.
689 * ppc-dis.c (print_insn_powerpc): Print fields with both
690 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
692 2019-03-25 Tamar Christina <tamar.christina@arm.com>
694 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
695 (mapping_symbol_for_insn): Implement new algorithm.
696 (print_insn): Remove duplicate code.
698 2019-03-25 Tamar Christina <tamar.christina@arm.com>
700 * aarch64-dis.c (print_insn_aarch64):
703 2019-03-25 Tamar Christina <tamar.christina@arm.com>
705 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
708 2019-03-25 Tamar Christina <tamar.christina@arm.com>
710 * aarch64-dis.c (last_stop_offset): New.
711 (print_insn_aarch64): Use stop_offset.
713 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
716 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
718 * i386-init.h: Regenerated.
720 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
723 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
724 vmovdqu16, vmovdqu32 and vmovdqu64.
725 * i386-tbl.h: Regenerated.
727 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
729 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
730 from vstrszb, vstrszh, and vstrszf.
732 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
734 * s390-opc.txt: Add instruction descriptions.
736 2019-02-08 Jim Wilson <jimw@sifive.com>
738 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
741 2019-02-07 Tamar Christina <tamar.christina@arm.com>
743 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
745 2019-02-07 Tamar Christina <tamar.christina@arm.com>
748 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
749 * aarch64-opc.c (verify_elem_sd): New.
750 (fields): Add FLD_sz entr.
751 * aarch64-tbl.h (_SIMD_INSN): New.
752 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
753 fmulx scalar and vector by element isns.
755 2019-02-07 Nick Clifton <nickc@redhat.com>
757 * po/sv.po: Updated Swedish translation.
759 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
761 * s390-mkopc.c (main): Accept arch13 as cpu string.
762 * s390-opc.c: Add new instruction formats and instruction opcode
764 * s390-opc.txt: Add new arch13 instructions.
766 2019-01-25 Sudakshina Das <sudi.das@arm.com>
768 * aarch64-tbl.h (QL_LDST_AT): Update macro.
769 (aarch64_opcode): Change encoding for stg, stzg
771 * aarch64-asm-2.c: Regenerated.
772 * aarch64-dis-2.c: Regenerated.
773 * aarch64-opc-2.c: Regenerated.
775 2019-01-25 Sudakshina Das <sudi.das@arm.com>
777 * aarch64-asm-2.c: Regenerated.
778 * aarch64-dis-2.c: Likewise.
779 * aarch64-opc-2.c: Likewise.
780 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
782 2019-01-25 Sudakshina Das <sudi.das@arm.com>
783 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
785 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
786 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
787 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
788 * aarch64-dis.h (ext_addr_simple_2): Likewise.
789 * aarch64-opc.c (operand_general_constraint_met_p): Remove
790 case for ldstgv_indexed.
791 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
792 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
793 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
794 * aarch64-asm-2.c: Regenerated.
795 * aarch64-dis-2.c: Regenerated.
796 * aarch64-opc-2.c: Regenerated.
798 2019-01-23 Nick Clifton <nickc@redhat.com>
800 * po/pt_BR.po: Updated Brazilian Portuguese translation.
802 2019-01-21 Nick Clifton <nickc@redhat.com>
804 * po/de.po: Updated German translation.
805 * po/uk.po: Updated Ukranian translation.
807 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
808 * mips-dis.c (mips_arch_choices): Fix typo in
809 gs464, gs464e and gs264e descriptors.
811 2019-01-19 Nick Clifton <nickc@redhat.com>
813 * configure: Regenerate.
814 * po/opcodes.pot: Regenerate.
816 2018-06-24 Nick Clifton <nickc@redhat.com>
820 2019-01-09 John Darrington <john@darrington.wattle.id.au>
822 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
824 -dis.c (opr_emit_disassembly): Do not omit an index if it is
827 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
829 * configure: Regenerate.
831 2019-01-07 Alan Modra <amodra@gmail.com>
833 * configure: Regenerate.
834 * po/POTFILES.in: Regenerate.
836 2019-01-03 John Darrington <john@darrington.wattle.id.au>
838 * s12z-opc.c: New file.
839 * s12z-opc.h: New file.
840 * s12z-dis.c: Removed all code not directly related to display
841 of instructions. Used the interface provided by the new files
843 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
844 * Makefile.in: Regenerate.
845 * configure.ac (bfd_s12z_arch): Correct the dependencies.
846 * configure: Regenerate.
848 2019-01-01 Alan Modra <amodra@gmail.com>
850 Update year range in copyright notice of all files.
852 For older changes see ChangeLog-2018
854 Copyright (C) 2019 Free Software Foundation, Inc.
856 Copying and distribution of this file, with or without modification,
857 are permitted in any medium without royalty provided the copyright
858 notice and this notice are preserved.
864 version-control: never