opcodes/ChangeLog

   1 2004-11-04 Jan Beulich <jbeulich@novell.com>
   2
   3         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
   4         (indirEb): Remove.
   5         (Mp): Use f_mode rather than none at all.
   6         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
   7         replaces what previously was x_mode; x_mode now means 128-bit SSE
   8         operands.
   9         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
  10         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
  11         pinsrw's second operand is Edqw.
  12         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
  13         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
  14         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
  15         mode when an operand size override is present or always suffixing.
  16         More instructions will need to be added to this group.
  17         (putop): Handle new macro chars 'C' (short/long suffix selector),
  18         'I' (Intel mode override for following macro char), and 'J' (for
  19         adding the 'l' prefix to far branches in AT&T mode). When an
  20         alternative was specified in the template, honor macro character when
  21         specified for Intel mode.
  22         (OP_E): Handle new *_mode values. Correct pointer specifications for
  23         memory operands. Consolidate output of index register.
  24         (OP_G): Handle new *_mode values.
  25         (OP_I): Handle const_1_mode.
  26         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
  27         respective opcode prefix bits have been consumed.
  28         (OP_EM, OP_EX): Provide some default handling for generating pointer
  29         specifications.
  30
  31 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
  32
  33         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
  34         COP_INST macro.
  35
  36 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  37
  38         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
  39         (getregliststring): Support HI/LO and user registers.
  40         * crx-opc.c (crx_instruction): Update data structure according to the
  41         rearrangement done in CRX opcode header file.
  42         (crx_regtab):  Likewise.
  43         (crx_optab):  Likewise.
  44         (crx_instruction): Reorder load/stor instructions, remove unsupported
  45         formats.
  46         support new Co-Processor instruction 'cpi'.
  47
  48 2004-10-27  Nick Clifton  <nickc@redhat.com>
  49
  50         * opcodes/iq2000-asm.c: Regenerate.
  51         * opcodes/iq2000-desc.c: Regenerate.
  52         * opcodes/iq2000-desc.h: Regenerate.
  53         * opcodes/iq2000-dis.c: Regenerate.
  54         * opcodes/iq2000-ibld.c: Regenerate.
  55         * opcodes/iq2000-opc.c: Regenerate.
  56         * opcodes/iq2000-opc.h: Regenerate.
  57
  58 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  59
  60         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
  61         us4, us5 (respectively).
  62         Remove unsupported 'popa' instruction.
  63         Reverse operands order in store co-processor instructions.
  64
  65 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
  66
  67         * Makefile.am: Run "make dep-am"
  68         * Makefile.in: Regenerate.
  69
  70 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
  71
  72         * xtensa-dis.c: Use ISO C90 formatting.
  73
  74 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
  75
  76         * ppc-opc.c: Revert 2004-09-09 change.
  77
  78 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
  79
  80         * xtensa-dis.c (state_names): Delete.
  81         (fetch_data): Use xtensa_isa_maxlength.
  82         (print_xtensa_operand): Replace operand parameter with opcode/operand
  83         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
  84         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
  85         instruction bundles.  Use xmalloc instead of malloc.
  86
  87 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
  88
  89         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
  90         initializers.
  91
  92 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
  93
  94         * crx-opc.c (crx_instruction): Support Co-processor insns.
  95         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
  96         (getregliststring): Change function to use the above enum.
  97         (print_arg): Handle CO-Processor insns.
  98         (crx_cinvs): Add 'b' option to invalidate the branch-target
  99         cache.
 100
 101 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 102
 103         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 104         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 105         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 106         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 107         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 108
 109 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 110
 111         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 112         rather than add it.
 113
 114 2004-09-30  Paul Brook  <paul@codesourcery.com>
 115
 116         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 117         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 118
 119 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 122         (CONFIG_STATUS_DEPENDENCIES): New.
 123         (Makefile): Removed.
 124         (config.status): Likewise.
 125         * Makefile.in: Regenerated.
 126
 127 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 128
 129         * Makefile.am: Run "make dep-am".
 130         * Makefile.in: Regenerate.
 131         * aclocal.m4: Regenerate.
 132         * configure: Regenerate.
 133         * po/POTFILES.in: Regenerate.
 134         * po/opcodes.pot: Regenerate.
 135
 136 2004-09-11  Andreas Schwab  <schwab@suse.de>
 137
 138         * configure: Rebuild.
 139
 140 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 141
 142         * ppc-opc.c (L): Make this field not optional.
 143
 144 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 145
 146         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 147         Fix parameter to 'm[t|f]csr' insns.
 148
 149 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 150
 151         * configure.in: Autoupdate to autoconf 2.59.
 152         * aclocal.m4: Rebuild with aclocal 1.4p6.
 153         * configure: Rebuild with autoconf 2.59.
 154         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 155         bfd changes for autoconf 2.59 on the way).
 156         * config.in: Rebuild with autoheader 2.59.
 157
 158 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 159
 160         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 161
 162 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 163
 164         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 165         (GRPPADLCK2): New define.
 166         (twobyte_has_modrm): True for 0xA6.
 167         (grps): GRPPADLCK2 for opcode 0xA6.
 168
 169 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 170
 171         Introduce SH2a support.
 172         * sh-opc.h (arch_sh2a_base): Renumber.
 173         (arch_sh2a_nofpu_base): Remove.
 174         (arch_sh_base_mask): Adjust.
 175         (arch_opann_mask): New.
 176         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 177         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 178         (sh_table): Adjust whitespace.
 179         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 180         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 181         instruction list throughout.
 182         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 183         of arch_sh2a in instruction list throughout.
 184         (arch_sh2e_up): Accomodate above changes.
 185         (arch_sh2_up): Ditto.
 186         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 187         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 188         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 189         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 190         * sh-opc.h (arch_sh2a_nofpu): New.
 191         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 192         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 193         instruction.
 194         2004-01-20  DJ Delorie  <dj@redhat.com>
 195         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 196         2003-12-29  DJ Delorie  <dj@redhat.com>
 197         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 198         sh_opcode_info, sh_table): Add sh2a support.
 199         (arch_op32): New, to tag 32-bit opcodes.
 200         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 201         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 202         * sh-opc.h (arch_sh2a): Add.
 203         * sh-dis.c (arch_sh2a): Handle.
 204         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 205
 206 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 207
 208         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 209
 210 2004-07-22  Nick Clifton  <nickc@redhat.com>
 211
 212         PR/280
 213         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 214         insns - this is done by objdump itself.
 215         * h8500-dis.c (print_insn_h8500): Likewise.
 216
 217 2004-07-21  Jan Beulich <jbeulich@novell.com>
 218
 219         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 220         regardless of address size prefix in effect.
 221         (ptr_reg): Size or address registers does not depend on rex64, but
 222         on the presence of an address size override.
 223         (OP_MMX): Use rex.x only for xmm registers.
 224         (OP_EM): Use rex.z only for xmm registers.
 225
 226 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 227
 228         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 229         move/branch operations to the bottom so that VR5400 multimedia
 230         instructions take precedence in disassembly.
 231
 232 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 233
 234         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 235         ISA-specific "break" encoding.
 236
 237 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 238
 239         * arm-opc.h: Fix typo in comment.
 240
 241 2004-07-11  Andreas Schwab  <schwab@suse.de>
 242
 243         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 244
 245 2004-07-09  Andreas Schwab  <schwab@suse.de>
 246
 247         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 248
 249 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 250
 251         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 252         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 253         (crx-dis.lo): New target.
 254         (crx-opc.lo): Likewise.
 255         * Makefile.in: Regenerate.
 256         * configure.in: Handle bfd_crx_arch.
 257         * configure: Regenerate.
 258         * crx-dis.c: New file.
 259         * crx-opc.c: New file.
 260         * disassemble.c (ARCH_crx): Define.
 261         (disassembler): Handle ARCH_crx.
 262
 263 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 264
 265         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 266         * ia64-asmtab.c: Regnerate.
 267
 268 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 269
 270         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 271         (extract_fxm): Don't test dialect.
 272         (XFXFXM_MASK): Include the power4 bit.
 273         (XFXM): Add p4 param.
 274         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 275
 276 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 277
 278         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 279         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 280
 281 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 282
 283         * ppc-opc.c (BH, XLBH_MASK): Define.
 284         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 285
 286 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 287
 288         * i386-dis.c (x_mode): Comment.
 289         (two_source_ops): File scope.
 290         (float_mem): Correct fisttpll and fistpll.
 291         (float_mem_mode): New table.
 292         (dofloat): Use it.
 293         (OP_E): Correct intel mode PTR output.
 294         (ptr_reg): Use open_char and close_char.
 295         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 296         operands.  Set two_source_ops.
 297
 298 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 299
 300         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 301         instead of _raw_size.
 302
 303 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 304
 305         * ia64-gen.c (in_iclass): Handle more postinc st
 306         and ld variants.
 307         * ia64-asmtab.c: Rebuilt.
 308
 309 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 310
 311         * s390-opc.txt: Correct architecture mask for some opcodes.
 312         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 313         in the esa mode as well.
 314
 315 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 316
 317         * sh-dis.c (target_arch): Make unsigned.
 318         (print_insn_sh): Replace (most of) switch with a call to
 319         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 320         * sh-opc.h: Redefine architecture flags values.
 321         Add sh3-nommu architecture.
 322         Reorganise <arch>_up macros so they make more visual sense.
 323         (SH_MERGE_ARCH_SET): Define new macro.
 324         (SH_VALID_BASE_ARCH_SET): Likewise.
 325         (SH_VALID_MMU_ARCH_SET): Likewise.
 326         (SH_VALID_CO_ARCH_SET): Likewise.
 327         (SH_VALID_ARCH_SET): Likewise.
 328         (SH_MERGE_ARCH_SET_VALID): Likewise.
 329         (SH_ARCH_SET_HAS_FPU): Likewise.
 330         (SH_ARCH_SET_HAS_DSP): Likewise.
 331         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 332         (sh_get_arch_from_bfd_mach): Add prototype.
 333         (sh_get_arch_up_from_bfd_mach): Likewise.
 334         (sh_get_bfd_mach_from_arch_set): Likewise.
 335         (sh_merge_bfd_arc): Likewise.
 336
 337 2004-05-24  Peter Barada  <peter@the-baradas.com>
 338
 339         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 340         into new match_insn_m68k function.  Loop over canidate
 341         matches and select first that completely matches.
 342         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 343         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 344         to verify addressing for MAC/EMAC.
 345         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 346         reigster halves since 'fpu' and 'spl' look misleading.
 347         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 348         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 349         first, tighten up match masks.
 350         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 351         'size' from special case code in print_insn_m68k to
 352         determine decode size of insns.
 353
 354 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 355
 356         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 357         well as when -mpower4.
 358
 359 2004-05-13  Nick Clifton  <nickc@redhat.com>
 360
 361         * po/fr.po: Updated French translation.
 362
 363 2004-05-05  Peter Barada  <peter@the-baradas.com>
 364
 365         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 366         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 367         * m68k-op.c: Switch from ColdFire chips to core variants.
 368
 369 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 370
 371         PR 147.
 372         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 373
 374 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 375
 376         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 377         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 378
 379 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 380
 381         * sh-dis.c (print_insn_sh): Print the value in constant pool
 382         as a symbol if it looks like a symbol.
 383
 384 2004-04-22  Peter Barada <peter@the-baradas.com>
 385
 386         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 387         appropriate ColdFire architectures.
 388         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 389         mask addressing.
 390         Add EMAC instructions, fix MAC instructions. Remove
 391         macmw/macml/msacmw/msacml instructions since mask addressing now
 392         supported.
 393
 394 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 395
 396         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 397         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 398         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 399         macro.  Adjust all users.
 400
 401 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 402
 403         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 404         separately.
 405
 406 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 407
 408         * m32r-asm.c: Regenerate.
 409
 410 2004-03-29  Stan Shebs  <shebs@apple.com>
 411
 412         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 413         used.
 414
 415 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 416
 417         * aclocal.m4: Regenerate.
 418         * config.in: Regenerate.
 419         * configure: Regenerate.
 420         * po/POTFILES.in: Regenerate.
 421         * po/opcodes.pot: Regenerate.
 422
 423 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 424
 425         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 426         PPC_OPERANDS_GPR_0.
 427         * ppc-opc.c (RA0): Define.
 428         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 429         (RAOPT): Rename from RAO.  Update all uses.
 430         (powerpc_opcodes): Use RA0 as appropriate.
 431
 432 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 433
 434         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 435
 436 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 437
 438         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 439
 440 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 441
 442         * i386-dis.c (GRPPLOCK): Delete.
 443         (grps): Delete GRPPLOCK entry.
 444
 445 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 446
 447         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 448         (M, Mp): Use OP_M.
 449         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 450         (GRPPADLCK): Define.
 451         (dis386): Use NOP_Fixup on "nop".
 452         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 453         (twobyte_has_modrm): Set for 0xa7.
 454         (padlock_table): Delete.  Move to..
 455         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 456         and clflush.
 457         (print_insn): Revert PADLOCK_SPECIAL code.
 458         (OP_E): Delete sfence, lfence, mfence checks.
 459
 460 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 461
 462         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 463         (INVLPG_Fixup): New function.
 464         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 465
 466 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 467
 468         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 469         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 470         (padlock_table): New struct with PadLock instructions.
 471         (print_insn): Handle PADLOCK_SPECIAL.
 472
 473 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 474
 475         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 476         (OP_E): Twiddle clflush to sfence here.
 477
 478 2004-03-08  Nick Clifton  <nickc@redhat.com>
 479
 480         * po/de.po: Updated German translation.
 481
 482 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 483
 484         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 485         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 486         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 487         accordingly.
 488
 489 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 490
 491         * frv-asm.c: Regenerate.
 492         * frv-desc.c: Regenerate.
 493         * frv-desc.h: Regenerate.
 494         * frv-dis.c: Regenerate.
 495         * frv-ibld.c: Regenerate.
 496         * frv-opc.c: Regenerate.
 497         * frv-opc.h: Regenerate.
 498
 499 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 500
 501         * frv-desc.c, frv-opc.c: Regenerate.
 502
 503 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 504
 505         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 506
 507 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 508
 509         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 510         Also correct mistake in the comment.
 511
 512 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 513
 514         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 515         ensure that double registers have even numbers.
 516         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 517         that reserved instruction 0xfffd does not decode the same
 518         as 0xfdfd (ftrv).
 519         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 520         REG_N refers to a double register.
 521         Add REG_N_B01 nibble type and use it instead of REG_NM
 522         in ftrv.
 523         Adjust the bit patterns in a few comments.
 524
 525 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 526
 527         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 528
 529 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 530
 531         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 532
 533 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 534
 535         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 536
 537 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 538
 539         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 540         mtivor32, mtivor33, mtivor34.
 541
 542 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 543
 544         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 545
 546 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 547
 548         * arm-opc.h Maverick accumulator register opcode fixes.
 549
 550 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 551
 552         * m32r-dis.c: Regenerate.
 553
 554 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 555
 556         * sh-opc.h (sh_table): "fsrra", not "fssra".
 557
 558 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 559
 560         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 561         contraints.
 562
 563 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 564
 565         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 566
 567 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 568
 569         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 570         1.  Don't print scale factor on AT&T mode when index missing.
 571
 572 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 573
 574         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 575         when loaded into XR registers.
 576
 577 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 578
 579         * frv-desc.h: Regenerate.
 580         * frv-desc.c: Regenerate.
 581         * frv-opc.c: Regenerate.
 582
 583 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 584
 585         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 586
 587 2004-01-09  Paul Brook  <paul@codesourcery.com>
 588
 589         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 590         specific opcodes.
 591
 592 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 593
 594         * Makefile.am (libopcodes_la_DEPENDENCIES)
 595         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 596         comment about the problem.
 597         * Makefile.in: Regenerate.
 598
 599 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 600
 601         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 602         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 603         cut&paste errors in shifting/truncating numerical operands.
 604         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 605         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 606         (parse_uslo16): Likewise.
 607         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 608         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 609         (parse_s12): Likewise.
 610         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 611         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 612         (parse_uslo16): Likewise.
 613         (parse_uhi16): Parse gothi and gotfuncdeschi.
 614         (parse_d12): Parse got12 and gotfuncdesc12.
 615         (parse_s12): Likewise.
 616
 617 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 618
 619         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 620         instruction which looks similar to an 'rla' instruction.
 621
 622 For older changes see ChangeLog-0203
 623 \f
 624 Local Variables:
 625 mode: change-log
 626 left-margin: 8
 627 fill-column: 74
 628 version-control: never
 629 End: