1 2020-03-06 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
4 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
5 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
6 (ptwrite): Split into non-64-bit and 64-bit forms.
7 * i386-tbl.h: Re-generate.
9 2020-03-06 Jan Beulich <jbeulich@suse.com>
11 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
13 * i386-tbl.h: Re-generate.
15 2020-03-04 Jan Beulich <jbeulich@suse.com>
17 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
18 (prefix_table): Move vmmcall here. Add vmgexit.
19 (rm_table): Replace vmmcall entry by prefix_table[] escape.
20 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
21 (cpu_flags): Add CpuSEV_ES entry.
22 * i386-opc.h (CpuSEV_ES): New.
23 (union i386_cpu_flags): Add cpusev_es field.
24 * i386-opc.tbl (vmgexit): New.
25 * i386-init.h, i386-tbl.h: Re-generate.
27 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
29 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
31 * i386-opc.h (IGNORESIZE): New.
32 (DEFAULTSIZE): Likewise.
33 (IgnoreSize): Removed.
34 (DefaultSize): Likewise.
36 (i386_opcode_modifier): Replace ignoresize/defaultsize with
38 * i386-opc.tbl (IgnoreSize): New.
39 (DefaultSize): Likewise.
40 * i386-tbl.h: Regenerated.
42 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
45 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
48 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
51 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
52 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
53 * i386-tbl.h: Regenerated.
55 2020-02-26 Alan Modra <amodra@gmail.com>
57 * aarch64-asm.c: Indent labels correctly.
58 * aarch64-dis.c: Likewise.
59 * aarch64-gen.c: Likewise.
60 * aarch64-opc.c: Likewise.
61 * alpha-dis.c: Likewise.
62 * i386-dis.c: Likewise.
63 * nds32-asm.c: Likewise.
64 * nfp-dis.c: Likewise.
65 * visium-dis.c: Likewise.
67 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
69 * arc-regs.h (int_vector_base): Make it available for all ARC
72 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
74 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
77 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
79 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
80 c.mv/c.li if rs1 is zero.
82 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
84 * i386-gen.c (cpu_flag_init): Replace CpuABM with
85 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
87 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
88 * i386-opc.h (CpuABM): Removed.
90 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
91 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
92 popcnt. Remove CpuABM from lzcnt.
93 * i386-init.h: Regenerated.
94 * i386-tbl.h: Likewise.
96 2020-02-17 Jan Beulich <jbeulich@suse.com>
98 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
99 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
100 VexW1 instead of open-coding them.
101 * i386-tbl.h: Re-generate.
103 2020-02-17 Jan Beulich <jbeulich@suse.com>
105 * i386-opc.tbl (AddrPrefixOpReg): Define.
106 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
107 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
108 templates. Drop NoRex64.
109 * i386-tbl.h: Re-generate.
111 2020-02-17 Jan Beulich <jbeulich@suse.com>
114 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
115 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
116 into Intel syntax instance (with Unpsecified) and AT&T one
118 (vcvtneps2bf16): Likewise, along with folding the two so far
120 * i386-tbl.h: Re-generate.
122 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
124 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
127 2020-02-17 Alan Modra <amodra@gmail.com>
129 * i386-gen.c (cpu_flag_init): Correct last change.
131 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
136 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
138 * i386-opc.tbl (movsx): Remove Intel syntax comments.
141 2020-02-14 Jan Beulich <jbeulich@suse.com>
144 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
145 destination for Cpu64-only variant.
146 (movzx): Fold patterns.
147 * i386-tbl.h: Re-generate.
149 2020-02-13 Jan Beulich <jbeulich@suse.com>
151 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
152 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
153 CPU_ANY_SSE4_FLAGS entry.
154 * i386-init.h: Re-generate.
156 2020-02-12 Jan Beulich <jbeulich@suse.com>
158 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
159 with Unspecified, making the present one AT&T syntax only.
160 * i386-tbl.h: Re-generate.
162 2020-02-12 Jan Beulich <jbeulich@suse.com>
164 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
165 * i386-tbl.h: Re-generate.
167 2020-02-12 Jan Beulich <jbeulich@suse.com>
170 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
171 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
172 Amd64 and Intel64 templates.
173 (call, jmp): Likewise for far indirect variants. Dro
175 * i386-tbl.h: Re-generate.
177 2020-02-11 Jan Beulich <jbeulich@suse.com>
179 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
180 * i386-opc.h (ShortForm): Delete.
181 (struct i386_opcode_modifier): Remove shortform field.
182 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
183 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
184 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
185 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
187 * i386-tbl.h: Re-generate.
189 2020-02-11 Jan Beulich <jbeulich@suse.com>
191 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
192 fucompi): Drop ShortForm from operand-less templates.
193 * i386-tbl.h: Re-generate.
195 2020-02-11 Alan Modra <amodra@gmail.com>
197 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
198 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
199 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
200 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
201 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
203 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
205 * arm-dis.c (print_insn_cde): Define 'V' parse character.
206 (cde_opcodes): Add VCX* instructions.
208 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
209 Matthew Malcomson <matthew.malcomson@arm.com>
211 * arm-dis.c (struct cdeopcode32): New.
212 (CDE_OPCODE): New macro.
213 (cde_opcodes): New disassembly table.
214 (regnames): New option to table.
215 (cde_coprocs): New global variable.
216 (print_insn_cde): New
217 (print_insn_thumb32): Use print_insn_cde.
218 (parse_arm_disassembler_options): Parse coprocN args.
220 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
223 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
225 * i386-opc.h (AMD64): Removed.
229 (INTEL64ONLY): Likewise.
230 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
231 * i386-opc.tbl (Amd64): New.
233 (Intel64Only): Likewise.
234 Replace AMD64 with Amd64. Update sysenter/sysenter with
235 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
236 * i386-tbl.h: Regenerated.
238 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
241 * z80-dis.c: Add support for GBZ80 opcodes.
243 2020-02-04 Alan Modra <amodra@gmail.com>
245 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
247 2020-02-03 Alan Modra <amodra@gmail.com>
249 * m32c-ibld.c: Regenerate.
251 2020-02-01 Alan Modra <amodra@gmail.com>
253 * frv-ibld.c: Regenerate.
255 2020-01-31 Jan Beulich <jbeulich@suse.com>
257 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
258 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
259 (OP_E_memory): Replace xmm_mdq_mode case label by
260 vex_scalar_w_dq_mode one.
261 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
263 2020-01-31 Jan Beulich <jbeulich@suse.com>
265 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
266 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
267 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
268 (intel_operand_size): Drop vex_w_dq_mode case label.
270 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
272 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
273 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
275 2020-01-30 Alan Modra <amodra@gmail.com>
277 * m32c-ibld.c: Regenerate.
279 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
281 * bpf-opc.c: Regenerate.
283 2020-01-30 Jan Beulich <jbeulich@suse.com>
285 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
286 (dis386): Use them to replace C2/C3 table entries.
287 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
288 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
289 ones. Use Size64 instead of DefaultSize on Intel64 ones.
290 * i386-tbl.h: Re-generate.
292 2020-01-30 Jan Beulich <jbeulich@suse.com>
294 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
296 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
298 * i386-tbl.h: Re-generate.
300 2020-01-30 Alan Modra <amodra@gmail.com>
302 * tic4x-dis.c (tic4x_dp): Make unsigned.
304 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
305 Jan Beulich <jbeulich@suse.com>
308 * i386-dis.c (MOVSXD_Fixup): New function.
309 (movsxd_mode): New enum.
310 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
311 (intel_operand_size): Handle movsxd_mode.
312 (OP_E_register): Likewise.
314 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
315 register on movsxd. Add movsxd with 16-bit destination register
316 for AMD64 and Intel64 ISAs.
317 * i386-tbl.h: Regenerated.
319 2020-01-27 Tamar Christina <tamar.christina@arm.com>
322 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
323 * aarch64-asm-2.c: Regenerate
324 * aarch64-dis-2.c: Likewise.
325 * aarch64-opc-2.c: Likewise.
327 2020-01-21 Jan Beulich <jbeulich@suse.com>
329 * i386-opc.tbl (sysret): Drop DefaultSize.
330 * i386-tbl.h: Re-generate.
332 2020-01-21 Jan Beulich <jbeulich@suse.com>
334 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
336 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
337 * i386-tbl.h: Re-generate.
339 2020-01-20 Nick Clifton <nickc@redhat.com>
341 * po/de.po: Updated German translation.
342 * po/pt_BR.po: Updated Brazilian Portuguese translation.
343 * po/uk.po: Updated Ukranian translation.
345 2020-01-20 Alan Modra <amodra@gmail.com>
347 * hppa-dis.c (fput_const): Remove useless cast.
349 2020-01-20 Alan Modra <amodra@gmail.com>
351 * arm-dis.c (print_insn_arm): Wrap 'T' value.
353 2020-01-18 Nick Clifton <nickc@redhat.com>
355 * configure: Regenerate.
356 * po/opcodes.pot: Regenerate.
358 2020-01-18 Nick Clifton <nickc@redhat.com>
360 Binutils 2.34 branch created.
362 2020-01-17 Christian Biesinger <cbiesinger@google.com>
364 * opintl.h: Fix spelling error (seperate).
366 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
368 * i386-opc.tbl: Add {vex} pseudo prefix.
369 * i386-tbl.h: Regenerated.
371 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
374 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
375 (neon_opcodes): Likewise.
376 (select_arm_features): Make sure we enable MVE bits when selecting
377 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
380 2020-01-16 Jan Beulich <jbeulich@suse.com>
382 * i386-opc.tbl: Drop stale comment from XOP section.
384 2020-01-16 Jan Beulich <jbeulich@suse.com>
386 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
387 (extractps): Add VexWIG to SSE2AVX forms.
388 * i386-tbl.h: Re-generate.
390 2020-01-16 Jan Beulich <jbeulich@suse.com>
392 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
393 Size64 from and use VexW1 on SSE2AVX forms.
394 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
395 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
396 * i386-tbl.h: Re-generate.
398 2020-01-15 Alan Modra <amodra@gmail.com>
400 * tic4x-dis.c (tic4x_version): Make unsigned long.
401 (optab, optab_special, registernames): New file scope vars.
402 (tic4x_print_register): Set up registernames rather than
403 malloc'd registertable.
404 (tic4x_disassemble): Delete optable and optable_special. Use
405 optab and optab_special instead. Throw away old optab,
406 optab_special and registernames when info->mach changes.
408 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
411 * z80-dis.c (suffix): Use .db instruction to generate double
414 2020-01-14 Alan Modra <amodra@gmail.com>
416 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
417 values to unsigned before shifting.
419 2020-01-13 Thomas Troeger <tstroege@gmx.de>
421 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
423 (print_insn_thumb16, print_insn_thumb32): Likewise.
424 (print_insn): Initialize the insn info.
425 * i386-dis.c (print_insn): Initialize the insn info fields, and
428 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
430 * arc-opc.c (C_NE): Make it required.
432 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
434 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
435 reserved register name.
437 2020-01-13 Alan Modra <amodra@gmail.com>
439 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
440 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
442 2020-01-13 Alan Modra <amodra@gmail.com>
444 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
445 result of wasm_read_leb128 in a uint64_t and check that bits
446 are not lost when copying to other locals. Use uint32_t for
447 most locals. Use PRId64 when printing int64_t.
449 2020-01-13 Alan Modra <amodra@gmail.com>
451 * score-dis.c: Formatting.
452 * score7-dis.c: Formatting.
454 2020-01-13 Alan Modra <amodra@gmail.com>
456 * score-dis.c (print_insn_score48): Use unsigned variables for
457 unsigned values. Don't left shift negative values.
458 (print_insn_score32): Likewise.
459 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
461 2020-01-13 Alan Modra <amodra@gmail.com>
463 * tic4x-dis.c (tic4x_print_register): Remove dead code.
465 2020-01-13 Alan Modra <amodra@gmail.com>
467 * fr30-ibld.c: Regenerate.
469 2020-01-13 Alan Modra <amodra@gmail.com>
471 * xgate-dis.c (print_insn): Don't left shift signed value.
472 (ripBits): Formatting, use 1u.
474 2020-01-10 Alan Modra <amodra@gmail.com>
476 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
477 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
479 2020-01-10 Alan Modra <amodra@gmail.com>
481 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
482 and XRREG value earlier to avoid a shift with negative exponent.
483 * m10200-dis.c (disassemble): Similarly.
485 2020-01-09 Nick Clifton <nickc@redhat.com>
488 * z80-dis.c (ld_ii_ii): Use correct cast.
490 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
493 * z80-dis.c (ld_ii_ii): Use character constant when checking
496 2020-01-09 Jan Beulich <jbeulich@suse.com>
498 * i386-dis.c (SEP_Fixup): New.
500 (dis386_twobyte): Use it for sysenter/sysexit.
501 (enum x86_64_isa): Change amd64 enumerator to value 1.
502 (OP_J): Compare isa64 against intel64 instead of amd64.
503 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
505 * i386-tbl.h: Re-generate.
507 2020-01-08 Alan Modra <amodra@gmail.com>
509 * z8k-dis.c: Include libiberty.h
510 (instr_data_s): Make max_fetched unsigned.
511 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
512 Don't exceed byte_info bounds.
513 (output_instr): Make num_bytes unsigned.
514 (unpack_instr): Likewise for nibl_count and loop.
515 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
517 * z8k-opc.h: Regenerate.
519 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
521 * arc-tbl.h (llock): Use 'LLOCK' as class.
523 (scond): Use 'SCOND' as class.
525 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
528 2020-01-06 Alan Modra <amodra@gmail.com>
530 * m32c-ibld.c: Regenerate.
532 2020-01-06 Alan Modra <amodra@gmail.com>
535 * z80-dis.c (suffix): Don't use a local struct buffer copy.
536 Peek at next byte to prevent recursion on repeated prefix bytes.
537 Ensure uninitialised "mybuf" is not accessed.
538 (print_insn_z80): Don't zero n_fetch and n_used here,..
539 (print_insn_z80_buf): ..do it here instead.
541 2020-01-04 Alan Modra <amodra@gmail.com>
543 * m32r-ibld.c: Regenerate.
545 2020-01-04 Alan Modra <amodra@gmail.com>
547 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
549 2020-01-04 Alan Modra <amodra@gmail.com>
551 * crx-dis.c (match_opcode): Avoid shift left of signed value.
553 2020-01-04 Alan Modra <amodra@gmail.com>
555 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
557 2020-01-03 Jan Beulich <jbeulich@suse.com>
559 * aarch64-tbl.h (aarch64_opcode_table): Use
560 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
562 2020-01-03 Jan Beulich <jbeulich@suse.com>
564 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
565 forms of SUDOT and USDOT.
567 2020-01-03 Jan Beulich <jbeulich@suse.com>
569 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
571 * opcodes/aarch64-dis-2.c: Re-generate.
573 2020-01-03 Jan Beulich <jbeulich@suse.com>
575 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
577 * opcodes/aarch64-dis-2.c: Re-generate.
579 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
581 * z80-dis.c: Add support for eZ80 and Z80 instructions.
583 2020-01-01 Alan Modra <amodra@gmail.com>
585 Update year range in copyright notice of all files.
587 For older changes see ChangeLog-2019
589 Copyright (C) 2020 Free Software Foundation, Inc.
591 Copying and distribution of this file, with or without modification,
592 are permitted in any medium without royalty provided the copyright
593 notice and this notice are preserved.
599 version-control: never