1 2020-03-22 Alan Modra <amodra@gmail.com>
3 * arc-dis.c (find_format): Use ISO C string concatenation rather
4 than line continuation within a string. Don't access needs_limm
5 before testing opcode != NULL.
7 2020-03-22 Alan Modra <amodra@gmail.com>
9 * ns32k-dis.c (print_insn_arg): Update comment.
10 (print_insn_ns32k): Reduce size of index_offset array, and
11 initialize, passing -1 to print_insn_arg for args that are not
12 an index. Don't exit arg loop early. Abort on bad arg number.
14 2020-03-22 Alan Modra <amodra@gmail.com>
16 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
17 * s12z-opc.c: Formatting.
18 (operands_f): Return an int.
19 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
20 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
21 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
22 (exg_sex_discrim): Likewise.
23 (create_immediate_operand, create_bitfield_operand),
24 (create_register_operand_with_size, create_register_all_operand),
25 (create_register_all16_operand, create_simple_memory_operand),
26 (create_memory_operand, create_memory_auto_operand): Don't
27 segfault on malloc failure.
28 (z_ext24_decode): Return an int status, negative on fail, zero
30 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
31 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
32 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
33 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
34 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
35 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
36 (loop_primitive_decode, shift_decode, psh_pul_decode),
37 (bit_field_decode): Similarly.
38 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
39 to return value, update callers.
40 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
41 Don't segfault on NULL operand.
42 (decode_operation): Return OP_INVALID on first fail.
43 (decode_s12z): Check all reads, returning -1 on fail.
45 2020-03-20 Alan Modra <amodra@gmail.com>
47 * metag-dis.c (print_insn_metag): Don't ignore status from
50 2020-03-20 Alan Modra <amodra@gmail.com>
52 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
53 Initialize parts of buffer not written when handling a possible
54 2-byte insn at end of section. Don't attempt decoding of such
55 an insn by the 4-byte machinery.
57 2020-03-20 Alan Modra <amodra@gmail.com>
59 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
60 partially filled buffer. Prevent lookup of 4-byte insns when
61 only VLE 2-byte insns are possible due to section size. Print
62 ".word" rather than ".long" for 2-byte leftovers.
64 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
67 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
69 2020-03-13 Jan Beulich <jbeulich@suse.com>
71 * i386-dis.c (X86_64_0D): Rename to ...
72 (X86_64_0E): ... this.
74 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
76 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
77 * Makefile.in: Regenerated.
79 2020-03-09 Jan Beulich <jbeulich@suse.com>
81 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
83 * i386-tbl.h: Re-generate.
85 2020-03-09 Jan Beulich <jbeulich@suse.com>
87 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
88 vprot*, vpsha*, and vpshl*.
89 * i386-tbl.h: Re-generate.
91 2020-03-09 Jan Beulich <jbeulich@suse.com>
93 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
94 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
95 * i386-tbl.h: Re-generate.
97 2020-03-09 Jan Beulich <jbeulich@suse.com>
99 * i386-gen.c (set_bitfield): Ignore zero-length field names.
100 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
101 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
102 * i386-tbl.h: Re-generate.
104 2020-03-09 Jan Beulich <jbeulich@suse.com>
106 * i386-gen.c (struct template_arg, struct template_instance,
107 struct template_param, struct template, templates,
108 parse_template, expand_templates): New.
109 (process_i386_opcodes): Various local variables moved to
110 expand_templates. Call parse_template and expand_templates.
111 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
112 * i386-tbl.h: Re-generate.
114 2020-03-06 Jan Beulich <jbeulich@suse.com>
116 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
117 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
118 register and memory source templates. Replace VexW= by VexW*
120 * i386-tbl.h: Re-generate.
122 2020-03-06 Jan Beulich <jbeulich@suse.com>
124 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
125 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
126 * i386-tbl.h: Re-generate.
128 2020-03-06 Jan Beulich <jbeulich@suse.com>
130 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
131 * i386-tbl.h: Re-generate.
133 2020-03-06 Jan Beulich <jbeulich@suse.com>
135 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
136 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
137 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
138 VexW0 on SSE2AVX variants.
139 (vmovq): Drop NoRex64 from XMM/XMM variants.
140 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
141 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
142 applicable use VexW0.
143 * i386-tbl.h: Re-generate.
145 2020-03-06 Jan Beulich <jbeulich@suse.com>
147 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
148 * i386-opc.h (Rex64): Delete.
149 (struct i386_opcode_modifier): Remove rex64 field.
150 * i386-opc.tbl (crc32): Drop Rex64.
151 Replace Rex64 with Size64 everywhere else.
152 * i386-tbl.h: Re-generate.
154 2020-03-06 Jan Beulich <jbeulich@suse.com>
156 * i386-dis.c (OP_E_memory): Exclude recording of used address
157 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
158 addressed memory operands for MPX insns.
160 2020-03-06 Jan Beulich <jbeulich@suse.com>
162 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
163 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
164 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
165 (ptwrite): Split into non-64-bit and 64-bit forms.
166 * i386-tbl.h: Re-generate.
168 2020-03-06 Jan Beulich <jbeulich@suse.com>
170 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
172 * i386-tbl.h: Re-generate.
174 2020-03-04 Jan Beulich <jbeulich@suse.com>
176 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
177 (prefix_table): Move vmmcall here. Add vmgexit.
178 (rm_table): Replace vmmcall entry by prefix_table[] escape.
179 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
180 (cpu_flags): Add CpuSEV_ES entry.
181 * i386-opc.h (CpuSEV_ES): New.
182 (union i386_cpu_flags): Add cpusev_es field.
183 * i386-opc.tbl (vmgexit): New.
184 * i386-init.h, i386-tbl.h: Re-generate.
186 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
188 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
190 * i386-opc.h (IGNORESIZE): New.
191 (DEFAULTSIZE): Likewise.
192 (IgnoreSize): Removed.
193 (DefaultSize): Likewise.
195 (i386_opcode_modifier): Replace ignoresize/defaultsize with
197 * i386-opc.tbl (IgnoreSize): New.
198 (DefaultSize): Likewise.
199 * i386-tbl.h: Regenerated.
201 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
204 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
207 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
210 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
211 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
212 * i386-tbl.h: Regenerated.
214 2020-02-26 Alan Modra <amodra@gmail.com>
216 * aarch64-asm.c: Indent labels correctly.
217 * aarch64-dis.c: Likewise.
218 * aarch64-gen.c: Likewise.
219 * aarch64-opc.c: Likewise.
220 * alpha-dis.c: Likewise.
221 * i386-dis.c: Likewise.
222 * nds32-asm.c: Likewise.
223 * nfp-dis.c: Likewise.
224 * visium-dis.c: Likewise.
226 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
228 * arc-regs.h (int_vector_base): Make it available for all ARC
231 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
233 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
236 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
238 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
239 c.mv/c.li if rs1 is zero.
241 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
243 * i386-gen.c (cpu_flag_init): Replace CpuABM with
244 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
246 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
247 * i386-opc.h (CpuABM): Removed.
249 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
250 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
251 popcnt. Remove CpuABM from lzcnt.
252 * i386-init.h: Regenerated.
253 * i386-tbl.h: Likewise.
255 2020-02-17 Jan Beulich <jbeulich@suse.com>
257 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
258 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
259 VexW1 instead of open-coding them.
260 * i386-tbl.h: Re-generate.
262 2020-02-17 Jan Beulich <jbeulich@suse.com>
264 * i386-opc.tbl (AddrPrefixOpReg): Define.
265 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
266 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
267 templates. Drop NoRex64.
268 * i386-tbl.h: Re-generate.
270 2020-02-17 Jan Beulich <jbeulich@suse.com>
273 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
274 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
275 into Intel syntax instance (with Unpsecified) and AT&T one
277 (vcvtneps2bf16): Likewise, along with folding the two so far
279 * i386-tbl.h: Re-generate.
281 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
283 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
286 2020-02-17 Alan Modra <amodra@gmail.com>
288 * i386-gen.c (cpu_flag_init): Correct last change.
290 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
292 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
295 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
297 * i386-opc.tbl (movsx): Remove Intel syntax comments.
300 2020-02-14 Jan Beulich <jbeulich@suse.com>
303 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
304 destination for Cpu64-only variant.
305 (movzx): Fold patterns.
306 * i386-tbl.h: Re-generate.
308 2020-02-13 Jan Beulich <jbeulich@suse.com>
310 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
311 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
312 CPU_ANY_SSE4_FLAGS entry.
313 * i386-init.h: Re-generate.
315 2020-02-12 Jan Beulich <jbeulich@suse.com>
317 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
318 with Unspecified, making the present one AT&T syntax only.
319 * i386-tbl.h: Re-generate.
321 2020-02-12 Jan Beulich <jbeulich@suse.com>
323 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
324 * i386-tbl.h: Re-generate.
326 2020-02-12 Jan Beulich <jbeulich@suse.com>
329 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
330 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
331 Amd64 and Intel64 templates.
332 (call, jmp): Likewise for far indirect variants. Dro
334 * i386-tbl.h: Re-generate.
336 2020-02-11 Jan Beulich <jbeulich@suse.com>
338 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
339 * i386-opc.h (ShortForm): Delete.
340 (struct i386_opcode_modifier): Remove shortform field.
341 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
342 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
343 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
344 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
346 * i386-tbl.h: Re-generate.
348 2020-02-11 Jan Beulich <jbeulich@suse.com>
350 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
351 fucompi): Drop ShortForm from operand-less templates.
352 * i386-tbl.h: Re-generate.
354 2020-02-11 Alan Modra <amodra@gmail.com>
356 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
357 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
358 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
359 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
360 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
362 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
364 * arm-dis.c (print_insn_cde): Define 'V' parse character.
365 (cde_opcodes): Add VCX* instructions.
367 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
368 Matthew Malcomson <matthew.malcomson@arm.com>
370 * arm-dis.c (struct cdeopcode32): New.
371 (CDE_OPCODE): New macro.
372 (cde_opcodes): New disassembly table.
373 (regnames): New option to table.
374 (cde_coprocs): New global variable.
375 (print_insn_cde): New
376 (print_insn_thumb32): Use print_insn_cde.
377 (parse_arm_disassembler_options): Parse coprocN args.
379 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
382 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
384 * i386-opc.h (AMD64): Removed.
388 (INTEL64ONLY): Likewise.
389 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
390 * i386-opc.tbl (Amd64): New.
392 (Intel64Only): Likewise.
393 Replace AMD64 with Amd64. Update sysenter/sysenter with
394 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
395 * i386-tbl.h: Regenerated.
397 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
400 * z80-dis.c: Add support for GBZ80 opcodes.
402 2020-02-04 Alan Modra <amodra@gmail.com>
404 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
406 2020-02-03 Alan Modra <amodra@gmail.com>
408 * m32c-ibld.c: Regenerate.
410 2020-02-01 Alan Modra <amodra@gmail.com>
412 * frv-ibld.c: Regenerate.
414 2020-01-31 Jan Beulich <jbeulich@suse.com>
416 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
417 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
418 (OP_E_memory): Replace xmm_mdq_mode case label by
419 vex_scalar_w_dq_mode one.
420 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
422 2020-01-31 Jan Beulich <jbeulich@suse.com>
424 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
425 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
426 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
427 (intel_operand_size): Drop vex_w_dq_mode case label.
429 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
431 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
432 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
434 2020-01-30 Alan Modra <amodra@gmail.com>
436 * m32c-ibld.c: Regenerate.
438 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
440 * bpf-opc.c: Regenerate.
442 2020-01-30 Jan Beulich <jbeulich@suse.com>
444 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
445 (dis386): Use them to replace C2/C3 table entries.
446 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
447 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
448 ones. Use Size64 instead of DefaultSize on Intel64 ones.
449 * i386-tbl.h: Re-generate.
451 2020-01-30 Jan Beulich <jbeulich@suse.com>
453 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
455 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
457 * i386-tbl.h: Re-generate.
459 2020-01-30 Alan Modra <amodra@gmail.com>
461 * tic4x-dis.c (tic4x_dp): Make unsigned.
463 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
464 Jan Beulich <jbeulich@suse.com>
467 * i386-dis.c (MOVSXD_Fixup): New function.
468 (movsxd_mode): New enum.
469 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
470 (intel_operand_size): Handle movsxd_mode.
471 (OP_E_register): Likewise.
473 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
474 register on movsxd. Add movsxd with 16-bit destination register
475 for AMD64 and Intel64 ISAs.
476 * i386-tbl.h: Regenerated.
478 2020-01-27 Tamar Christina <tamar.christina@arm.com>
481 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
482 * aarch64-asm-2.c: Regenerate
483 * aarch64-dis-2.c: Likewise.
484 * aarch64-opc-2.c: Likewise.
486 2020-01-21 Jan Beulich <jbeulich@suse.com>
488 * i386-opc.tbl (sysret): Drop DefaultSize.
489 * i386-tbl.h: Re-generate.
491 2020-01-21 Jan Beulich <jbeulich@suse.com>
493 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
495 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
496 * i386-tbl.h: Re-generate.
498 2020-01-20 Nick Clifton <nickc@redhat.com>
500 * po/de.po: Updated German translation.
501 * po/pt_BR.po: Updated Brazilian Portuguese translation.
502 * po/uk.po: Updated Ukranian translation.
504 2020-01-20 Alan Modra <amodra@gmail.com>
506 * hppa-dis.c (fput_const): Remove useless cast.
508 2020-01-20 Alan Modra <amodra@gmail.com>
510 * arm-dis.c (print_insn_arm): Wrap 'T' value.
512 2020-01-18 Nick Clifton <nickc@redhat.com>
514 * configure: Regenerate.
515 * po/opcodes.pot: Regenerate.
517 2020-01-18 Nick Clifton <nickc@redhat.com>
519 Binutils 2.34 branch created.
521 2020-01-17 Christian Biesinger <cbiesinger@google.com>
523 * opintl.h: Fix spelling error (seperate).
525 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
527 * i386-opc.tbl: Add {vex} pseudo prefix.
528 * i386-tbl.h: Regenerated.
530 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
533 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
534 (neon_opcodes): Likewise.
535 (select_arm_features): Make sure we enable MVE bits when selecting
536 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
539 2020-01-16 Jan Beulich <jbeulich@suse.com>
541 * i386-opc.tbl: Drop stale comment from XOP section.
543 2020-01-16 Jan Beulich <jbeulich@suse.com>
545 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
546 (extractps): Add VexWIG to SSE2AVX forms.
547 * i386-tbl.h: Re-generate.
549 2020-01-16 Jan Beulich <jbeulich@suse.com>
551 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
552 Size64 from and use VexW1 on SSE2AVX forms.
553 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
554 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
555 * i386-tbl.h: Re-generate.
557 2020-01-15 Alan Modra <amodra@gmail.com>
559 * tic4x-dis.c (tic4x_version): Make unsigned long.
560 (optab, optab_special, registernames): New file scope vars.
561 (tic4x_print_register): Set up registernames rather than
562 malloc'd registertable.
563 (tic4x_disassemble): Delete optable and optable_special. Use
564 optab and optab_special instead. Throw away old optab,
565 optab_special and registernames when info->mach changes.
567 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
570 * z80-dis.c (suffix): Use .db instruction to generate double
573 2020-01-14 Alan Modra <amodra@gmail.com>
575 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
576 values to unsigned before shifting.
578 2020-01-13 Thomas Troeger <tstroege@gmx.de>
580 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
582 (print_insn_thumb16, print_insn_thumb32): Likewise.
583 (print_insn): Initialize the insn info.
584 * i386-dis.c (print_insn): Initialize the insn info fields, and
587 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
589 * arc-opc.c (C_NE): Make it required.
591 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
593 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
594 reserved register name.
596 2020-01-13 Alan Modra <amodra@gmail.com>
598 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
599 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
601 2020-01-13 Alan Modra <amodra@gmail.com>
603 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
604 result of wasm_read_leb128 in a uint64_t and check that bits
605 are not lost when copying to other locals. Use uint32_t for
606 most locals. Use PRId64 when printing int64_t.
608 2020-01-13 Alan Modra <amodra@gmail.com>
610 * score-dis.c: Formatting.
611 * score7-dis.c: Formatting.
613 2020-01-13 Alan Modra <amodra@gmail.com>
615 * score-dis.c (print_insn_score48): Use unsigned variables for
616 unsigned values. Don't left shift negative values.
617 (print_insn_score32): Likewise.
618 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
620 2020-01-13 Alan Modra <amodra@gmail.com>
622 * tic4x-dis.c (tic4x_print_register): Remove dead code.
624 2020-01-13 Alan Modra <amodra@gmail.com>
626 * fr30-ibld.c: Regenerate.
628 2020-01-13 Alan Modra <amodra@gmail.com>
630 * xgate-dis.c (print_insn): Don't left shift signed value.
631 (ripBits): Formatting, use 1u.
633 2020-01-10 Alan Modra <amodra@gmail.com>
635 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
636 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
638 2020-01-10 Alan Modra <amodra@gmail.com>
640 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
641 and XRREG value earlier to avoid a shift with negative exponent.
642 * m10200-dis.c (disassemble): Similarly.
644 2020-01-09 Nick Clifton <nickc@redhat.com>
647 * z80-dis.c (ld_ii_ii): Use correct cast.
649 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
652 * z80-dis.c (ld_ii_ii): Use character constant when checking
655 2020-01-09 Jan Beulich <jbeulich@suse.com>
657 * i386-dis.c (SEP_Fixup): New.
659 (dis386_twobyte): Use it for sysenter/sysexit.
660 (enum x86_64_isa): Change amd64 enumerator to value 1.
661 (OP_J): Compare isa64 against intel64 instead of amd64.
662 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
664 * i386-tbl.h: Re-generate.
666 2020-01-08 Alan Modra <amodra@gmail.com>
668 * z8k-dis.c: Include libiberty.h
669 (instr_data_s): Make max_fetched unsigned.
670 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
671 Don't exceed byte_info bounds.
672 (output_instr): Make num_bytes unsigned.
673 (unpack_instr): Likewise for nibl_count and loop.
674 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
676 * z8k-opc.h: Regenerate.
678 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
680 * arc-tbl.h (llock): Use 'LLOCK' as class.
682 (scond): Use 'SCOND' as class.
684 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
687 2020-01-06 Alan Modra <amodra@gmail.com>
689 * m32c-ibld.c: Regenerate.
691 2020-01-06 Alan Modra <amodra@gmail.com>
694 * z80-dis.c (suffix): Don't use a local struct buffer copy.
695 Peek at next byte to prevent recursion on repeated prefix bytes.
696 Ensure uninitialised "mybuf" is not accessed.
697 (print_insn_z80): Don't zero n_fetch and n_used here,..
698 (print_insn_z80_buf): ..do it here instead.
700 2020-01-04 Alan Modra <amodra@gmail.com>
702 * m32r-ibld.c: Regenerate.
704 2020-01-04 Alan Modra <amodra@gmail.com>
706 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
708 2020-01-04 Alan Modra <amodra@gmail.com>
710 * crx-dis.c (match_opcode): Avoid shift left of signed value.
712 2020-01-04 Alan Modra <amodra@gmail.com>
714 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
716 2020-01-03 Jan Beulich <jbeulich@suse.com>
718 * aarch64-tbl.h (aarch64_opcode_table): Use
719 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
721 2020-01-03 Jan Beulich <jbeulich@suse.com>
723 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
724 forms of SUDOT and USDOT.
726 2020-01-03 Jan Beulich <jbeulich@suse.com>
728 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
730 * opcodes/aarch64-dis-2.c: Re-generate.
732 2020-01-03 Jan Beulich <jbeulich@suse.com>
734 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
736 * opcodes/aarch64-dis-2.c: Re-generate.
738 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
740 * z80-dis.c: Add support for eZ80 and Z80 instructions.
742 2020-01-01 Alan Modra <amodra@gmail.com>
744 Update year range in copyright notice of all files.
746 For older changes see ChangeLog-2019
748 Copyright (C) 2020 Free Software Foundation, Inc.
750 Copying and distribution of this file, with or without modification,
751 are permitted in any medium without royalty provided the copyright
752 notice and this notice are preserved.
758 version-control: never