1 2018-07-19 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
4 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
5 VPCLMULQDQ templates into their respective AVX512VL counterparts
6 where possible, using Disp8ShiftVL and CheckRegSize instead of
7 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
8 * i386-tbl.h: Re-generate.
10 2018-07-19 Jan Beulich <jbeulich@suse.com>
12 * i386-opc.tbl: Fold AVX512DQ templates into their respective
13 AVX512VL counterparts where possible, using Disp8ShiftVL and
14 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
15 IgnoreSize) as appropriate.
16 * i386-tbl.h: Re-generate.
18 2018-07-19 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl: Fold AVX512BW templates into their respective
21 AVX512VL counterparts where possible, using Disp8ShiftVL and
22 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
23 IgnoreSize) as appropriate.
24 * i386-tbl.h: Re-generate.
26 2018-07-19 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl: Fold AVX512CD templates into their respective
29 AVX512VL counterparts where possible, using Disp8ShiftVL and
30 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
31 IgnoreSize) as appropriate.
32 * i386-tbl.h: Re-generate.
34 2018-07-19 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.h (DISP8_SHIFT_VL): New.
37 * i386-opc.tbl (Disp8ShiftVL): Define.
38 (various): Fold AVX512VL templates into their respective
39 AVX512F counterparts where possible, using Disp8ShiftVL and
40 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
41 IgnoreSize) as appropriate.
42 * i386-tbl.h: Re-generate.
44 2018-07-19 Jan Beulich <jbeulich@suse.com>
46 * Makefile.am: Change dependencies and rule for
47 $(srcdir)/i386-init.h.
48 * Makefile.in: Re-generate.
49 * i386-gen.c (process_i386_opcodes): New local variable
50 "marker". Drop opening of input file. Recognize marker and line
52 * i386-opc.tbl (OPCODE_I386_H): Define.
53 (i386-opc.h): Include it.
56 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
59 * i386-opc.h (Byte): Update comments.
68 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
70 * i386-tbl.h: Regenerated.
72 2018-07-12 Sudakshina Das <sudi.das@arm.com>
74 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
75 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
76 * aarch64-asm-2.c: Regenerate.
77 * aarch64-dis-2.c: Regenerate.
78 * aarch64-opc-2.c: Regenerate.
80 2018-07-12 Tamar Christina <tamar.christina@arm.com>
83 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
84 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
85 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
86 sqdmulh, sqrdmulh): Use Em16.
88 2018-07-11 Sudakshina Das <sudi.das@arm.com>
90 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
91 csdb together with them.
92 (thumb32_opcodes): Likewise.
94 2018-07-11 Jan Beulich <jbeulich@suse.com>
96 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
97 requiring 32-bit registers as operands 2 and 3. Improve
99 (mwait, mwaitx): Fold templates. Improve comments.
100 OPERAND_TYPE_INOUTPORTREG.
101 * i386-tbl.h: Re-generate.
103 2018-07-11 Jan Beulich <jbeulich@suse.com>
105 * i386-gen.c (operand_type_init): Remove
106 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
107 OPERAND_TYPE_INOUTPORTREG.
108 * i386-init.h: Re-generate.
110 2018-07-11 Jan Beulich <jbeulich@suse.com>
112 * i386-opc.tbl (wrssd, wrussd): Add Dword.
113 (wrssq, wrussq): Add Qword.
114 * i386-tbl.h: Re-generate.
116 2018-07-11 Jan Beulich <jbeulich@suse.com>
118 * i386-opc.h: Rename OTMax to OTNum.
119 (OTNumOfUints): Adjust calculation.
120 (OTUnused): Directly alias to OTNum.
122 2018-07-09 Maciej W. Rozycki <macro@mips.com>
124 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
126 (lea_reg_xys): Likewise.
127 (print_insn_loop_primitive): Rename `reg' local variable to
130 2018-07-06 Tamar Christina <tamar.christina@arm.com>
133 * aarch64-tbl.h (ldarh): Fix disassembly mask.
135 2018-07-06 Tamar Christina <tamar.christina@arm.com>
138 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
139 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
141 2018-07-02 Maciej W. Rozycki <macro@mips.com>
144 * mips-dis.c (mips_option_arg_t): New enumeration.
145 (mips_options): New variable.
146 (disassembler_options_mips): New function.
147 (print_mips_disassembler_options): Reimplement in terms of
148 `disassembler_options_mips'.
149 * arm-dis.c (disassembler_options_arm): Adapt to using the
150 `disasm_options_and_args_t' structure.
151 * ppc-dis.c (disassembler_options_powerpc): Likewise.
152 * s390-dis.c (disassembler_options_s390): Likewise.
154 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
156 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
158 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
159 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
160 * testsuite/ld-arm/tls-longplt.d: Likewise.
162 2018-06-29 Tamar Christina <tamar.christina@arm.com>
165 * aarch64-asm-2.c: Regenerate.
166 * aarch64-dis-2.c: Likewise.
167 * aarch64-opc-2.c: Likewise.
168 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
169 * aarch64-opc.c (operand_general_constraint_met_p,
170 aarch64_print_operand): Likewise.
171 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
172 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
174 (AARCH64_OPERANDS): Add Em2.
176 2018-06-26 Nick Clifton <nickc@redhat.com>
178 * po/uk.po: Updated Ukranian translation.
179 * po/de.po: Updated German translation.
180 * po/pt_BR.po: Updated Brazilian Portuguese translation.
182 2018-06-26 Nick Clifton <nickc@redhat.com>
184 * nfp-dis.c: Fix spelling mistake.
186 2018-06-24 Nick Clifton <nickc@redhat.com>
188 * configure: Regenerate.
189 * po/opcodes.pot: Regenerate.
191 2018-06-24 Nick Clifton <nickc@redhat.com>
195 2018-06-19 Tamar Christina <tamar.christina@arm.com>
197 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
198 * aarch64-asm-2.c: Regenerate.
199 * aarch64-dis-2.c: Likewise.
201 2018-06-21 Maciej W. Rozycki <macro@mips.com>
203 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
204 `-M ginv' option description.
206 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
209 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
212 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
214 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
215 * configure.ac: Remove AC_PREREQ.
216 * Makefile.in: Re-generate.
217 * aclocal.m4: Re-generate.
218 * configure: Re-generate.
220 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
222 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
223 mips64r6 descriptors.
224 (parse_mips_ase_option): Handle -Mginv option.
225 (print_mips_disassembler_options): Document -Mginv.
226 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
228 (mips_opcodes): Define ginvi and ginvt.
230 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
231 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
233 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
234 * mips-opc.c (CRC, CRC64): New macros.
235 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
236 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
239 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
242 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
243 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
245 2018-06-06 Alan Modra <amodra@gmail.com>
247 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
248 setjmp. Move init for some other vars later too.
250 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
252 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
253 (dis_private): Add new fields for property section tracking.
254 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
255 (xtensa_instruction_fits): New functions.
256 (fetch_data): Bump minimal fetch size to 4.
257 (print_insn_xtensa): Make struct dis_private static.
258 Load and prepare property table on section change.
259 Don't disassemble literals. Don't disassemble instructions that
260 cross property table boundaries.
262 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
264 * configure: Regenerated.
266 2018-06-01 Jan Beulich <jbeulich@suse.com>
268 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
269 * i386-tbl.h: Re-generate.
271 2018-06-01 Jan Beulich <jbeulich@suse.com>
273 * i386-opc.tbl (sldt, str): Add NoRex64.
274 * i386-tbl.h: Re-generate.
276 2018-06-01 Jan Beulich <jbeulich@suse.com>
278 * i386-opc.tbl (invpcid): Add Oword.
279 * i386-tbl.h: Re-generate.
281 2018-06-01 Alan Modra <amodra@gmail.com>
283 * sysdep.h (_bfd_error_handler): Don't declare.
284 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
285 * rl78-decode.opc: Likewise.
286 * msp430-decode.c: Regenerate.
287 * rl78-decode.c: Regenerate.
289 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
291 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
292 * i386-init.h : Regenerated.
294 2018-05-25 Alan Modra <amodra@gmail.com>
296 * Makefile.in: Regenerate.
297 * po/POTFILES.in: Regenerate.
299 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
301 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
302 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
303 (insert_bab, extract_bab, insert_btab, extract_btab,
304 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
305 (BAT, BBA VBA RBS XB6S): Delete macros.
306 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
307 (BB, BD, RBX, XC6): Update for new macros.
308 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
309 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
310 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
311 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
313 2018-05-18 John Darrington <john@darrington.wattle.id.au>
315 * Makefile.am: Add support for s12z architecture.
316 * configure.ac: Likewise.
317 * disassemble.c: Likewise.
318 * disassemble.h: Likewise.
319 * Makefile.in: Regenerate.
320 * configure: Regenerate.
321 * s12z-dis.c: New file.
324 2018-05-18 Alan Modra <amodra@gmail.com>
326 * nfp-dis.c: Don't #include libbfd.h.
327 (init_nfp3200_priv): Use bfd_get_section_contents.
328 (nit_nfp6000_mecsr_sec): Likewise.
330 2018-05-17 Nick Clifton <nickc@redhat.com>
332 * po/zh_CN.po: Updated simplified Chinese translation.
334 2018-05-16 Tamar Christina <tamar.christina@arm.com>
337 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
338 * aarch64-dis-2.c: Regenerate.
340 2018-05-15 Tamar Christina <tamar.christina@arm.com>
343 * aarch64-asm.c (opintl.h): Include.
344 (aarch64_ins_sysreg): Enforce read/write constraints.
345 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
346 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
347 (F_REG_READ, F_REG_WRITE): New.
348 * aarch64-opc.c (aarch64_print_operand): Generate notes for
350 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
351 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
352 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
353 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
354 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
355 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
356 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
357 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
358 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
359 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
360 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
361 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
362 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
363 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
364 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
365 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
366 msr (F_SYS_WRITE), mrs (F_SYS_READ).
368 2018-05-15 Tamar Christina <tamar.christina@arm.com>
371 * aarch64-dis.c (no_notes: New.
372 (parse_aarch64_dis_option): Support notes.
373 (aarch64_decode_insn, print_operands): Likewise.
374 (print_aarch64_disassembler_options): Document notes.
375 * aarch64-opc.c (aarch64_print_operand): Support notes.
377 2018-05-15 Tamar Christina <tamar.christina@arm.com>
380 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
381 and take error struct.
382 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
383 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
384 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
385 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
386 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
387 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
388 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
389 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
390 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
391 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
392 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
393 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
394 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
395 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
396 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
397 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
398 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
399 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
400 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
401 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
402 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
403 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
404 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
405 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
406 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
407 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
408 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
409 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
410 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
411 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
412 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
413 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
414 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
415 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
416 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
417 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
418 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
419 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
420 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
421 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
422 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
423 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
424 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
425 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
426 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
427 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
428 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
429 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
430 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
431 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
432 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
433 (determine_disassembling_preference, aarch64_decode_insn,
434 print_insn_aarch64_word, print_insn_data): Take errors struct.
435 (print_insn_aarch64): Use errors.
436 * aarch64-asm-2.c: Regenerate.
437 * aarch64-dis-2.c: Regenerate.
438 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
439 boolean in aarch64_insert_operan.
440 (print_operand_extractor): Likewise.
441 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
443 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
445 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
447 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
451 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
453 * cr16-opc.c (cr16_instruction): Comment typo fix.
454 * hppa-dis.c (print_insn_hppa): Likewise.
456 2018-05-08 Jim Wilson <jimw@sifive.com>
458 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
459 (match_c_slli64, match_srxi_as_c_srxi): New.
460 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
461 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
462 <c.slli, c.srli, c.srai>: Use match_s_slli.
463 <c.slli64, c.srli64, c.srai64>: New.
465 2018-05-08 Alan Modra <amodra@gmail.com>
467 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
468 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
469 partition opcode space for index lookup.
471 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
473 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
474 <insn_length>: ...with this. Update usage.
475 Remove duplicate call to *info->memory_error_func.
477 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
478 H.J. Lu <hongjiu.lu@intel.com>
480 * i386-dis.c (Gva): New.
481 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
482 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
483 (prefix_table): New instructions (see prefix above).
484 (mod_table): New instructions (see prefix above).
485 (OP_G): Handle va_mode.
486 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
488 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
489 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
490 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
491 * i386-opc.tbl: Add movidir{i,64b}.
492 * i386-init.h: Regenerated.
493 * i386-tbl.h: Likewise.
495 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
499 * i386-opc.h (AddrPrefixOp0): Renamed to ...
500 (AddrPrefixOpReg): This.
501 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
502 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
504 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
506 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
507 (vle_num_opcodes): Likewise.
508 (spe2_num_opcodes): Likewise.
509 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
511 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
512 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
515 2018-05-01 Tamar Christina <tamar.christina@arm.com>
517 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
519 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
521 Makefile.am: Added nfp-dis.c.
522 configure.ac: Added bfd_nfp_arch.
523 disassemble.h: Added print_insn_nfp prototype.
524 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
525 nfp-dis.c: New, for NFP support.
526 po/POTFILES.in: Added nfp-dis.c to the list.
527 Makefile.in: Regenerate.
528 configure: Regenerate.
530 2018-04-26 Jan Beulich <jbeulich@suse.com>
532 * i386-opc.tbl: Fold various non-memory operand AVX512VL
533 templates into their base ones.
534 * i386-tlb.h: Re-generate.
536 2018-04-26 Jan Beulich <jbeulich@suse.com>
538 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
539 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
540 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
541 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
542 * i386-init.h: Re-generate.
544 2018-04-26 Jan Beulich <jbeulich@suse.com>
546 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
547 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
548 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
549 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
551 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
553 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
555 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
556 cpuregzmm, and cpuregmask.
557 * i386-init.h: Re-generate.
558 * i386-tbl.h: Re-generate.
560 2018-04-26 Jan Beulich <jbeulich@suse.com>
562 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
563 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
564 * i386-init.h: Re-generate.
566 2018-04-26 Jan Beulich <jbeulich@suse.com>
568 * i386-gen.c (VexImmExt): Delete.
569 * i386-opc.h (VexImmExt, veximmext): Delete.
570 * i386-opc.tbl: Drop all VexImmExt uses.
571 * i386-tlb.h: Re-generate.
573 2018-04-25 Jan Beulich <jbeulich@suse.com>
575 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
577 * i386-tlb.h: Re-generate.
579 2018-04-25 Tamar Christina <tamar.christina@arm.com>
581 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
583 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
585 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
587 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
588 (cpu_flags): Add CpuCLDEMOTE.
589 * i386-init.h: Regenerate.
590 * i386-opc.h (enum): Add CpuCLDEMOTE,
591 (i386_cpu_flags): Add cpucldemote.
592 * i386-opc.tbl: Add cldemote.
593 * i386-tbl.h: Regenerate.
595 2018-04-16 Alan Modra <amodra@gmail.com>
597 * Makefile.am: Remove sh5 and sh64 support.
598 * configure.ac: Likewise.
599 * disassemble.c: Likewise.
600 * disassemble.h: Likewise.
601 * sh-dis.c: Likewise.
602 * sh64-dis.c: Delete.
603 * sh64-opc.c: Delete.
604 * sh64-opc.h: Delete.
605 * Makefile.in: Regenerate.
606 * configure: Regenerate.
607 * po/POTFILES.in: Regenerate.
609 2018-04-16 Alan Modra <amodra@gmail.com>
611 * Makefile.am: Remove w65 support.
612 * configure.ac: Likewise.
613 * disassemble.c: Likewise.
614 * disassemble.h: Likewise.
617 * Makefile.in: Regenerate.
618 * configure: Regenerate.
619 * po/POTFILES.in: Regenerate.
621 2018-04-16 Alan Modra <amodra@gmail.com>
623 * configure.ac: Remove we32k support.
624 * configure: Regenerate.
626 2018-04-16 Alan Modra <amodra@gmail.com>
628 * Makefile.am: Remove m88k support.
629 * configure.ac: Likewise.
630 * disassemble.c: Likewise.
631 * disassemble.h: Likewise.
632 * m88k-dis.c: Delete.
633 * Makefile.in: Regenerate.
634 * configure: Regenerate.
635 * po/POTFILES.in: Regenerate.
637 2018-04-16 Alan Modra <amodra@gmail.com>
639 * Makefile.am: Remove i370 support.
640 * configure.ac: Likewise.
641 * disassemble.c: Likewise.
642 * disassemble.h: Likewise.
643 * i370-dis.c: Delete.
644 * i370-opc.c: Delete.
645 * Makefile.in: Regenerate.
646 * configure: Regenerate.
647 * po/POTFILES.in: Regenerate.
649 2018-04-16 Alan Modra <amodra@gmail.com>
651 * Makefile.am: Remove h8500 support.
652 * configure.ac: Likewise.
653 * disassemble.c: Likewise.
654 * disassemble.h: Likewise.
655 * h8500-dis.c: Delete.
656 * h8500-opc.h: Delete.
657 * Makefile.in: Regenerate.
658 * configure: Regenerate.
659 * po/POTFILES.in: Regenerate.
661 2018-04-16 Alan Modra <amodra@gmail.com>
663 * configure.ac: Remove tahoe support.
664 * configure: Regenerate.
666 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
668 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
670 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
672 * i386-tbl.h: Regenerated.
674 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
676 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
677 PREFIX_MOD_1_0FAE_REG_6.
679 (OP_E_register): Use va_mode.
680 * i386-dis-evex.h (prefix_table):
681 New instructions (see prefixes above).
682 * i386-gen.c (cpu_flag_init): Add WAITPKG.
683 (cpu_flags): Likewise.
684 * i386-opc.h (enum): Likewise.
685 (i386_cpu_flags): Likewise.
686 * i386-opc.tbl: Add umonitor, umwait, tpause.
687 * i386-init.h: Regenerate.
688 * i386-tbl.h: Likewise.
690 2018-04-11 Alan Modra <amodra@gmail.com>
692 * opcodes/i860-dis.c: Delete.
693 * opcodes/i960-dis.c: Delete.
694 * Makefile.am: Remove i860 and i960 support.
695 * configure.ac: Likewise.
696 * disassemble.c: Likewise.
697 * disassemble.h: Likewise.
698 * Makefile.in: Regenerate.
699 * configure: Regenerate.
700 * po/POTFILES.in: Regenerate.
702 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
707 (print_insn): Clear vex instead of vex.evex.
709 2018-04-04 Nick Clifton <nickc@redhat.com>
711 * po/es.po: Updated Spanish translation.
713 2018-03-28 Jan Beulich <jbeulich@suse.com>
715 * i386-gen.c (opcode_modifiers): Delete VecESize.
716 * i386-opc.h (VecESize): Delete.
717 (struct i386_opcode_modifier): Delete vecesize.
718 * i386-opc.tbl: Drop VecESize.
719 * i386-tlb.h: Re-generate.
721 2018-03-28 Jan Beulich <jbeulich@suse.com>
723 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
724 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
725 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
726 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
727 * i386-tlb.h: Re-generate.
729 2018-03-28 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
733 * i386-tlb.h: Re-generate.
735 2018-03-28 Jan Beulich <jbeulich@suse.com>
737 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
738 (vex_len_table): Drop Y for vcvt*2si.
739 (putop): Replace plain 'Y' handling by abort().
741 2018-03-28 Nick Clifton <nickc@redhat.com>
744 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
745 instructions with only a base address register.
746 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
747 handle AARHC64_OPND_SVE_ADDR_R.
748 (aarch64_print_operand): Likewise.
749 * aarch64-asm-2.c: Regenerate.
750 * aarch64_dis-2.c: Regenerate.
751 * aarch64-opc-2.c: Regenerate.
753 2018-03-22 Jan Beulich <jbeulich@suse.com>
755 * i386-opc.tbl: Drop VecESize from register only insn forms and
756 memory forms not allowing broadcast.
757 * i386-tlb.h: Re-generate.
759 2018-03-22 Jan Beulich <jbeulich@suse.com>
761 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
762 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
763 sha256*): Drop Disp<N>.
765 2018-03-22 Jan Beulich <jbeulich@suse.com>
767 * i386-dis.c (EbndS, bnd_swap_mode): New.
768 (prefix_table): Use EbndS.
769 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
770 * i386-opc.tbl (bndmov): Move misplaced Load.
771 * i386-tlb.h: Re-generate.
773 2018-03-22 Jan Beulich <jbeulich@suse.com>
775 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
776 templates allowing memory operands and folded ones for register
778 * i386-tlb.h: Re-generate.
780 2018-03-22 Jan Beulich <jbeulich@suse.com>
782 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
783 256-bit templates. Drop redundant leftover Disp<N>.
784 * i386-tlb.h: Re-generate.
786 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
788 * riscv-opc.c (riscv_insn_types): New.
790 2018-03-13 Nick Clifton <nickc@redhat.com>
792 * po/pt_BR.po: Updated Brazilian Portuguese translation.
794 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
796 * i386-opc.tbl: Add Optimize to clr.
797 * i386-tbl.h: Regenerated.
799 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
801 * i386-gen.c (opcode_modifiers): Remove OldGcc.
802 * i386-opc.h (OldGcc): Removed.
803 (i386_opcode_modifier): Remove oldgcc.
804 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
805 instructions for old (<= 2.8.1) versions of gcc.
806 * i386-tbl.h: Regenerated.
808 2018-03-08 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.h (EVEXDYN): New.
811 * i386-opc.tbl: Fold various AVX512VL templates.
812 * i386-tlb.h: Re-generate.
814 2018-03-08 Jan Beulich <jbeulich@suse.com>
816 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
817 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
818 vpexpandd, vpexpandq): Fold AFX512VF templates.
819 * i386-tlb.h: Re-generate.
821 2018-03-08 Jan Beulich <jbeulich@suse.com>
823 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
824 Fold 128- and 256-bit VEX-encoded templates.
825 * i386-tlb.h: Re-generate.
827 2018-03-08 Jan Beulich <jbeulich@suse.com>
829 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
830 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
831 vpexpandd, vpexpandq): Fold AVX512F templates.
832 * i386-tlb.h: Re-generate.
834 2018-03-08 Jan Beulich <jbeulich@suse.com>
836 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
837 64-bit templates. Drop Disp<N>.
838 * i386-tlb.h: Re-generate.
840 2018-03-08 Jan Beulich <jbeulich@suse.com>
842 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
843 and 256-bit templates.
844 * i386-tlb.h: Re-generate.
846 2018-03-08 Jan Beulich <jbeulich@suse.com>
848 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
849 * i386-tlb.h: Re-generate.
851 2018-03-08 Jan Beulich <jbeulich@suse.com>
853 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
855 * i386-tlb.h: Re-generate.
857 2018-03-08 Jan Beulich <jbeulich@suse.com>
859 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
860 * i386-tlb.h: Re-generate.
862 2018-03-08 Jan Beulich <jbeulich@suse.com>
864 * i386-gen.c (opcode_modifiers): Delete FloatD.
865 * i386-opc.h (FloatD): Delete.
866 (struct i386_opcode_modifier): Delete floatd.
867 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
869 * i386-tlb.h: Re-generate.
871 2018-03-08 Jan Beulich <jbeulich@suse.com>
873 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
875 2018-03-08 Jan Beulich <jbeulich@suse.com>
877 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
878 * i386-tlb.h: Re-generate.
880 2018-03-08 Jan Beulich <jbeulich@suse.com>
882 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
884 * i386-tlb.h: Re-generate.
886 2018-03-07 Alan Modra <amodra@gmail.com>
888 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
890 * disassemble.h (print_insn_rs6000): Delete.
891 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
892 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
893 (print_insn_rs6000): Delete.
895 2018-03-03 Alan Modra <amodra@gmail.com>
897 * sysdep.h (opcodes_error_handler): Define.
898 (_bfd_error_handler): Declare.
899 * Makefile.am: Remove stray #.
900 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
902 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
903 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
904 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
905 opcodes_error_handler to print errors. Standardize error messages.
906 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
907 and include opintl.h.
908 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
909 * i386-gen.c: Standardize error messages.
910 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
911 * Makefile.in: Regenerate.
912 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
913 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
914 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
915 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
916 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
917 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
918 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
919 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
920 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
921 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
922 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
923 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
924 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
926 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
928 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
929 vpsub[bwdq] instructions.
930 * i386-tbl.h: Regenerated.
932 2018-03-01 Alan Modra <amodra@gmail.com>
934 * configure.ac (ALL_LINGUAS): Sort.
935 * configure: Regenerate.
937 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
939 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
940 macro by assignements.
942 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
945 * i386-gen.c (opcode_modifiers): Add Optimize.
946 * i386-opc.h (Optimize): New enum.
947 (i386_opcode_modifier): Add optimize.
948 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
949 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
950 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
951 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
952 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
954 * i386-tbl.h: Regenerated.
956 2018-02-26 Alan Modra <amodra@gmail.com>
958 * crx-dis.c (getregliststring): Allocate a large enough buffer
959 to silence false positive gcc8 warning.
961 2018-02-22 Shea Levy <shea@shealevy.com>
963 * disassemble.c (ARCH_riscv): Define if ARCH_all.
965 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
967 * i386-opc.tbl: Add {rex},
968 * i386-tbl.h: Regenerated.
970 2018-02-20 Maciej W. Rozycki <macro@mips.com>
972 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
973 (mips16_opcodes): Replace `M' with `m' for "restore".
975 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
977 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
979 2018-02-13 Maciej W. Rozycki <macro@mips.com>
981 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
982 variable to `function_index'.
984 2018-02-13 Nick Clifton <nickc@redhat.com>
987 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
988 about truncation of printing.
990 2018-02-12 Henry Wong <henry@stuffedcow.net>
992 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
994 2018-02-05 Nick Clifton <nickc@redhat.com>
996 * po/pt_BR.po: Updated Brazilian Portuguese translation.
998 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1000 * i386-dis.c (enum): Add pconfig.
1001 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1002 (cpu_flags): Add CpuPCONFIG.
1003 * i386-opc.h (enum): Add CpuPCONFIG.
1004 (i386_cpu_flags): Add cpupconfig.
1005 * i386-opc.tbl: Add PCONFIG instruction.
1006 * i386-init.h: Regenerate.
1007 * i386-tbl.h: Likewise.
1009 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1011 * i386-dis.c (enum): Add PREFIX_0F09.
1012 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1013 (cpu_flags): Add CpuWBNOINVD.
1014 * i386-opc.h (enum): Add CpuWBNOINVD.
1015 (i386_cpu_flags): Add cpuwbnoinvd.
1016 * i386-opc.tbl: Add WBNOINVD instruction.
1017 * i386-init.h: Regenerate.
1018 * i386-tbl.h: Likewise.
1020 2018-01-17 Jim Wilson <jimw@sifive.com>
1022 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1024 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1026 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1027 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1028 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1029 (cpu_flags): Add CpuIBT, CpuSHSTK.
1030 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1031 (i386_cpu_flags): Add cpuibt, cpushstk.
1032 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1033 * i386-init.h: Regenerate.
1034 * i386-tbl.h: Likewise.
1036 2018-01-16 Nick Clifton <nickc@redhat.com>
1038 * po/pt_BR.po: Updated Brazilian Portugese translation.
1039 * po/de.po: Updated German translation.
1041 2018-01-15 Jim Wilson <jimw@sifive.com>
1043 * riscv-opc.c (match_c_nop): New.
1044 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1046 2018-01-15 Nick Clifton <nickc@redhat.com>
1048 * po/uk.po: Updated Ukranian translation.
1050 2018-01-13 Nick Clifton <nickc@redhat.com>
1052 * po/opcodes.pot: Regenerated.
1054 2018-01-13 Nick Clifton <nickc@redhat.com>
1056 * configure: Regenerate.
1058 2018-01-13 Nick Clifton <nickc@redhat.com>
1060 2.30 branch created.
1062 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1064 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1065 * i386-tbl.h: Regenerate.
1067 2018-01-10 Jan Beulich <jbeulich@suse.com>
1069 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1070 * i386-tbl.h: Re-generate.
1072 2018-01-10 Jan Beulich <jbeulich@suse.com>
1074 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1075 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1076 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1077 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1078 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1079 Disp8MemShift of AVX512VL forms.
1080 * i386-tbl.h: Re-generate.
1082 2018-01-09 Jim Wilson <jimw@sifive.com>
1084 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1085 then the hi_addr value is zero.
1087 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1089 * arm-dis.c (arm_opcodes): Add csdb.
1090 (thumb32_opcodes): Add csdb.
1092 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1094 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1095 * aarch64-asm-2.c: Regenerate.
1096 * aarch64-dis-2.c: Regenerate.
1097 * aarch64-opc-2.c: Regenerate.
1099 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1102 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1103 Remove AVX512 vmovd with 64-bit operands.
1104 * i386-tbl.h: Regenerated.
1106 2018-01-05 Jim Wilson <jimw@sifive.com>
1108 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1111 2018-01-03 Alan Modra <amodra@gmail.com>
1113 Update year range in copyright notice of all files.
1115 2018-01-02 Jan Beulich <jbeulich@suse.com>
1117 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1118 and OPERAND_TYPE_REGZMM entries.
1120 For older changes see ChangeLog-2017
1122 Copyright (C) 2018 Free Software Foundation, Inc.
1124 Copying and distribution of this file, with or without modification,
1125 are permitted in any medium without royalty provided the copyright
1126 notice and this notice are preserved.
1132 version-control: never