opcodes/ChangeLog

   1 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (REG_0F1E_MOD_3): New enum.
   4         (MOD_0F1E_PREFIX_1): Likewise.
   5         (MOD_0F38F5_PREFIX_2): Likewise.
   6         (MOD_0F38F6_PREFIX_0): Likewise.
   7         (RM_0F1E_MOD_3_REG_7): Likewise.
   8         (PREFIX_MOD_0_0F01_REG_5): Likewise.
   9         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  10         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  11         (PREFIX_0F1E): Likewise.
  12         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  13         (PREFIX_0F38F5): Likewise.
  14         (dis386_twobyte): Use PREFIX_0F1E.
  15         (reg_table): Add REG_0F1E_MOD_3.
  16         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  17         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  18         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  19         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  20         (three_byte_table): Use PREFIX_0F38F5.
  21         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  22         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  23         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  24         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  25         PREFIX_MOD_3_0F01_REG_5_RM_2.
  26         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  27         (cpu_flags): Add CpuCET.
  28         * i386-opc.h (CpuCET): New enum.
  29         (CpuUnused): Commented out.
  30         (i386_cpu_flags): Add cpucet.
  31         * i386-opc.tbl: Add Intel CET instructions.
  32         * i386-init.h: Regenerated.
  33         * i386-tbl.h: Likewise.
  34
  35 2017-03-06  Alan Modra  <amodra@gmail.com>
  36
  37         PR 21124
  38         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
  39         (extract_raq, extract_ras, extract_rbx): New functions.
  40         (powerpc_operands): Use opposite corresponding insert function.
  41         (Q_MASK): Define.
  42         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
  43         register restriction.
  44
  45 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  46
  47         * disassemble.c Include "safe-ctype.h".
  48         (disassemble_init_for_target): Handle s390 init.
  49         (remove_whitespace_and_extra_commas): New function.
  50         (disassembler_options_cmp): Likewise.
  51         * arm-dis.c: Include "libiberty.h".
  52         (NUM_ELEM): Delete.
  53         (regnames): Use long disassembler style names.
  54         Add force-thumb and no-force-thumb options.
  55         (NUM_ARM_REGNAMES): Rename from this...
  56         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  57         (get_arm_regname_num_options): Delete.
  58         (set_arm_regname_option): Likewise.
  59         (get_arm_regnames): Likewise.
  60         (parse_disassembler_options): Likewise.
  61         (parse_arm_disassembler_option): Rename from this...
  62         (parse_arm_disassembler_options): ...to this.  Make static.
  63         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
  64         (print_insn): Use parse_arm_disassembler_options.
  65         (disassembler_options_arm): New function.
  66         (print_arm_disassembler_options): Handle updated regnames.
  67         * ppc-dis.c: Include "libiberty.h".
  68         (ppc_opts): Add "32" and "64" entries.
  69         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
  70         (powerpc_init_dialect): Add break to switch statement.
  71         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
  72         (disassembler_options_powerpc): New function.
  73         (print_ppc_disassembler_options): Use ARRAY_SIZE.
  74         Remove printing of "32" and "64".
  75         * s390-dis.c: Include "libiberty.h".
  76         (init_flag): Remove unneeded variable.
  77         (struct s390_options_t): New structure type.
  78         (options): New structure.
  79         (init_disasm): Rename from this...
  80         (disassemble_init_s390): ...to this.  Add initializations for
  81         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
  82         (print_insn_s390): Delete call to init_disasm.
  83         (disassembler_options_s390): New function.
  84         (print_s390_disassembler_options): Print using information from
  85         struct 'options'.
  86         * po/opcodes.pot: Regenerate.
  87
  88 2017-02-28  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-dis.c (PCMPESTR_Fixup): New.
  91         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
  92         (prefix_table): Use PCMPESTR_Fixup.
  93         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
  94         PCMPESTR_Fixup.
  95         (vex_w_table): Delete VPCMPESTR{I,M} entries.
  96         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
  97         Split 64-bit and non-64-bit variants.
  98         * opcodes/i386-tbl.h: Re-generate.
  99
 100 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 101
 102         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 103         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 104         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 105         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 106         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 107         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 108         (OP_SVE_V_HSD): New macros.
 109         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 110         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 111         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 112         (aarch64_opcode_table): Add new SVE instructions.
 113         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 114         for rotation operands.  Add new SVE operands.
 115         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 116         (ins_sve_quad_index): Likewise.
 117         (ins_imm_rotate): Split into...
 118         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 119         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 120         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 121         functions.
 122         (aarch64_ins_sve_addr_ri_s4): New function.
 123         (aarch64_ins_sve_quad_index): Likewise.
 124         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 125         * aarch64-asm-2.c: Regenerate.
 126         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 127         (ext_sve_quad_index): Likewise.
 128         (ext_imm_rotate): Split into...
 129         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 130         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 131         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 132         functions.
 133         (aarch64_ext_sve_addr_ri_s4): New function.
 134         (aarch64_ext_sve_quad_index): Likewise.
 135         (aarch64_ext_sve_index): Allow quad indices.
 136         (do_misc_decoding): Likewise.
 137         * aarch64-dis-2.c: Regenerate.
 138         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 139         aarch64_field_kinds.
 140         (OPD_F_OD_MASK): Widen by one bit.
 141         (OPD_F_NO_ZR): Bump accordingly.
 142         (get_operand_field_width): New function.
 143         * aarch64-opc.c (fields): Add new SVE fields.
 144         (operand_general_constraint_met_p): Handle new SVE operands.
 145         (aarch64_print_operand): Likewise.
 146         * aarch64-opc-2.c: Regenerate.
 147
 148 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 149
 150         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 151         (aarch64_feature_compnum): ...this.
 152         (SIMD_V8_3): Replace with...
 153         (COMPNUM): ...this.
 154         (CNUM_INSN): New macro.
 155         (aarch64_opcode_table): Use it for the complex number instructions.
 156
 157 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 160
 161 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 162
 163         Add support for associating SPARC ASIs with an architecture level.
 164         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 165         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 166         decoding of SPARC ASIs.
 167
 168 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 171         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 172
 173 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 174
 175         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 176         1 (instead of to itself). Correct typo.
 177
 178 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 179
 180         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 181         pseudoinstructions.
 182
 183 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 184
 185         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 186         (aarch64_sys_reg_supported_p): Handle them.
 187
 188 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 189
 190         * arc-opc.c (UIMM6_20R): Define.
 191         (SIMM12_20): Use above.
 192         (SIMM12_20R): Define.
 193         (SIMM3_5_S): Use above.
 194         (UIMM7_A32_11R_S): Define.
 195         (UIMM7_9_S): Use above.
 196         (UIMM3_13R_S): Define.
 197         (SIMM11_A32_7_S): Use above.
 198         (SIMM9_8R): Define.
 199         (UIMM10_A32_8_S): Use above.
 200         (UIMM8_8R_S): Define.
 201         (W6): Use above.
 202         (arc_relax_opcodes): Use all above defines.
 203
 204 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 205
 206         * arc-regs.h: Distinguish some of the registers different on
 207         ARC700 and HS38 cpus.
 208
 209 2017-02-14  Alan Modra  <amodra@gmail.com>
 210
 211         PR 21118
 212         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 213         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 214
 215 2017-02-11  Stafford Horne  <shorne@gmail.com>
 216             Alan Modra  <amodra@gmail.com>
 217
 218         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 219         Use insn_bytes_value and insn_int_value directly instead.  Don't
 220         free allocated memory until function exit.
 221
 222 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 223
 224         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 225
 226 2017-02-03  Nick Clifton  <nickc@redhat.com>
 227
 228         PR 21096
 229         * aarch64-opc.c (print_register_list): Ensure that the register
 230         list index will fir into the tb buffer.
 231         (print_register_offset_address): Likewise.
 232         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 233
 234 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 235
 236         PR 21056
 237         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 238         instructions when the previous fetch packet ends with a 32-bit
 239         instruction.
 240
 241 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 242
 243         * pru-opc.c: Remove vague reference to a future GDB port.
 244
 245 2017-01-20  Nick Clifton  <nickc@redhat.com>
 246
 247         * po/ga.po: Updated Irish translation.
 248
 249 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 250
 251         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 252
 253 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 254
 255         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 256         if FETCH_DATA returns 0.
 257         (m68k_scan_mask): Likewise.
 258         (print_insn_m68k): Update code to handle -1 return value.
 259
 260 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 261
 262         * m68k-dis.c (enum print_insn_arg_error): New.
 263         (NEXTBYTE): Replace -3 with
 264         PRINT_INSN_ARG_MEMORY_ERROR.
 265         (NEXTULONG): Likewise.
 266         (NEXTSINGLE): Likewise.
 267         (NEXTDOUBLE): Likewise.
 268         (NEXTDOUBLE): Likewise.
 269         (NEXTPACKED): Likewise.
 270         (FETCH_ARG): Likewise.
 271         (FETCH_DATA): Update comments.
 272         (print_insn_arg): Update comments. Replace magic numbers with
 273         enum.
 274         (match_insn_m68k): Likewise.
 275
 276 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 277
 278         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 279         * i386-dis-evex.h (evex_table): Updated.
 280         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 281         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 282         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 283         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 284         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 285         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 286         * i386-init.h: Regenerate.
 287         * i386-tbl.h: Ditto.
 288
 289 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 290
 291         * msp430-dis.c (msp430_singleoperand): Return -1 if
 292         msp430dis_opcode_signed returns false.
 293         (msp430_doubleoperand): Likewise.
 294         (msp430_branchinstr): Return -1 if
 295         msp430dis_opcode_unsigned returns false.
 296         (msp430x_calla_instr): Likewise.
 297         (print_insn_msp430): Likewise.
 298
 299 2017-01-05  Nick Clifton  <nickc@redhat.com>
 300
 301         PR 20946
 302         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 303         could not be matched.
 304         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 305         NULL.
 306
 307 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 308
 309         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 310         (aarch64_opcode_table): Use RCPC_INSN.
 311
 312 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 313
 314         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 315         extension.
 316         * riscv-opcodes/all-opcodes: Likewise.
 317
 318 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 319
 320         * riscv-dis.c (print_insn_args): Add fall through comment.
 321
 322 2017-01-03  Nick Clifton  <nickc@redhat.com>
 323
 324         * po/sr.po: New Serbian translation.
 325         * configure.ac (ALL_LINGUAS): Add sr.
 326         * configure: Regenerate.
 327
 328 2017-01-02  Alan Modra  <amodra@gmail.com>
 329
 330         * epiphany-desc.h: Regenerate.
 331         * epiphany-opc.h: Regenerate.
 332         * fr30-desc.h: Regenerate.
 333         * fr30-opc.h: Regenerate.
 334         * frv-desc.h: Regenerate.
 335         * frv-opc.h: Regenerate.
 336         * ip2k-desc.h: Regenerate.
 337         * ip2k-opc.h: Regenerate.
 338         * iq2000-desc.h: Regenerate.
 339         * iq2000-opc.h: Regenerate.
 340         * lm32-desc.h: Regenerate.
 341         * lm32-opc.h: Regenerate.
 342         * m32c-desc.h: Regenerate.
 343         * m32c-opc.h: Regenerate.
 344         * m32r-desc.h: Regenerate.
 345         * m32r-opc.h: Regenerate.
 346         * mep-desc.h: Regenerate.
 347         * mep-opc.h: Regenerate.
 348         * mt-desc.h: Regenerate.
 349         * mt-opc.h: Regenerate.
 350         * or1k-desc.h: Regenerate.
 351         * or1k-opc.h: Regenerate.
 352         * xc16x-desc.h: Regenerate.
 353         * xc16x-opc.h: Regenerate.
 354         * xstormy16-desc.h: Regenerate.
 355         * xstormy16-opc.h: Regenerate.
 356
 357 2017-01-02  Alan Modra  <amodra@gmail.com>
 358
 359         Update year range in copyright notice of all files.
 360
 361 For older changes see ChangeLog-2016
 362 \f
 363 Copyright (C) 2017 Free Software Foundation, Inc.
 364
 365 Copying and distribution of this file, with or without modification,
 366 are permitted in any medium without royalty provided the copyright
 367 notice and this notice are preserved.
 368
 369 Local Variables:
 370 mode: change-log
 371 left-margin: 8
 372 fill-column: 74
 373 version-control: never
 374 End: