1 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
3 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
5 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
7 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
9 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
11 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
13 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
15 2020-05-11 Alan Modra <amodra@gmail.com>
17 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
19 2020-05-11 Alan Modra <amodra@gmail.com>
21 * ppc-dis.c (ppc_opts): Add "power10" entry.
22 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
23 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
25 2020-05-11 Nick Clifton <nickc@redhat.com>
27 * po/fr.po: Updated French translation.
29 2020-04-30 Alex Coplan <alex.coplan@arm.com>
31 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
32 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
33 (operand_general_constraint_met_p): validate
34 AARCH64_OPND_UNDEFINED.
35 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
37 * aarch64-asm-2.c: Regenerated.
38 * aarch64-dis-2.c: Regenerated.
39 * aarch64-opc-2.c: Regenerated.
41 2020-04-29 Nick Clifton <nickc@redhat.com>
44 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
47 2020-04-29 Nick Clifton <nickc@redhat.com>
49 * po/sv.po: Updated Swedish translation.
51 2020-04-29 Nick Clifton <nickc@redhat.com>
54 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
55 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
56 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
59 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
62 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
63 cmpi only on m68020up and cpu32.
65 2020-04-20 Sudakshina Das <sudi.das@arm.com>
67 * aarch64-asm.c (aarch64_ins_none): New.
68 * aarch64-asm.h (ins_none): New declaration.
69 * aarch64-dis.c (aarch64_ext_none): New.
70 * aarch64-dis.h (ext_none): New declaration.
71 * aarch64-opc.c (aarch64_print_operand): Update case for
72 AARCH64_OPND_BARRIER_PSB.
73 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
74 (AARCH64_OPERANDS): Update inserter/extracter for
75 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
76 * aarch64-asm-2.c: Regenerated.
77 * aarch64-dis-2.c: Regenerated.
78 * aarch64-opc-2.c: Regenerated.
80 2020-04-20 Sudakshina Das <sudi.das@arm.com>
82 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
83 (aarch64_feature_ras, RAS): Likewise.
84 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
85 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
86 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
87 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
88 * aarch64-asm-2.c: Regenerated.
89 * aarch64-dis-2.c: Regenerated.
90 * aarch64-opc-2.c: Regenerated.
92 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
94 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
95 (print_insn_neon): Support disassembly of conditional
98 2020-02-16 David Faust <david.faust@oracle.com>
100 * bpf-desc.c: Regenerate.
101 * bpf-desc.h: Likewise.
102 * bpf-opc.c: Regenerate.
103 * bpf-opc.h: Likewise.
105 2020-04-07 Lili Cui <lili.cui@intel.com>
107 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
108 (prefix_table): New instructions (see prefixes above).
110 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
111 CPU_ANY_TSXLDTRK_FLAGS.
112 (cpu_flags): Add CpuTSXLDTRK.
113 * i386-opc.h (enum): Add CpuTSXLDTRK.
114 (i386_cpu_flags): Add cputsxldtrk.
115 * i386-opc.tbl: Add XSUSPLDTRK insns.
116 * i386-init.h: Regenerate.
117 * i386-tbl.h: Likewise.
119 2020-04-02 Lili Cui <lili.cui@intel.com>
121 * i386-dis.c (prefix_table): New instructions serialize.
122 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
123 CPU_ANY_SERIALIZE_FLAGS.
124 (cpu_flags): Add CpuSERIALIZE.
125 * i386-opc.h (enum): Add CpuSERIALIZE.
126 (i386_cpu_flags): Add cpuserialize.
127 * i386-opc.tbl: Add SERIALIZE insns.
128 * i386-init.h: Regenerate.
129 * i386-tbl.h: Likewise.
131 2020-03-26 Alan Modra <amodra@gmail.com>
133 * disassemble.h (opcodes_assert): Declare.
134 (OPCODES_ASSERT): Define.
135 * disassemble.c: Don't include assert.h. Include opintl.h.
136 (opcodes_assert): New function.
137 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
138 (bfd_h8_disassemble): Reduce size of data array. Correctly
139 calculate maxlen. Omit insn decoding when insn length exceeds
140 maxlen. Exit from nibble loop when looking for E, before
141 accessing next data byte. Move processing of E outside loop.
142 Replace tests of maxlen in loop with assertions.
144 2020-03-26 Alan Modra <amodra@gmail.com>
146 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
148 2020-03-25 Alan Modra <amodra@gmail.com>
150 * z80-dis.c (suffix): Init mybuf.
152 2020-03-22 Alan Modra <amodra@gmail.com>
154 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
155 successflly read from section.
157 2020-03-22 Alan Modra <amodra@gmail.com>
159 * arc-dis.c (find_format): Use ISO C string concatenation rather
160 than line continuation within a string. Don't access needs_limm
161 before testing opcode != NULL.
163 2020-03-22 Alan Modra <amodra@gmail.com>
165 * ns32k-dis.c (print_insn_arg): Update comment.
166 (print_insn_ns32k): Reduce size of index_offset array, and
167 initialize, passing -1 to print_insn_arg for args that are not
168 an index. Don't exit arg loop early. Abort on bad arg number.
170 2020-03-22 Alan Modra <amodra@gmail.com>
172 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
173 * s12z-opc.c: Formatting.
174 (operands_f): Return an int.
175 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
176 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
177 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
178 (exg_sex_discrim): Likewise.
179 (create_immediate_operand, create_bitfield_operand),
180 (create_register_operand_with_size, create_register_all_operand),
181 (create_register_all16_operand, create_simple_memory_operand),
182 (create_memory_operand, create_memory_auto_operand): Don't
183 segfault on malloc failure.
184 (z_ext24_decode): Return an int status, negative on fail, zero
186 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
187 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
188 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
189 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
190 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
191 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
192 (loop_primitive_decode, shift_decode, psh_pul_decode),
193 (bit_field_decode): Similarly.
194 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
195 to return value, update callers.
196 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
197 Don't segfault on NULL operand.
198 (decode_operation): Return OP_INVALID on first fail.
199 (decode_s12z): Check all reads, returning -1 on fail.
201 2020-03-20 Alan Modra <amodra@gmail.com>
203 * metag-dis.c (print_insn_metag): Don't ignore status from
206 2020-03-20 Alan Modra <amodra@gmail.com>
208 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
209 Initialize parts of buffer not written when handling a possible
210 2-byte insn at end of section. Don't attempt decoding of such
211 an insn by the 4-byte machinery.
213 2020-03-20 Alan Modra <amodra@gmail.com>
215 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
216 partially filled buffer. Prevent lookup of 4-byte insns when
217 only VLE 2-byte insns are possible due to section size. Print
218 ".word" rather than ".long" for 2-byte leftovers.
220 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
223 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
225 2020-03-13 Jan Beulich <jbeulich@suse.com>
227 * i386-dis.c (X86_64_0D): Rename to ...
228 (X86_64_0E): ... this.
230 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
232 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
233 * Makefile.in: Regenerated.
235 2020-03-09 Jan Beulich <jbeulich@suse.com>
237 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
239 * i386-tbl.h: Re-generate.
241 2020-03-09 Jan Beulich <jbeulich@suse.com>
243 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
244 vprot*, vpsha*, and vpshl*.
245 * i386-tbl.h: Re-generate.
247 2020-03-09 Jan Beulich <jbeulich@suse.com>
249 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
250 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
251 * i386-tbl.h: Re-generate.
253 2020-03-09 Jan Beulich <jbeulich@suse.com>
255 * i386-gen.c (set_bitfield): Ignore zero-length field names.
256 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
257 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
258 * i386-tbl.h: Re-generate.
260 2020-03-09 Jan Beulich <jbeulich@suse.com>
262 * i386-gen.c (struct template_arg, struct template_instance,
263 struct template_param, struct template, templates,
264 parse_template, expand_templates): New.
265 (process_i386_opcodes): Various local variables moved to
266 expand_templates. Call parse_template and expand_templates.
267 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
268 * i386-tbl.h: Re-generate.
270 2020-03-06 Jan Beulich <jbeulich@suse.com>
272 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
273 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
274 register and memory source templates. Replace VexW= by VexW*
276 * i386-tbl.h: Re-generate.
278 2020-03-06 Jan Beulich <jbeulich@suse.com>
280 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
281 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
282 * i386-tbl.h: Re-generate.
284 2020-03-06 Jan Beulich <jbeulich@suse.com>
286 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
287 * i386-tbl.h: Re-generate.
289 2020-03-06 Jan Beulich <jbeulich@suse.com>
291 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
292 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
293 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
294 VexW0 on SSE2AVX variants.
295 (vmovq): Drop NoRex64 from XMM/XMM variants.
296 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
297 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
298 applicable use VexW0.
299 * i386-tbl.h: Re-generate.
301 2020-03-06 Jan Beulich <jbeulich@suse.com>
303 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
304 * i386-opc.h (Rex64): Delete.
305 (struct i386_opcode_modifier): Remove rex64 field.
306 * i386-opc.tbl (crc32): Drop Rex64.
307 Replace Rex64 with Size64 everywhere else.
308 * i386-tbl.h: Re-generate.
310 2020-03-06 Jan Beulich <jbeulich@suse.com>
312 * i386-dis.c (OP_E_memory): Exclude recording of used address
313 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
314 addressed memory operands for MPX insns.
316 2020-03-06 Jan Beulich <jbeulich@suse.com>
318 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
319 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
320 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
321 (ptwrite): Split into non-64-bit and 64-bit forms.
322 * i386-tbl.h: Re-generate.
324 2020-03-06 Jan Beulich <jbeulich@suse.com>
326 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
328 * i386-tbl.h: Re-generate.
330 2020-03-04 Jan Beulich <jbeulich@suse.com>
332 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
333 (prefix_table): Move vmmcall here. Add vmgexit.
334 (rm_table): Replace vmmcall entry by prefix_table[] escape.
335 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
336 (cpu_flags): Add CpuSEV_ES entry.
337 * i386-opc.h (CpuSEV_ES): New.
338 (union i386_cpu_flags): Add cpusev_es field.
339 * i386-opc.tbl (vmgexit): New.
340 * i386-init.h, i386-tbl.h: Re-generate.
342 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
344 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
346 * i386-opc.h (IGNORESIZE): New.
347 (DEFAULTSIZE): Likewise.
348 (IgnoreSize): Removed.
349 (DefaultSize): Likewise.
351 (i386_opcode_modifier): Replace ignoresize/defaultsize with
353 * i386-opc.tbl (IgnoreSize): New.
354 (DefaultSize): Likewise.
355 * i386-tbl.h: Regenerated.
357 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
360 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
363 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
366 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
367 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
368 * i386-tbl.h: Regenerated.
370 2020-02-26 Alan Modra <amodra@gmail.com>
372 * aarch64-asm.c: Indent labels correctly.
373 * aarch64-dis.c: Likewise.
374 * aarch64-gen.c: Likewise.
375 * aarch64-opc.c: Likewise.
376 * alpha-dis.c: Likewise.
377 * i386-dis.c: Likewise.
378 * nds32-asm.c: Likewise.
379 * nfp-dis.c: Likewise.
380 * visium-dis.c: Likewise.
382 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
384 * arc-regs.h (int_vector_base): Make it available for all ARC
387 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
389 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
392 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
394 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
395 c.mv/c.li if rs1 is zero.
397 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
399 * i386-gen.c (cpu_flag_init): Replace CpuABM with
400 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
402 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
403 * i386-opc.h (CpuABM): Removed.
405 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
406 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
407 popcnt. Remove CpuABM from lzcnt.
408 * i386-init.h: Regenerated.
409 * i386-tbl.h: Likewise.
411 2020-02-17 Jan Beulich <jbeulich@suse.com>
413 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
414 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
415 VexW1 instead of open-coding them.
416 * i386-tbl.h: Re-generate.
418 2020-02-17 Jan Beulich <jbeulich@suse.com>
420 * i386-opc.tbl (AddrPrefixOpReg): Define.
421 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
422 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
423 templates. Drop NoRex64.
424 * i386-tbl.h: Re-generate.
426 2020-02-17 Jan Beulich <jbeulich@suse.com>
429 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
430 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
431 into Intel syntax instance (with Unpsecified) and AT&T one
433 (vcvtneps2bf16): Likewise, along with folding the two so far
435 * i386-tbl.h: Re-generate.
437 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
439 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
442 2020-02-17 Alan Modra <amodra@gmail.com>
444 * i386-gen.c (cpu_flag_init): Correct last change.
446 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
448 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
451 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
453 * i386-opc.tbl (movsx): Remove Intel syntax comments.
456 2020-02-14 Jan Beulich <jbeulich@suse.com>
459 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
460 destination for Cpu64-only variant.
461 (movzx): Fold patterns.
462 * i386-tbl.h: Re-generate.
464 2020-02-13 Jan Beulich <jbeulich@suse.com>
466 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
467 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
468 CPU_ANY_SSE4_FLAGS entry.
469 * i386-init.h: Re-generate.
471 2020-02-12 Jan Beulich <jbeulich@suse.com>
473 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
474 with Unspecified, making the present one AT&T syntax only.
475 * i386-tbl.h: Re-generate.
477 2020-02-12 Jan Beulich <jbeulich@suse.com>
479 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
480 * i386-tbl.h: Re-generate.
482 2020-02-12 Jan Beulich <jbeulich@suse.com>
485 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
486 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
487 Amd64 and Intel64 templates.
488 (call, jmp): Likewise for far indirect variants. Dro
490 * i386-tbl.h: Re-generate.
492 2020-02-11 Jan Beulich <jbeulich@suse.com>
494 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
495 * i386-opc.h (ShortForm): Delete.
496 (struct i386_opcode_modifier): Remove shortform field.
497 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
498 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
499 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
500 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
502 * i386-tbl.h: Re-generate.
504 2020-02-11 Jan Beulich <jbeulich@suse.com>
506 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
507 fucompi): Drop ShortForm from operand-less templates.
508 * i386-tbl.h: Re-generate.
510 2020-02-11 Alan Modra <amodra@gmail.com>
512 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
513 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
514 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
515 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
516 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
518 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
520 * arm-dis.c (print_insn_cde): Define 'V' parse character.
521 (cde_opcodes): Add VCX* instructions.
523 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
524 Matthew Malcomson <matthew.malcomson@arm.com>
526 * arm-dis.c (struct cdeopcode32): New.
527 (CDE_OPCODE): New macro.
528 (cde_opcodes): New disassembly table.
529 (regnames): New option to table.
530 (cde_coprocs): New global variable.
531 (print_insn_cde): New
532 (print_insn_thumb32): Use print_insn_cde.
533 (parse_arm_disassembler_options): Parse coprocN args.
535 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
538 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
540 * i386-opc.h (AMD64): Removed.
544 (INTEL64ONLY): Likewise.
545 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
546 * i386-opc.tbl (Amd64): New.
548 (Intel64Only): Likewise.
549 Replace AMD64 with Amd64. Update sysenter/sysenter with
550 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
551 * i386-tbl.h: Regenerated.
553 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
556 * z80-dis.c: Add support for GBZ80 opcodes.
558 2020-02-04 Alan Modra <amodra@gmail.com>
560 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
562 2020-02-03 Alan Modra <amodra@gmail.com>
564 * m32c-ibld.c: Regenerate.
566 2020-02-01 Alan Modra <amodra@gmail.com>
568 * frv-ibld.c: Regenerate.
570 2020-01-31 Jan Beulich <jbeulich@suse.com>
572 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
573 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
574 (OP_E_memory): Replace xmm_mdq_mode case label by
575 vex_scalar_w_dq_mode one.
576 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
578 2020-01-31 Jan Beulich <jbeulich@suse.com>
580 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
581 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
582 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
583 (intel_operand_size): Drop vex_w_dq_mode case label.
585 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
587 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
588 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
590 2020-01-30 Alan Modra <amodra@gmail.com>
592 * m32c-ibld.c: Regenerate.
594 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
596 * bpf-opc.c: Regenerate.
598 2020-01-30 Jan Beulich <jbeulich@suse.com>
600 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
601 (dis386): Use them to replace C2/C3 table entries.
602 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
603 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
604 ones. Use Size64 instead of DefaultSize on Intel64 ones.
605 * i386-tbl.h: Re-generate.
607 2020-01-30 Jan Beulich <jbeulich@suse.com>
609 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
611 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
613 * i386-tbl.h: Re-generate.
615 2020-01-30 Alan Modra <amodra@gmail.com>
617 * tic4x-dis.c (tic4x_dp): Make unsigned.
619 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
620 Jan Beulich <jbeulich@suse.com>
623 * i386-dis.c (MOVSXD_Fixup): New function.
624 (movsxd_mode): New enum.
625 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
626 (intel_operand_size): Handle movsxd_mode.
627 (OP_E_register): Likewise.
629 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
630 register on movsxd. Add movsxd with 16-bit destination register
631 for AMD64 and Intel64 ISAs.
632 * i386-tbl.h: Regenerated.
634 2020-01-27 Tamar Christina <tamar.christina@arm.com>
637 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
638 * aarch64-asm-2.c: Regenerate
639 * aarch64-dis-2.c: Likewise.
640 * aarch64-opc-2.c: Likewise.
642 2020-01-21 Jan Beulich <jbeulich@suse.com>
644 * i386-opc.tbl (sysret): Drop DefaultSize.
645 * i386-tbl.h: Re-generate.
647 2020-01-21 Jan Beulich <jbeulich@suse.com>
649 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
651 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
652 * i386-tbl.h: Re-generate.
654 2020-01-20 Nick Clifton <nickc@redhat.com>
656 * po/de.po: Updated German translation.
657 * po/pt_BR.po: Updated Brazilian Portuguese translation.
658 * po/uk.po: Updated Ukranian translation.
660 2020-01-20 Alan Modra <amodra@gmail.com>
662 * hppa-dis.c (fput_const): Remove useless cast.
664 2020-01-20 Alan Modra <amodra@gmail.com>
666 * arm-dis.c (print_insn_arm): Wrap 'T' value.
668 2020-01-18 Nick Clifton <nickc@redhat.com>
670 * configure: Regenerate.
671 * po/opcodes.pot: Regenerate.
673 2020-01-18 Nick Clifton <nickc@redhat.com>
675 Binutils 2.34 branch created.
677 2020-01-17 Christian Biesinger <cbiesinger@google.com>
679 * opintl.h: Fix spelling error (seperate).
681 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
683 * i386-opc.tbl: Add {vex} pseudo prefix.
684 * i386-tbl.h: Regenerated.
686 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
689 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
690 (neon_opcodes): Likewise.
691 (select_arm_features): Make sure we enable MVE bits when selecting
692 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
695 2020-01-16 Jan Beulich <jbeulich@suse.com>
697 * i386-opc.tbl: Drop stale comment from XOP section.
699 2020-01-16 Jan Beulich <jbeulich@suse.com>
701 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
702 (extractps): Add VexWIG to SSE2AVX forms.
703 * i386-tbl.h: Re-generate.
705 2020-01-16 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
708 Size64 from and use VexW1 on SSE2AVX forms.
709 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
710 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
711 * i386-tbl.h: Re-generate.
713 2020-01-15 Alan Modra <amodra@gmail.com>
715 * tic4x-dis.c (tic4x_version): Make unsigned long.
716 (optab, optab_special, registernames): New file scope vars.
717 (tic4x_print_register): Set up registernames rather than
718 malloc'd registertable.
719 (tic4x_disassemble): Delete optable and optable_special. Use
720 optab and optab_special instead. Throw away old optab,
721 optab_special and registernames when info->mach changes.
723 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
726 * z80-dis.c (suffix): Use .db instruction to generate double
729 2020-01-14 Alan Modra <amodra@gmail.com>
731 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
732 values to unsigned before shifting.
734 2020-01-13 Thomas Troeger <tstroege@gmx.de>
736 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
738 (print_insn_thumb16, print_insn_thumb32): Likewise.
739 (print_insn): Initialize the insn info.
740 * i386-dis.c (print_insn): Initialize the insn info fields, and
743 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
745 * arc-opc.c (C_NE): Make it required.
747 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
749 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
750 reserved register name.
752 2020-01-13 Alan Modra <amodra@gmail.com>
754 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
755 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
757 2020-01-13 Alan Modra <amodra@gmail.com>
759 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
760 result of wasm_read_leb128 in a uint64_t and check that bits
761 are not lost when copying to other locals. Use uint32_t for
762 most locals. Use PRId64 when printing int64_t.
764 2020-01-13 Alan Modra <amodra@gmail.com>
766 * score-dis.c: Formatting.
767 * score7-dis.c: Formatting.
769 2020-01-13 Alan Modra <amodra@gmail.com>
771 * score-dis.c (print_insn_score48): Use unsigned variables for
772 unsigned values. Don't left shift negative values.
773 (print_insn_score32): Likewise.
774 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
776 2020-01-13 Alan Modra <amodra@gmail.com>
778 * tic4x-dis.c (tic4x_print_register): Remove dead code.
780 2020-01-13 Alan Modra <amodra@gmail.com>
782 * fr30-ibld.c: Regenerate.
784 2020-01-13 Alan Modra <amodra@gmail.com>
786 * xgate-dis.c (print_insn): Don't left shift signed value.
787 (ripBits): Formatting, use 1u.
789 2020-01-10 Alan Modra <amodra@gmail.com>
791 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
792 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
794 2020-01-10 Alan Modra <amodra@gmail.com>
796 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
797 and XRREG value earlier to avoid a shift with negative exponent.
798 * m10200-dis.c (disassemble): Similarly.
800 2020-01-09 Nick Clifton <nickc@redhat.com>
803 * z80-dis.c (ld_ii_ii): Use correct cast.
805 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
808 * z80-dis.c (ld_ii_ii): Use character constant when checking
811 2020-01-09 Jan Beulich <jbeulich@suse.com>
813 * i386-dis.c (SEP_Fixup): New.
815 (dis386_twobyte): Use it for sysenter/sysexit.
816 (enum x86_64_isa): Change amd64 enumerator to value 1.
817 (OP_J): Compare isa64 against intel64 instead of amd64.
818 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
820 * i386-tbl.h: Re-generate.
822 2020-01-08 Alan Modra <amodra@gmail.com>
824 * z8k-dis.c: Include libiberty.h
825 (instr_data_s): Make max_fetched unsigned.
826 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
827 Don't exceed byte_info bounds.
828 (output_instr): Make num_bytes unsigned.
829 (unpack_instr): Likewise for nibl_count and loop.
830 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
832 * z8k-opc.h: Regenerate.
834 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
836 * arc-tbl.h (llock): Use 'LLOCK' as class.
838 (scond): Use 'SCOND' as class.
840 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
843 2020-01-06 Alan Modra <amodra@gmail.com>
845 * m32c-ibld.c: Regenerate.
847 2020-01-06 Alan Modra <amodra@gmail.com>
850 * z80-dis.c (suffix): Don't use a local struct buffer copy.
851 Peek at next byte to prevent recursion on repeated prefix bytes.
852 Ensure uninitialised "mybuf" is not accessed.
853 (print_insn_z80): Don't zero n_fetch and n_used here,..
854 (print_insn_z80_buf): ..do it here instead.
856 2020-01-04 Alan Modra <amodra@gmail.com>
858 * m32r-ibld.c: Regenerate.
860 2020-01-04 Alan Modra <amodra@gmail.com>
862 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
864 2020-01-04 Alan Modra <amodra@gmail.com>
866 * crx-dis.c (match_opcode): Avoid shift left of signed value.
868 2020-01-04 Alan Modra <amodra@gmail.com>
870 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
872 2020-01-03 Jan Beulich <jbeulich@suse.com>
874 * aarch64-tbl.h (aarch64_opcode_table): Use
875 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
877 2020-01-03 Jan Beulich <jbeulich@suse.com>
879 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
880 forms of SUDOT and USDOT.
882 2020-01-03 Jan Beulich <jbeulich@suse.com>
884 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
886 * opcodes/aarch64-dis-2.c: Re-generate.
888 2020-01-03 Jan Beulich <jbeulich@suse.com>
890 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
892 * opcodes/aarch64-dis-2.c: Re-generate.
894 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
896 * z80-dis.c: Add support for eZ80 and Z80 instructions.
898 2020-01-01 Alan Modra <amodra@gmail.com>
900 Update year range in copyright notice of all files.
902 For older changes see ChangeLog-2019
904 Copyright (C) 2020 Free Software Foundation, Inc.
906 Copying and distribution of this file, with or without modification,
907 are permitted in any medium without royalty provided the copyright
908 notice and this notice are preserved.
914 version-control: never