1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
5 * i386-tbl.h: Re-generate.
7 2018-09-13 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
10 * i386-tbl.h: Re-generate.
12 2018-09-13 Jan Beulich <jbeulich@suse.com>
14 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
15 * i386-tbl.h: Re-generate.
17 2018-09-13 Jan Beulich <jbeulich@suse.com>
19 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
20 * i386-tbl.h: Re-generate.
22 2018-09-13 Jan Beulich <jbeulich@suse.com>
24 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
26 * i386-tbl.h: Re-generate.
28 2018-09-13 Jan Beulich <jbeulich@suse.com>
30 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
32 * i386-tbl.h: Re-generate.
34 2018-09-13 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
38 * i386-tbl.h: Re-generate.
40 2018-09-13 Jan Beulich <jbeulich@suse.com>
42 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
43 * i386-tbl.h: Re-generate.
45 2018-09-13 Jan Beulich <jbeulich@suse.com>
47 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
48 * i386-tbl.h: Re-generate.
50 2018-09-13 Jan Beulich <jbeulich@suse.com>
52 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
53 * i386-tbl.h: Re-generate.
55 2018-09-13 Jan Beulich <jbeulich@suse.com>
57 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
58 (vpbroadcastw, rdpid): Drop NoRex64.
59 * i386-tbl.h: Re-generate.
61 2018-09-13 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
64 store templates, adding D.
65 * i386-tbl.h: Re-generate.
67 2018-09-13 Jan Beulich <jbeulich@suse.com>
69 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
70 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
71 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
72 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
73 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
74 Fold load and store templates where possible, adding D. Drop
75 IgnoreSize where it was pointlessly present. Drop redundant
77 * i386-tbl.h: Re-generate.
79 2018-09-13 Jan Beulich <jbeulich@suse.com>
81 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
82 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
83 (intel_operand_size): Handle v_bndmk_mode.
84 (OP_E_memory): Likewise. Produce (bad) when also riprel.
86 2018-09-08 John Darrington <john@darrington.wattle.id.au>
88 * disassemble.c (ARCH_s12z): Define if ARCH_all.
90 2018-08-31 Kito Cheng <kito@andestech.com>
92 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
93 compressed floating point instructions.
95 2018-08-30 Kito Cheng <kito@andestech.com>
97 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
98 riscv_opcode.xlen_requirement.
99 * riscv-opc.c (riscv_opcodes): Update for struct change.
101 2018-08-29 Martin Aberg <maberg@gaisler.com>
103 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
104 psr (PWRPSR) instruction.
106 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
108 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
110 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
112 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
114 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
116 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
117 loongson3a as an alias of gs464 for compatibility.
118 * mips-opc.c (mips_opcodes): Change Comments.
120 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
122 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
124 (print_mips_disassembler_options): Document -M loongson-ext.
125 * mips-opc.c (LEXT2): New macro.
126 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
128 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
130 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
132 (parse_mips_ase_option): Handle -M loongson-ext option.
133 (print_mips_disassembler_options): Document -M loongson-ext.
134 * mips-opc.c (IL3A): Delete.
135 * mips-opc.c (LEXT): New macro.
136 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
139 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
141 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
143 (parse_mips_ase_option): Handle -M loongson-cam option.
144 (print_mips_disassembler_options): Document -M loongson-cam.
145 * mips-opc.c (LCAM): New macro.
146 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
149 2018-08-21 Alan Modra <amodra@gmail.com>
151 * ppc-dis.c (operand_value_powerpc): Init "invalid".
152 (skip_optional_operands): Count optional operands, and update
153 ppc_optional_operand_value call.
154 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
155 (extract_vlensi): Likewise.
156 (extract_fxm): Return default value for missing optional operand.
157 (extract_ls, extract_raq, extract_tbr): Likewise.
158 (insert_sxl, extract_sxl): New functions.
159 (insert_esync, extract_esync): Remove Power9 handling and simplify.
160 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
161 flag and extra entry.
162 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
165 2018-08-20 Alan Modra <amodra@gmail.com>
167 * sh-opc.h (MASK): Simplify.
169 2018-08-18 John Darrington <john@darrington.wattle.id.au>
171 * s12z-dis.c (bm_decode): Deal with cases where the mode is
172 BM_RESERVED0 or BM_RESERVED1
173 (bm_rel_decode, bm_n_bytes): Ditto.
175 2018-08-18 John Darrington <john@darrington.wattle.id.au>
179 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
181 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
182 address with the addr32 prefix and without base nor index
185 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
187 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
188 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
189 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
190 (cpu_flags): Add CpuCMOV and CpuFXSR.
191 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
192 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
193 * i386-init.h: Regenerated.
194 * i386-tbl.h: Likewise.
196 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
198 * arc-regs.h: Update auxiliary registers.
200 2018-08-06 Jan Beulich <jbeulich@suse.com>
202 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
203 (RegIP, RegIZ): Define.
204 * i386-reg.tbl: Adjust comments.
205 (rip): Use Qword instead of BaseIndex. Use RegIP.
206 (eip): Use Dword instead of BaseIndex. Use RegIP.
207 (riz): Add Qword. Use RegIZ.
208 (eiz): Add Dword. Use RegIZ.
209 * i386-tbl.h: Re-generate.
211 2018-08-03 Jan Beulich <jbeulich@suse.com>
213 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
214 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
215 vpmovzxdq, vpmovzxwd): Remove NoRex64.
216 * i386-tbl.h: Re-generate.
218 2018-08-03 Jan Beulich <jbeulich@suse.com>
220 * i386-gen.c (operand_types): Remove Mem field.
221 * i386-opc.h (union i386_operand_type): Remove mem field.
222 * i386-init.h, i386-tbl.h: Re-generate.
224 2018-08-01 Alan Modra <amodra@gmail.com>
226 * po/POTFILES.in: Regenerate.
228 2018-07-31 Nick Clifton <nickc@redhat.com>
230 * po/sv.po: Updated Swedish translation.
232 2018-07-31 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
235 * i386-init.h, i386-tbl.h: Re-generate.
237 2018-07-31 Jan Beulich <jbeulich@suse.com>
239 * i386-opc.h (ZEROING_MASKING) Rename to ...
240 (DYNAMIC_MASKING): ... this. Adjust comment.
241 * i386-opc.tbl (MaskingMorZ): Define.
242 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
243 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
244 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
245 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
246 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
247 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
248 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
249 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
250 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
252 2018-07-31 Jan Beulich <jbeulich@suse.com>
254 * i386-opc.tbl: Use element rather than vector size for AVX512*
255 scatter/gather insns.
256 * i386-tbl.h: Re-generate.
258 2018-07-31 Jan Beulich <jbeulich@suse.com>
260 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
261 (cpu_flags): Drop CpuVREX.
262 * i386-opc.h (CpuVREX): Delete.
263 (union i386_cpu_flags): Remove cpuvrex.
264 * i386-init.h, i386-tbl.h: Re-generate.
266 2018-07-30 Jim Wilson <jimw@sifive.com>
268 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
270 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
272 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
274 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
275 * Makefile.in: Regenerated.
276 * configure.ac: Add C-SKY.
277 * configure: Regenerated.
278 * csky-dis.c: New file.
279 * csky-opc.h: New file.
280 * disassemble.c (ARCH_csky): Define.
281 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
282 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
284 2018-07-27 Alan Modra <amodra@gmail.com>
286 * ppc-opc.c (insert_sprbat): Correct function parameter and
288 (extract_sprbat): Likewise, variable too.
290 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
291 Alan Modra <amodra@gmail.com>
293 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
294 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
295 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
296 support disjointed BAT.
297 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
298 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
299 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
301 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
302 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
304 * i386-gen.c (adjust_broadcast_modifier): New function.
305 (process_i386_opcode_modifier): Add an argument for operands.
306 Adjust the Broadcast value based on operands.
307 (output_i386_opcode): Pass operand_types to
308 process_i386_opcode_modifier.
309 (process_i386_opcodes): Pass NULL as operands to
310 process_i386_opcode_modifier.
311 * i386-opc.h (BYTE_BROADCAST): New.
312 (WORD_BROADCAST): Likewise.
313 (DWORD_BROADCAST): Likewise.
314 (QWORD_BROADCAST): Likewise.
315 (i386_opcode_modifier): Expand broadcast to 3 bits.
316 * i386-tbl.h: Regenerated.
318 2018-07-24 Alan Modra <amodra@gmail.com>
321 * or1k-desc.h: Regenerate.
323 2018-07-24 Jan Beulich <jbeulich@suse.com>
325 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
326 vcvtusi2ss, and vcvtusi2sd.
327 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
328 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
329 * i386-tbl.h: Re-generate.
331 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
333 * arc-opc.c (extract_w6): Fix extending the sign.
335 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
337 * arc-tbl.h (vewt): Allow it for ARC EM family.
339 2018-07-23 Alan Modra <amodra@gmail.com>
342 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
343 opcode variants for mtspr/mfspr encodings.
345 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
346 Maciej W. Rozycki <macro@mips.com>
348 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
349 loongson3a descriptors.
350 (parse_mips_ase_option): Handle -M loongson-mmi option.
351 (print_mips_disassembler_options): Document -M loongson-mmi.
352 * mips-opc.c (LMMI): New macro.
353 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
356 2018-07-19 Jan Beulich <jbeulich@suse.com>
358 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
359 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
360 IgnoreSize and [XYZ]MMword where applicable.
361 * i386-tbl.h: Re-generate.
363 2018-07-19 Jan Beulich <jbeulich@suse.com>
365 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
366 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
367 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
368 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
369 * i386-tbl.h: Re-generate.
371 2018-07-19 Jan Beulich <jbeulich@suse.com>
373 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
374 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
375 VPCLMULQDQ templates into their respective AVX512VL counterparts
376 where possible, using Disp8ShiftVL and CheckRegSize instead of
377 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
378 * i386-tbl.h: Re-generate.
380 2018-07-19 Jan Beulich <jbeulich@suse.com>
382 * i386-opc.tbl: Fold AVX512DQ templates into their respective
383 AVX512VL counterparts where possible, using Disp8ShiftVL and
384 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
385 IgnoreSize) as appropriate.
386 * i386-tbl.h: Re-generate.
388 2018-07-19 Jan Beulich <jbeulich@suse.com>
390 * i386-opc.tbl: Fold AVX512BW templates into their respective
391 AVX512VL counterparts where possible, using Disp8ShiftVL and
392 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
393 IgnoreSize) as appropriate.
394 * i386-tbl.h: Re-generate.
396 2018-07-19 Jan Beulich <jbeulich@suse.com>
398 * i386-opc.tbl: Fold AVX512CD templates into their respective
399 AVX512VL counterparts where possible, using Disp8ShiftVL and
400 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
401 IgnoreSize) as appropriate.
402 * i386-tbl.h: Re-generate.
404 2018-07-19 Jan Beulich <jbeulich@suse.com>
406 * i386-opc.h (DISP8_SHIFT_VL): New.
407 * i386-opc.tbl (Disp8ShiftVL): Define.
408 (various): Fold AVX512VL templates into their respective
409 AVX512F counterparts where possible, using Disp8ShiftVL and
410 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
411 IgnoreSize) as appropriate.
412 * i386-tbl.h: Re-generate.
414 2018-07-19 Jan Beulich <jbeulich@suse.com>
416 * Makefile.am: Change dependencies and rule for
417 $(srcdir)/i386-init.h.
418 * Makefile.in: Re-generate.
419 * i386-gen.c (process_i386_opcodes): New local variable
420 "marker". Drop opening of input file. Recognize marker and line
422 * i386-opc.tbl (OPCODE_I386_H): Define.
423 (i386-opc.h): Include it.
426 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-opc.h (Byte): Update comments.
438 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
440 * i386-tbl.h: Regenerated.
442 2018-07-12 Sudakshina Das <sudi.das@arm.com>
444 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
445 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
446 * aarch64-asm-2.c: Regenerate.
447 * aarch64-dis-2.c: Regenerate.
448 * aarch64-opc-2.c: Regenerate.
450 2018-07-12 Tamar Christina <tamar.christina@arm.com>
453 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
454 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
455 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
456 sqdmulh, sqrdmulh): Use Em16.
458 2018-07-11 Sudakshina Das <sudi.das@arm.com>
460 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
461 csdb together with them.
462 (thumb32_opcodes): Likewise.
464 2018-07-11 Jan Beulich <jbeulich@suse.com>
466 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
467 requiring 32-bit registers as operands 2 and 3. Improve
469 (mwait, mwaitx): Fold templates. Improve comments.
470 OPERAND_TYPE_INOUTPORTREG.
471 * i386-tbl.h: Re-generate.
473 2018-07-11 Jan Beulich <jbeulich@suse.com>
475 * i386-gen.c (operand_type_init): Remove
476 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
477 OPERAND_TYPE_INOUTPORTREG.
478 * i386-init.h: Re-generate.
480 2018-07-11 Jan Beulich <jbeulich@suse.com>
482 * i386-opc.tbl (wrssd, wrussd): Add Dword.
483 (wrssq, wrussq): Add Qword.
484 * i386-tbl.h: Re-generate.
486 2018-07-11 Jan Beulich <jbeulich@suse.com>
488 * i386-opc.h: Rename OTMax to OTNum.
489 (OTNumOfUints): Adjust calculation.
490 (OTUnused): Directly alias to OTNum.
492 2018-07-09 Maciej W. Rozycki <macro@mips.com>
494 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
496 (lea_reg_xys): Likewise.
497 (print_insn_loop_primitive): Rename `reg' local variable to
500 2018-07-06 Tamar Christina <tamar.christina@arm.com>
503 * aarch64-tbl.h (ldarh): Fix disassembly mask.
505 2018-07-06 Tamar Christina <tamar.christina@arm.com>
508 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
509 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
511 2018-07-02 Maciej W. Rozycki <macro@mips.com>
514 * mips-dis.c (mips_option_arg_t): New enumeration.
515 (mips_options): New variable.
516 (disassembler_options_mips): New function.
517 (print_mips_disassembler_options): Reimplement in terms of
518 `disassembler_options_mips'.
519 * arm-dis.c (disassembler_options_arm): Adapt to using the
520 `disasm_options_and_args_t' structure.
521 * ppc-dis.c (disassembler_options_powerpc): Likewise.
522 * s390-dis.c (disassembler_options_s390): Likewise.
524 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
526 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
528 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
529 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
530 * testsuite/ld-arm/tls-longplt.d: Likewise.
532 2018-06-29 Tamar Christina <tamar.christina@arm.com>
535 * aarch64-asm-2.c: Regenerate.
536 * aarch64-dis-2.c: Likewise.
537 * aarch64-opc-2.c: Likewise.
538 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
539 * aarch64-opc.c (operand_general_constraint_met_p,
540 aarch64_print_operand): Likewise.
541 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
542 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
544 (AARCH64_OPERANDS): Add Em2.
546 2018-06-26 Nick Clifton <nickc@redhat.com>
548 * po/uk.po: Updated Ukranian translation.
549 * po/de.po: Updated German translation.
550 * po/pt_BR.po: Updated Brazilian Portuguese translation.
552 2018-06-26 Nick Clifton <nickc@redhat.com>
554 * nfp-dis.c: Fix spelling mistake.
556 2018-06-24 Nick Clifton <nickc@redhat.com>
558 * configure: Regenerate.
559 * po/opcodes.pot: Regenerate.
561 2018-06-24 Nick Clifton <nickc@redhat.com>
565 2018-06-19 Tamar Christina <tamar.christina@arm.com>
567 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
568 * aarch64-asm-2.c: Regenerate.
569 * aarch64-dis-2.c: Likewise.
571 2018-06-21 Maciej W. Rozycki <macro@mips.com>
573 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
574 `-M ginv' option description.
576 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
579 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
582 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
584 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
585 * configure.ac: Remove AC_PREREQ.
586 * Makefile.in: Re-generate.
587 * aclocal.m4: Re-generate.
588 * configure: Re-generate.
590 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
592 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
593 mips64r6 descriptors.
594 (parse_mips_ase_option): Handle -Mginv option.
595 (print_mips_disassembler_options): Document -Mginv.
596 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
598 (mips_opcodes): Define ginvi and ginvt.
600 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
601 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
603 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
604 * mips-opc.c (CRC, CRC64): New macros.
605 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
606 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
609 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
612 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
613 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
615 2018-06-06 Alan Modra <amodra@gmail.com>
617 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
618 setjmp. Move init for some other vars later too.
620 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
622 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
623 (dis_private): Add new fields for property section tracking.
624 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
625 (xtensa_instruction_fits): New functions.
626 (fetch_data): Bump minimal fetch size to 4.
627 (print_insn_xtensa): Make struct dis_private static.
628 Load and prepare property table on section change.
629 Don't disassemble literals. Don't disassemble instructions that
630 cross property table boundaries.
632 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
634 * configure: Regenerated.
636 2018-06-01 Jan Beulich <jbeulich@suse.com>
638 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
639 * i386-tbl.h: Re-generate.
641 2018-06-01 Jan Beulich <jbeulich@suse.com>
643 * i386-opc.tbl (sldt, str): Add NoRex64.
644 * i386-tbl.h: Re-generate.
646 2018-06-01 Jan Beulich <jbeulich@suse.com>
648 * i386-opc.tbl (invpcid): Add Oword.
649 * i386-tbl.h: Re-generate.
651 2018-06-01 Alan Modra <amodra@gmail.com>
653 * sysdep.h (_bfd_error_handler): Don't declare.
654 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
655 * rl78-decode.opc: Likewise.
656 * msp430-decode.c: Regenerate.
657 * rl78-decode.c: Regenerate.
659 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
661 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
662 * i386-init.h : Regenerated.
664 2018-05-25 Alan Modra <amodra@gmail.com>
666 * Makefile.in: Regenerate.
667 * po/POTFILES.in: Regenerate.
669 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
671 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
672 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
673 (insert_bab, extract_bab, insert_btab, extract_btab,
674 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
675 (BAT, BBA VBA RBS XB6S): Delete macros.
676 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
677 (BB, BD, RBX, XC6): Update for new macros.
678 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
679 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
680 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
681 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
683 2018-05-18 John Darrington <john@darrington.wattle.id.au>
685 * Makefile.am: Add support for s12z architecture.
686 * configure.ac: Likewise.
687 * disassemble.c: Likewise.
688 * disassemble.h: Likewise.
689 * Makefile.in: Regenerate.
690 * configure: Regenerate.
691 * s12z-dis.c: New file.
694 2018-05-18 Alan Modra <amodra@gmail.com>
696 * nfp-dis.c: Don't #include libbfd.h.
697 (init_nfp3200_priv): Use bfd_get_section_contents.
698 (nit_nfp6000_mecsr_sec): Likewise.
700 2018-05-17 Nick Clifton <nickc@redhat.com>
702 * po/zh_CN.po: Updated simplified Chinese translation.
704 2018-05-16 Tamar Christina <tamar.christina@arm.com>
707 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
708 * aarch64-dis-2.c: Regenerate.
710 2018-05-15 Tamar Christina <tamar.christina@arm.com>
713 * aarch64-asm.c (opintl.h): Include.
714 (aarch64_ins_sysreg): Enforce read/write constraints.
715 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
716 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
717 (F_REG_READ, F_REG_WRITE): New.
718 * aarch64-opc.c (aarch64_print_operand): Generate notes for
720 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
721 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
722 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
723 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
724 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
725 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
726 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
727 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
728 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
729 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
730 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
731 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
732 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
733 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
734 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
735 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
736 msr (F_SYS_WRITE), mrs (F_SYS_READ).
738 2018-05-15 Tamar Christina <tamar.christina@arm.com>
741 * aarch64-dis.c (no_notes: New.
742 (parse_aarch64_dis_option): Support notes.
743 (aarch64_decode_insn, print_operands): Likewise.
744 (print_aarch64_disassembler_options): Document notes.
745 * aarch64-opc.c (aarch64_print_operand): Support notes.
747 2018-05-15 Tamar Christina <tamar.christina@arm.com>
750 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
751 and take error struct.
752 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
753 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
754 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
755 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
756 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
757 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
758 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
759 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
760 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
761 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
762 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
763 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
764 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
765 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
766 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
767 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
768 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
769 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
770 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
771 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
772 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
773 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
774 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
775 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
776 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
777 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
778 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
779 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
780 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
781 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
782 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
783 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
784 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
785 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
786 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
787 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
788 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
789 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
790 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
791 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
792 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
793 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
794 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
795 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
796 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
797 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
798 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
799 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
800 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
801 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
802 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
803 (determine_disassembling_preference, aarch64_decode_insn,
804 print_insn_aarch64_word, print_insn_data): Take errors struct.
805 (print_insn_aarch64): Use errors.
806 * aarch64-asm-2.c: Regenerate.
807 * aarch64-dis-2.c: Regenerate.
808 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
809 boolean in aarch64_insert_operan.
810 (print_operand_extractor): Likewise.
811 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
813 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
815 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
817 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
819 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
821 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
823 * cr16-opc.c (cr16_instruction): Comment typo fix.
824 * hppa-dis.c (print_insn_hppa): Likewise.
826 2018-05-08 Jim Wilson <jimw@sifive.com>
828 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
829 (match_c_slli64, match_srxi_as_c_srxi): New.
830 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
831 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
832 <c.slli, c.srli, c.srai>: Use match_s_slli.
833 <c.slli64, c.srli64, c.srai64>: New.
835 2018-05-08 Alan Modra <amodra@gmail.com>
837 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
838 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
839 partition opcode space for index lookup.
841 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
843 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
844 <insn_length>: ...with this. Update usage.
845 Remove duplicate call to *info->memory_error_func.
847 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
848 H.J. Lu <hongjiu.lu@intel.com>
850 * i386-dis.c (Gva): New.
851 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
852 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
853 (prefix_table): New instructions (see prefix above).
854 (mod_table): New instructions (see prefix above).
855 (OP_G): Handle va_mode.
856 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
858 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
859 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
860 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
861 * i386-opc.tbl: Add movidir{i,64b}.
862 * i386-init.h: Regenerated.
863 * i386-tbl.h: Likewise.
865 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
867 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
869 * i386-opc.h (AddrPrefixOp0): Renamed to ...
870 (AddrPrefixOpReg): This.
871 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
872 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
874 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
876 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
877 (vle_num_opcodes): Likewise.
878 (spe2_num_opcodes): Likewise.
879 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
881 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
882 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
885 2018-05-01 Tamar Christina <tamar.christina@arm.com>
887 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
889 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
891 Makefile.am: Added nfp-dis.c.
892 configure.ac: Added bfd_nfp_arch.
893 disassemble.h: Added print_insn_nfp prototype.
894 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
895 nfp-dis.c: New, for NFP support.
896 po/POTFILES.in: Added nfp-dis.c to the list.
897 Makefile.in: Regenerate.
898 configure: Regenerate.
900 2018-04-26 Jan Beulich <jbeulich@suse.com>
902 * i386-opc.tbl: Fold various non-memory operand AVX512VL
903 templates into their base ones.
904 * i386-tlb.h: Re-generate.
906 2018-04-26 Jan Beulich <jbeulich@suse.com>
908 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
909 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
910 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
911 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
912 * i386-init.h: Re-generate.
914 2018-04-26 Jan Beulich <jbeulich@suse.com>
916 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
917 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
918 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
919 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
921 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
923 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
925 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
926 cpuregzmm, and cpuregmask.
927 * i386-init.h: Re-generate.
928 * i386-tbl.h: Re-generate.
930 2018-04-26 Jan Beulich <jbeulich@suse.com>
932 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
933 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
934 * i386-init.h: Re-generate.
936 2018-04-26 Jan Beulich <jbeulich@suse.com>
938 * i386-gen.c (VexImmExt): Delete.
939 * i386-opc.h (VexImmExt, veximmext): Delete.
940 * i386-opc.tbl: Drop all VexImmExt uses.
941 * i386-tlb.h: Re-generate.
943 2018-04-25 Jan Beulich <jbeulich@suse.com>
945 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
947 * i386-tlb.h: Re-generate.
949 2018-04-25 Tamar Christina <tamar.christina@arm.com>
951 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
953 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
955 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
957 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
958 (cpu_flags): Add CpuCLDEMOTE.
959 * i386-init.h: Regenerate.
960 * i386-opc.h (enum): Add CpuCLDEMOTE,
961 (i386_cpu_flags): Add cpucldemote.
962 * i386-opc.tbl: Add cldemote.
963 * i386-tbl.h: Regenerate.
965 2018-04-16 Alan Modra <amodra@gmail.com>
967 * Makefile.am: Remove sh5 and sh64 support.
968 * configure.ac: Likewise.
969 * disassemble.c: Likewise.
970 * disassemble.h: Likewise.
971 * sh-dis.c: Likewise.
972 * sh64-dis.c: Delete.
973 * sh64-opc.c: Delete.
974 * sh64-opc.h: Delete.
975 * Makefile.in: Regenerate.
976 * configure: Regenerate.
977 * po/POTFILES.in: Regenerate.
979 2018-04-16 Alan Modra <amodra@gmail.com>
981 * Makefile.am: Remove w65 support.
982 * configure.ac: Likewise.
983 * disassemble.c: Likewise.
984 * disassemble.h: Likewise.
987 * Makefile.in: Regenerate.
988 * configure: Regenerate.
989 * po/POTFILES.in: Regenerate.
991 2018-04-16 Alan Modra <amodra@gmail.com>
993 * configure.ac: Remove we32k support.
994 * configure: Regenerate.
996 2018-04-16 Alan Modra <amodra@gmail.com>
998 * Makefile.am: Remove m88k support.
999 * configure.ac: Likewise.
1000 * disassemble.c: Likewise.
1001 * disassemble.h: Likewise.
1002 * m88k-dis.c: Delete.
1003 * Makefile.in: Regenerate.
1004 * configure: Regenerate.
1005 * po/POTFILES.in: Regenerate.
1007 2018-04-16 Alan Modra <amodra@gmail.com>
1009 * Makefile.am: Remove i370 support.
1010 * configure.ac: Likewise.
1011 * disassemble.c: Likewise.
1012 * disassemble.h: Likewise.
1013 * i370-dis.c: Delete.
1014 * i370-opc.c: Delete.
1015 * Makefile.in: Regenerate.
1016 * configure: Regenerate.
1017 * po/POTFILES.in: Regenerate.
1019 2018-04-16 Alan Modra <amodra@gmail.com>
1021 * Makefile.am: Remove h8500 support.
1022 * configure.ac: Likewise.
1023 * disassemble.c: Likewise.
1024 * disassemble.h: Likewise.
1025 * h8500-dis.c: Delete.
1026 * h8500-opc.h: Delete.
1027 * Makefile.in: Regenerate.
1028 * configure: Regenerate.
1029 * po/POTFILES.in: Regenerate.
1031 2018-04-16 Alan Modra <amodra@gmail.com>
1033 * configure.ac: Remove tahoe support.
1034 * configure: Regenerate.
1036 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1038 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1040 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1042 * i386-tbl.h: Regenerated.
1044 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1046 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1047 PREFIX_MOD_1_0FAE_REG_6.
1049 (OP_E_register): Use va_mode.
1050 * i386-dis-evex.h (prefix_table):
1051 New instructions (see prefixes above).
1052 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1053 (cpu_flags): Likewise.
1054 * i386-opc.h (enum): Likewise.
1055 (i386_cpu_flags): Likewise.
1056 * i386-opc.tbl: Add umonitor, umwait, tpause.
1057 * i386-init.h: Regenerate.
1058 * i386-tbl.h: Likewise.
1060 2018-04-11 Alan Modra <amodra@gmail.com>
1062 * opcodes/i860-dis.c: Delete.
1063 * opcodes/i960-dis.c: Delete.
1064 * Makefile.am: Remove i860 and i960 support.
1065 * configure.ac: Likewise.
1066 * disassemble.c: Likewise.
1067 * disassemble.h: Likewise.
1068 * Makefile.in: Regenerate.
1069 * configure: Regenerate.
1070 * po/POTFILES.in: Regenerate.
1072 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1075 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1077 (print_insn): Clear vex instead of vex.evex.
1079 2018-04-04 Nick Clifton <nickc@redhat.com>
1081 * po/es.po: Updated Spanish translation.
1083 2018-03-28 Jan Beulich <jbeulich@suse.com>
1085 * i386-gen.c (opcode_modifiers): Delete VecESize.
1086 * i386-opc.h (VecESize): Delete.
1087 (struct i386_opcode_modifier): Delete vecesize.
1088 * i386-opc.tbl: Drop VecESize.
1089 * i386-tlb.h: Re-generate.
1091 2018-03-28 Jan Beulich <jbeulich@suse.com>
1093 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1094 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1095 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1096 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1097 * i386-tlb.h: Re-generate.
1099 2018-03-28 Jan Beulich <jbeulich@suse.com>
1101 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1103 * i386-tlb.h: Re-generate.
1105 2018-03-28 Jan Beulich <jbeulich@suse.com>
1107 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1108 (vex_len_table): Drop Y for vcvt*2si.
1109 (putop): Replace plain 'Y' handling by abort().
1111 2018-03-28 Nick Clifton <nickc@redhat.com>
1114 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1115 instructions with only a base address register.
1116 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1117 handle AARHC64_OPND_SVE_ADDR_R.
1118 (aarch64_print_operand): Likewise.
1119 * aarch64-asm-2.c: Regenerate.
1120 * aarch64_dis-2.c: Regenerate.
1121 * aarch64-opc-2.c: Regenerate.
1123 2018-03-22 Jan Beulich <jbeulich@suse.com>
1125 * i386-opc.tbl: Drop VecESize from register only insn forms and
1126 memory forms not allowing broadcast.
1127 * i386-tlb.h: Re-generate.
1129 2018-03-22 Jan Beulich <jbeulich@suse.com>
1131 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1132 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1133 sha256*): Drop Disp<N>.
1135 2018-03-22 Jan Beulich <jbeulich@suse.com>
1137 * i386-dis.c (EbndS, bnd_swap_mode): New.
1138 (prefix_table): Use EbndS.
1139 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1140 * i386-opc.tbl (bndmov): Move misplaced Load.
1141 * i386-tlb.h: Re-generate.
1143 2018-03-22 Jan Beulich <jbeulich@suse.com>
1145 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1146 templates allowing memory operands and folded ones for register
1148 * i386-tlb.h: Re-generate.
1150 2018-03-22 Jan Beulich <jbeulich@suse.com>
1152 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1153 256-bit templates. Drop redundant leftover Disp<N>.
1154 * i386-tlb.h: Re-generate.
1156 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1158 * riscv-opc.c (riscv_insn_types): New.
1160 2018-03-13 Nick Clifton <nickc@redhat.com>
1162 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1164 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1166 * i386-opc.tbl: Add Optimize to clr.
1167 * i386-tbl.h: Regenerated.
1169 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1171 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1172 * i386-opc.h (OldGcc): Removed.
1173 (i386_opcode_modifier): Remove oldgcc.
1174 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1175 instructions for old (<= 2.8.1) versions of gcc.
1176 * i386-tbl.h: Regenerated.
1178 2018-03-08 Jan Beulich <jbeulich@suse.com>
1180 * i386-opc.h (EVEXDYN): New.
1181 * i386-opc.tbl: Fold various AVX512VL templates.
1182 * i386-tlb.h: Re-generate.
1184 2018-03-08 Jan Beulich <jbeulich@suse.com>
1186 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1187 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1188 vpexpandd, vpexpandq): Fold AFX512VF templates.
1189 * i386-tlb.h: Re-generate.
1191 2018-03-08 Jan Beulich <jbeulich@suse.com>
1193 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1194 Fold 128- and 256-bit VEX-encoded templates.
1195 * i386-tlb.h: Re-generate.
1197 2018-03-08 Jan Beulich <jbeulich@suse.com>
1199 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1200 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1201 vpexpandd, vpexpandq): Fold AVX512F templates.
1202 * i386-tlb.h: Re-generate.
1204 2018-03-08 Jan Beulich <jbeulich@suse.com>
1206 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1207 64-bit templates. Drop Disp<N>.
1208 * i386-tlb.h: Re-generate.
1210 2018-03-08 Jan Beulich <jbeulich@suse.com>
1212 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1213 and 256-bit templates.
1214 * i386-tlb.h: Re-generate.
1216 2018-03-08 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1219 * i386-tlb.h: Re-generate.
1221 2018-03-08 Jan Beulich <jbeulich@suse.com>
1223 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1225 * i386-tlb.h: Re-generate.
1227 2018-03-08 Jan Beulich <jbeulich@suse.com>
1229 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1230 * i386-tlb.h: Re-generate.
1232 2018-03-08 Jan Beulich <jbeulich@suse.com>
1234 * i386-gen.c (opcode_modifiers): Delete FloatD.
1235 * i386-opc.h (FloatD): Delete.
1236 (struct i386_opcode_modifier): Delete floatd.
1237 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1239 * i386-tlb.h: Re-generate.
1241 2018-03-08 Jan Beulich <jbeulich@suse.com>
1243 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1245 2018-03-08 Jan Beulich <jbeulich@suse.com>
1247 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1248 * i386-tlb.h: Re-generate.
1250 2018-03-08 Jan Beulich <jbeulich@suse.com>
1252 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1254 * i386-tlb.h: Re-generate.
1256 2018-03-07 Alan Modra <amodra@gmail.com>
1258 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1260 * disassemble.h (print_insn_rs6000): Delete.
1261 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1262 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1263 (print_insn_rs6000): Delete.
1265 2018-03-03 Alan Modra <amodra@gmail.com>
1267 * sysdep.h (opcodes_error_handler): Define.
1268 (_bfd_error_handler): Declare.
1269 * Makefile.am: Remove stray #.
1270 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1272 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1273 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1274 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1275 opcodes_error_handler to print errors. Standardize error messages.
1276 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1277 and include opintl.h.
1278 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1279 * i386-gen.c: Standardize error messages.
1280 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1281 * Makefile.in: Regenerate.
1282 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1283 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1284 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1285 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1286 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1287 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1288 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1289 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1290 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1291 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1292 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1293 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1294 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1296 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1298 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1299 vpsub[bwdq] instructions.
1300 * i386-tbl.h: Regenerated.
1302 2018-03-01 Alan Modra <amodra@gmail.com>
1304 * configure.ac (ALL_LINGUAS): Sort.
1305 * configure: Regenerate.
1307 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1309 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1310 macro by assignements.
1312 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1315 * i386-gen.c (opcode_modifiers): Add Optimize.
1316 * i386-opc.h (Optimize): New enum.
1317 (i386_opcode_modifier): Add optimize.
1318 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1319 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1320 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1321 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1322 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1324 * i386-tbl.h: Regenerated.
1326 2018-02-26 Alan Modra <amodra@gmail.com>
1328 * crx-dis.c (getregliststring): Allocate a large enough buffer
1329 to silence false positive gcc8 warning.
1331 2018-02-22 Shea Levy <shea@shealevy.com>
1333 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1335 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1337 * i386-opc.tbl: Add {rex},
1338 * i386-tbl.h: Regenerated.
1340 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1342 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1343 (mips16_opcodes): Replace `M' with `m' for "restore".
1345 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1347 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1349 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1351 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1352 variable to `function_index'.
1354 2018-02-13 Nick Clifton <nickc@redhat.com>
1357 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1358 about truncation of printing.
1360 2018-02-12 Henry Wong <henry@stuffedcow.net>
1362 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1364 2018-02-05 Nick Clifton <nickc@redhat.com>
1366 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1368 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1370 * i386-dis.c (enum): Add pconfig.
1371 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1372 (cpu_flags): Add CpuPCONFIG.
1373 * i386-opc.h (enum): Add CpuPCONFIG.
1374 (i386_cpu_flags): Add cpupconfig.
1375 * i386-opc.tbl: Add PCONFIG instruction.
1376 * i386-init.h: Regenerate.
1377 * i386-tbl.h: Likewise.
1379 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1381 * i386-dis.c (enum): Add PREFIX_0F09.
1382 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1383 (cpu_flags): Add CpuWBNOINVD.
1384 * i386-opc.h (enum): Add CpuWBNOINVD.
1385 (i386_cpu_flags): Add cpuwbnoinvd.
1386 * i386-opc.tbl: Add WBNOINVD instruction.
1387 * i386-init.h: Regenerate.
1388 * i386-tbl.h: Likewise.
1390 2018-01-17 Jim Wilson <jimw@sifive.com>
1392 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1394 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1396 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1397 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1398 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1399 (cpu_flags): Add CpuIBT, CpuSHSTK.
1400 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1401 (i386_cpu_flags): Add cpuibt, cpushstk.
1402 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1403 * i386-init.h: Regenerate.
1404 * i386-tbl.h: Likewise.
1406 2018-01-16 Nick Clifton <nickc@redhat.com>
1408 * po/pt_BR.po: Updated Brazilian Portugese translation.
1409 * po/de.po: Updated German translation.
1411 2018-01-15 Jim Wilson <jimw@sifive.com>
1413 * riscv-opc.c (match_c_nop): New.
1414 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1416 2018-01-15 Nick Clifton <nickc@redhat.com>
1418 * po/uk.po: Updated Ukranian translation.
1420 2018-01-13 Nick Clifton <nickc@redhat.com>
1422 * po/opcodes.pot: Regenerated.
1424 2018-01-13 Nick Clifton <nickc@redhat.com>
1426 * configure: Regenerate.
1428 2018-01-13 Nick Clifton <nickc@redhat.com>
1430 2.30 branch created.
1432 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1434 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1435 * i386-tbl.h: Regenerate.
1437 2018-01-10 Jan Beulich <jbeulich@suse.com>
1439 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1440 * i386-tbl.h: Re-generate.
1442 2018-01-10 Jan Beulich <jbeulich@suse.com>
1444 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1445 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1446 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1447 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1448 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1449 Disp8MemShift of AVX512VL forms.
1450 * i386-tbl.h: Re-generate.
1452 2018-01-09 Jim Wilson <jimw@sifive.com>
1454 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1455 then the hi_addr value is zero.
1457 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1459 * arm-dis.c (arm_opcodes): Add csdb.
1460 (thumb32_opcodes): Add csdb.
1462 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1464 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1465 * aarch64-asm-2.c: Regenerate.
1466 * aarch64-dis-2.c: Regenerate.
1467 * aarch64-opc-2.c: Regenerate.
1469 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1472 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1473 Remove AVX512 vmovd with 64-bit operands.
1474 * i386-tbl.h: Regenerated.
1476 2018-01-05 Jim Wilson <jimw@sifive.com>
1478 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1481 2018-01-03 Alan Modra <amodra@gmail.com>
1483 Update year range in copyright notice of all files.
1485 2018-01-02 Jan Beulich <jbeulich@suse.com>
1487 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1488 and OPERAND_TYPE_REGZMM entries.
1490 For older changes see ChangeLog-2017
1492 Copyright (C) 2018 Free Software Foundation, Inc.
1494 Copying and distribution of this file, with or without modification,
1495 are permitted in any medium without royalty provided the copyright
1496 notice and this notice are preserved.
1502 version-control: never