opcodes/ChangeLog

   1 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
   2
   3         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
   4         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
   5
   6 2014-11-03  Nick Clifton  <nickc@redhat.com>
   7
   8         * po/fi.po: Updated Finnish translation.
   9
  10 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  11             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
  12
  13         * mips-dis.c (mips_arch_choices): Add octeon3.
  14         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  15         (IOCT2): Likewise.
  16         (IOCT3): New define.
  17         (IVIRT): New define.
  18         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  19         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  20         IVIRT instructions.
  21         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  22         operand for IOCT3.
  23
  24 2014-10-29  Nick Clifton  <nickc@redhat.com>
  25
  26         * po/de.po: Updated German translation.
  27
  28 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  29
  30         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  31         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  32         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  33         size and format initializers.  Merge 'b' arguments into 'j'.
  34         (NIOS2_NUM_OPCODES): Adjust definition.
  35         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  36         (nios2_opcodes): Adjust.
  37         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  38         * nios2-dis.c (INSNLEN): Update comment.
  39         (nios2_hash_init, nios2_hash): Delete.
  40         (OPCODE_HASH_SIZE): New.
  41         (nios2_r1_extract_opcode): New.
  42         (nios2_disassembler_state): New.
  43         (nios2_r1_disassembler_state): New.
  44         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  45         (nios2_find_opcode_hash): Use state object.
  46         (bad_opcode): New.
  47         (nios2_print_insn_arg): Add op parameter.  Use it to access
  48         format.  Remove 'b' case.
  49         (nios2_disassemble): Remove special case for nop.  Remove
  50         hard-coded instruction size.
  51
  52 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  53
  54         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  55
  56 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  57
  58         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  59         entries.
  60         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  61
  62 2014-10-15  Tristan Gingold  <gingold@adacore.com>
  63
  64         * configure: Regenerate.
  65
  66 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  67
  68         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  69         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  70         Annotate table with HWCAP2 bits.
  71         Add instructions xmontmul, xmontsqr, xmpmul.
  72         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  73         r,i,%mwait' and `rd %mwait,r' instructions.
  74         Add rd/wr instructions for accessing the %mcdper ancillary state
  75         register.
  76         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  77         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  78         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  79         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  80         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  81         fpsubus16, and faligndatai.
  82         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  83         ancillary state register to the table.
  84         (print_insn_sparc): Handle the %mcdper ancillary state register.
  85         (print_insn_sparc): Handle new operand type '}'.
  86
  87 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  88
  89         * i386-dis.c (MOD_0F20): Removed.
  90         (MOD_0F21): Likewise.
  91         (MOD_0F22): Likewise.
  92         (MOD_0F23): Likewise.
  93         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  94         MOD_0F23 with "movZ".
  95         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  96         (OP_R): Check mod/rm byte and call OP_E_register.
  97
  98 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  99
 100         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 101         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 102         keyword_aridxi): Add audio ISA extension.
 103         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 104         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 105         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 106         for nds32-dis.c using.
 107         (build_opcode_syntax): Remove dead code.
 108         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 109         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 110         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 111         operand parser.
 112         * nds32-asm.h: Declare.
 113         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 114         decoding by switch.
 115
 116 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 117             Matthew Fortune  <matthew.fortune@imgtec.com>
 118
 119         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 120         mips64r6.
 121         (parse_mips_dis_option): Allow MSA and virtualization support for
 122         mips64r6.
 123         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 124         (mips_seen_register): New function.
 125         (print_insn_arg): Refactored code to use mips_seen_register
 126         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 127         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 128         the register rather than aborting.
 129         (print_insn_args): Add length argument.  Add code to correctly
 130         calculate the instruction address for pc relative instructions.
 131         (validate_insn_args): New static function.
 132         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 133         validate_insn_args.
 134         (print_insn_micromips): Use validate_insn_args.
 135         all the arguments are valid.
 136         * mips-formats.h (PREV_CHECK): New define.
 137         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 138         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 139         (RD_pc): New define.
 140         (FS): New define.
 141         (I37): New define.
 142         (I69): New define.
 143         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 144         MIPS R6 instructions from MIPS R2 instructions.
 145
 146 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 149         (putop): Handle "%LP".
 150
 151 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 152
 153         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 154         * aarch64-dis-2.c: Update auto-generated file.
 155
 156 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 157
 158         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 159         (aarch64_feature_lse): New feature added.
 160         (LSE): New Added.
 161         (aarch64_opcode_table): New LSE instructions added.  Improve
 162         descriptions for ldarb/ldarh/ldar.
 163         (aarch64_opcode_table): Describe PAIRREG.
 164         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 165         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 166         (aarch64_print_operand): Recognize PAIRREG.
 167         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 168         instructions.
 169         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 170         (do_special_decoding): Recognize F_LSE_SZ.
 171         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 172
 173 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 174
 175         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 176         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 177         "sdbbp", "syscall" and "wait".
 178
 179 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 180             Maciej W. Rozycki  <macro@codesourcery.com>
 181
 182         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 183         returned if the U bit is set.
 184
 185 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 186
 187         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 188         48-bit "li" encoding.
 189
 190 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 191
 192         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 193         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 194         static functions, code was moved from...
 195         (print_insn_s390): ...here.
 196         (s390_extract_operand): Adjust comment.  Change type of first
 197         parameter from 'unsigned char *' to 'const bfd_byte *'.
 198         (union operand_value): New.
 199         (s390_extract_operand): Change return type to union operand_value.
 200         Also avoid integer overflow in sign-extension.
 201         (s390_print_insn_with_opcode): Adjust to changed return value from
 202         s390_extract_operand().  Change "%i" printf format to "%u" for
 203         unsigned values.
 204         (init_disasm): Simplify initialization of opc_index[].  This also
 205         fixes an access after the last element of s390_opcodes[].
 206         (print_insn_s390): Simplify the opcode search loop.
 207         Check architecture mask against all searched opcodes, not just the
 208         first matching one.
 209         (s390_print_insn_with_opcode): Drop function pointer dereferences
 210         without effect.
 211         (print_insn_s390): Likewise.
 212         (s390_insn_length): Simplify formula for return value.
 213         (s390_print_insn_with_opcode): Avoid special handling for the
 214         separator before the first operand.  Use new local variable
 215         'flags' in place of 'operand->flags'.
 216
 217 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 218
 219         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 220         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 221         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 222         Change assignment of 1 to priv->comment to TRUE.
 223         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 224         assignment of 0/1 with priv comment and parallel and legal
 225         to FALSE/TRUE.
 226
 227 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 228
 229         * bfin-dis.c (OUT): Define.
 230         (decode_CC2stat_0): Declare new op_names array.
 231         Replace multiple if statements with a single one.
 232
 233 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 234
 235         * bfin-dis.c (struct private): Add iw0.
 236         (_print_insn_bfin): Assign iw0 to priv.iw0.
 237         (print_insn_bfin): Drop ifetch and use priv.iw0.
 238
 239 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 240
 241         * bfin-dis.c (comment, parallel): Move from global scope ...
 242         (struct private): ... to this new struct.
 243         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 244         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 245         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 246         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 247         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 248         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 249         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 250         print_insn_bfin): Declare private struct.  Use priv's comment and
 251         parallel members.
 252
 253 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 254
 255         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 256         (_print_insn_bfin): Add check for unaligned pc.
 257
 258 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 259
 260         * bfin-dis.c (ifetch): New function.
 261         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 262         -1 when it errors.
 263
 264 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 265
 266         * micromips-opc.c (COD): Rename throughout to...
 267         (CM): New define, update to use INSN_COPROC_MOVE.
 268         (LCD): Rename throughout to...
 269         (LC): New define, update to use INSN_LOAD_COPROC.
 270         * mips-opc.c: Likewise.
 271
 272 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 273
 274         * micromips-opc.c (COD, LCD) New macros.
 275         (cfc1, ctc1): Remove FP_S attribute.
 276         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 277         (dmtc1, mtc1, mthc1): Add COD attribute.
 278         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 279
 280 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 281             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 282             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 283             Sergey Lega  <sergey.s.lega@intel.com>
 284             Anna Tikhonova  <anna.tikhonova@intel.com>
 285             Ilya Tocar  <ilya.tocar@intel.com>
 286             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 287             Ilya Verbin  <ilya.verbin@intel.com>
 288             Kirill Yukhin  <kirill.yukhin@intel.com>
 289             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 290
 291         * i386-dis-evex.h: Updated.
 292         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 293         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 294         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 295         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 296         PREFIX_EVEX_0F3A67.
 297         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 298         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 299         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 300         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 301         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 302         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 303         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 304         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 305         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 306         (prefix_table): Add entries for new instructions.
 307         (vex_len_table): Ditto.
 308         (vex_w_table): Ditto.
 309         (OP_E_memory): Update xmmq_mode handling.
 310         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 311         (cpu_flags): Add CpuAVX512DQ.
 312         * i386-init.h: Regenerared.
 313         * i386-opc.h (CpuAVX512DQ): New.
 314         (i386_cpu_flags): Add cpuavx512dq.
 315         * i386-opc.tbl: Add AVX512DQ instructions.
 316         * i386-tbl.h: Regenerate.
 317
 318 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 319             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 320             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 321             Sergey Lega  <sergey.s.lega@intel.com>
 322             Anna Tikhonova  <anna.tikhonova@intel.com>
 323             Ilya Tocar  <ilya.tocar@intel.com>
 324             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 325             Ilya Verbin  <ilya.verbin@intel.com>
 326             Kirill Yukhin  <kirill.yukhin@intel.com>
 327             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 328
 329         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 330         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 331         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 332         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 333         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 334         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 335         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 336         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 337         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 338         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 339         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 340         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 341         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 342         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 343         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 344         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 345         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 346         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 347         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 348         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 349         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 350         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 351         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 352         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 353         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 354         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 355         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 356         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 357         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 358         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 359         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 360         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 361         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 362         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 363         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 364         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 365         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 366         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 367         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 368         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 369         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 370         (prefix_table): Add entries for new instructions.
 371         (vex_table) : Ditto.
 372         (vex_len_table): Ditto.
 373         (vex_w_table): Ditto.
 374         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 375         mask_bd_mode handling.
 376         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 377         handling.
 378         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 379         handling.
 380         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 381         (OP_EX): Add dqw_swap_mode handling.
 382         (OP_VEX): Add mask_bd_mode handling.
 383         (OP_Mask): Add mask_bd_mode handling.
 384         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 385         (cpu_flags): Add CpuAVX512BW.
 386         * i386-init.h: Regenerated.
 387         * i386-opc.h (CpuAVX512BW): New.
 388         (i386_cpu_flags): Add cpuavx512bw.
 389         * i386-opc.tbl: Add AVX512BW instructions.
 390         * i386-tbl.h: Regenerate.
 391
 392 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 393             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 394             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 395             Sergey Lega  <sergey.s.lega@intel.com>
 396             Anna Tikhonova  <anna.tikhonova@intel.com>
 397             Ilya Tocar  <ilya.tocar@intel.com>
 398             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 399             Ilya Verbin  <ilya.verbin@intel.com>
 400             Kirill Yukhin  <kirill.yukhin@intel.com>
 401             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 402
 403         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 404         * i386-tbl.h: Regenerate.
 405
 406 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 407             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 408             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 409             Sergey Lega  <sergey.s.lega@intel.com>
 410             Anna Tikhonova  <anna.tikhonova@intel.com>
 411             Ilya Tocar  <ilya.tocar@intel.com>
 412             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 413             Ilya Verbin  <ilya.verbin@intel.com>
 414             Kirill Yukhin  <kirill.yukhin@intel.com>
 415             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 416
 417         * i386-dis.c (intel_operand_size): Support 128/256 length in
 418         vex_vsib_q_w_dq_mode.
 419         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 420         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 421         (cpu_flags): Add CpuAVX512VL.
 422         * i386-init.h: Regenerated.
 423         * i386-opc.h (CpuAVX512VL): New.
 424         (i386_cpu_flags): Add cpuavx512vl.
 425         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 426         * i386-opc.tbl: Add AVX512VL instructions.
 427         * i386-tbl.h: Regenerate.
 428
 429 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 430
 431         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 432         * or1k-opinst.c: Regenerate.
 433
 434 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 435
 436         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 437         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 438
 439 2014-07-04  Alan Modra  <amodra@gmail.com>
 440
 441         * configure.ac: Rename from configure.in.
 442         * Makefile.in: Regenerate.
 443         * config.in: Regenerate.
 444
 445 2014-07-04  Alan Modra  <amodra@gmail.com>
 446
 447         * configure.in: Include bfd/version.m4.
 448         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 449         (BFD_VERSION): Delete.
 450         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 451         * configure: Regenerate.
 452         * Makefile.in: Regenerate.
 453
 454 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 455             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 456             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 457             Soundararajan  <Sounderarajan.D@atmel.com>
 458
 459         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 460         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 461         machine is not avrtiny.
 462
 463 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 464
 465         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 466         constants.
 467
 468 2014-06-12  Alan Modra  <amodra@gmail.com>
 469
 470         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 471         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 472
 473 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         * i386-dis.c (fwait_prefix): New.
 476         (ckprefix): Set fwait_prefix.
 477         (print_insn): Properly print prefixes before fwait.
 478
 479 2014-06-07  Alan Modra  <amodra@gmail.com>
 480
 481         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 482
 483 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 484
 485         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 486         bfd's development.sh.
 487         * Makefile.in, configure: Regenerate.
 488
 489 2014-06-03  Nick Clifton  <nickc@redhat.com>
 490
 491         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 492         decide when extended addressing is being used.
 493
 494 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 495
 496         * sparc-opc.c (cas): Disable for LEON.
 497         (casl): Likewise.
 498
 499 2014-05-20  Alan Modra  <amodra@gmail.com>
 500
 501         * m68k-dis.c: Don't include setjmp.h.
 502
 503 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         * i386-dis.c (ADDR16_PREFIX): Removed.
 506         (ADDR32_PREFIX): Likewise.
 507         (DATA16_PREFIX): Likewise.
 508         (DATA32_PREFIX): Likewise.
 509         (prefix_name): Updated.
 510         (print_insn): Simplify data and address size prefixes processing.
 511
 512 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 513
 514         * or1k-desc.c: Regenerated.
 515         * or1k-desc.h: Likewise.
 516         * or1k-opc.c: Likewise.
 517         * or1k-opc.h: Likewise.
 518         * or1k-opinst.c: Likewise.
 519
 520 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 521
 522         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 523         (I34): New define.
 524         (I36): New define.
 525         (I66): New define.
 526         (I68): New define.
 527         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 528         mips64r5.
 529         (parse_mips_dis_option): Update MSA and virtualization support to
 530         allow mips64r3 and mips64r5.
 531
 532 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 533
 534         * mips-opc.c (G3): Remove I4.
 535
 536 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 537
 538         PR binutils/16893
 539         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 540         (end_codep): Likewise.
 541         (mandatory_prefix): Likewise.
 542         (active_seg_prefix): Likewise.
 543         (ckprefix): Set active_seg_prefix to the active segment register
 544         prefix.
 545         (seg_prefix): Removed.
 546         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 547         for prefix index.  Ignore the index if it is invalid and the
 548         mandatory prefix isn't required.
 549         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 550         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 551         in used_prefixes here.  Don't print unused prefixes.  Check
 552         active_seg_prefix for the active segment register prefix.
 553         Restore the DFLAG bit in sizeflag if the data size prefix is
 554         unused.  Check the unused mandatory PREFIX_XXX prefixes
 555         (append_seg): Only print the segment register which gets used.
 556         (OP_E_memory): Check active_seg_prefix for the segment register
 557         prefix.
 558         (OP_OFF): Likewise.
 559         (OP_OFF64): Likewise.
 560         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 561
 562 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 563
 564         PR binutils/16886
 565         * config.in: Regenerated.
 566         * configure: Likewise.
 567         * configure.in: Check if sigsetjmp is available.
 568         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 569         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 570         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 571         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 572         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 573         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 574         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 575         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 576         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 577         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 578         (OPCODES_SIGSETJMP): Likewise.
 579         (OPCODES_SIGLONGJMP): Likewise.
 580         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 581         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 582         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 583         * xtensa-dis.c (dis_private): Replace jmp_buf with
 584         OPCODES_SIGJMP_BUF.
 585         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 586         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 587         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 588         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 589         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 590
 591 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 592
 593         PR binutils/16891
 594         * i386-dis.c (print_insn): Handle prefixes before fwait.
 595
 596 2014-04-26  Alan Modra  <amodra@gmail.com>
 597
 598         * po/POTFILES.in: Regenerate.
 599
 600 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 601
 602         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 603         to allow the MIPS XPA ASE.
 604         (parse_mips_dis_option): Process the -Mxpa option.
 605         * mips-opc.c (XPA): New define.
 606         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 607         locations of the ctc0 and cfc0 instructions.
 608
 609 2014-04-22  Christian Svensson  <blue@cmd.nu>
 610
 611         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 612         * configure.in: Likewise.
 613         * disassemble.c: Likewise.
 614         * or1k-asm.c: New file.
 615         * or1k-desc.c: New file.
 616         * or1k-desc.h: New file.
 617         * or1k-dis.c: New file.
 618         * or1k-ibld.c: New file.
 619         * or1k-opc.c: New file.
 620         * or1k-opc.h: New file.
 621         * or1k-opinst.c: New file.
 622         * Makefile.in: Regenerate.
 623         * configure: Regenerate.
 624         * openrisc-asm.c: Delete.
 625         * openrisc-desc.c: Delete.
 626         * openrisc-desc.h: Delete.
 627         * openrisc-dis.c: Delete.
 628         * openrisc-ibld.c: Delete.
 629         * openrisc-opc.c: Delete.
 630         * openrisc-opc.h: Delete.
 631         * or32-dis.c: Delete.
 632         * or32-opc.c: Delete.
 633
 634 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 635
 636         * i386-dis.c (rm_table): Add encls, enclu.
 637         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 638         (cpu_flags): Add CpuSE1.
 639         * i386-opc.h (enum): Add CpuSE1.
 640         (i386_cpu_flags): Add cpuse1.
 641         * i386-opc.tbl: Add encls, enclu.
 642         * i386-init.h: Regenerated.
 643         * i386-tbl.h: Likewise.
 644
 645 2014-04-02  Anthony Green  <green@moxielogic.com>
 646
 647         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 648         instructions, sex.b and sex.s.
 649
 650 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 651
 652         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 653         instructions.
 654
 655 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 656
 657         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 658         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 659         vscatterqps.
 660         * i386-tbl.h: Regenerate.
 661
 662 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 663
 664         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 665         %hstick_enable added.
 666
 667 2014-03-19  Nick Clifton  <nickc@redhat.com>
 668
 669         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 670         field of 3.
 671         (sbwl, ubwl, SCALE): Likewise.
 672         * rx-decode.c: Regenerate.
 673
 674 2014-03-12  Alan Modra  <amodra@gmail.com>
 675
 676         * Makefile.in: Regenerate.
 677
 678 2014-03-05  Alan Modra  <amodra@gmail.com>
 679
 680         Update copyright years.
 681
 682 2014-03-04  Heiher  <r@hev.cc>
 683
 684         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 685
 686 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 687
 688         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 689         so that they come after the Loongson extensions.
 690
 691 2014-03-03  Alan Modra  <amodra@gmail.com>
 692
 693         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 694
 695 2014-02-28  Alan Modra  <amodra@gmail.com>
 696
 697         * msp430-decode.c: Regenerate.
 698
 699 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 700
 701         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 702         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 703
 704 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 705
 706         * aarch64-opc.c (print_register_offset_address): Call
 707         get_int_reg_name to prepare the register name.
 708
 709 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 710
 711         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 712         * i386-tbl.h: Regenerate.
 713
 714 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 715
 716         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 717         (cpu_flags): Add CpuPREFETCHWT1.
 718         * i386-init.h: Regenerate.
 719         * i386-opc.h (CpuPREFETCHWT1): New.
 720         (i386_cpu_flags): Add cpuprefetchwt1.
 721         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 722         * i386-tbl.h: Regenerate.
 723
 724 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 725
 726         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 727         to CpuAVX512F.
 728         * i386-tbl.h: Regenerate.
 729
 730 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 731
 732         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 733         (output_opcode_modifier): Likewise.
 734         (output_operand_type): Likewise.
 735         * i386-init.h: Regenerated.
 736         * i386-tbl.h: Likewise.
 737
 738 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 739
 740         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 741         MOD_0FC7_REG_5.
 742         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 743         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 744         (prefix_table): Add clflusopt.
 745         (mod_table): Add xrstors, xsavec, xsaves.
 746         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 747         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 748         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 749         * i386-init.h: Regenerate.
 750         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 751         xsaves64, xsavec, xsavec64.
 752         * i386-tbl.h: Regenerate.
 753
 754 2014-02-10  Alan Modra  <amodra@gmail.com>
 755
 756         * po/POTFILES.in: Regenerate.
 757         * po/opcodes.pot: Regenerate.
 758
 759 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 760             Jan Beulich  <jbeulich@suse.com>
 761
 762         PR binutils/16490
 763         * i386-dis.c (OP_E_memory): Fix shift computation for
 764         vex_vsib_q_w_dq_mode.
 765
 766 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 767             Roland McGrath  <mcgrathr@google.com>
 768
 769         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 770         last_rex_prefix is -1.
 771
 772 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 773
 774         * i386-gen.c (process_copyright): Update copyright year to 2014.
 775
 776 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 777
 778         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 779
 780 For older changes see ChangeLog-2013
 781 \f
 782 Copyright (C) 2014 Free Software Foundation, Inc.
 783
 784 Copying and distribution of this file, with or without modification,
 785 are permitted in any medium without royalty provided the copyright
 786 notice and this notice are preserved.
 787
 788 Local Variables:
 789 mode: change-log
 790 left-margin: 8
 791 fill-column: 74
 792 version-control: never
 793 End: