1 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
3 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
4 Change the coproc CRC conditions to use the extension
5 feature set, second word, base on ARM_EXT2_CRC.
7 2019-11-14 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
10 * i386-tbl.h: Re-generate.
12 2019-11-14 Jan Beulich <jbeulich@suse.com>
14 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
15 JumpInterSegment, and JumpAbsolute entries.
16 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
17 JUMP_ABSOLUTE): Define.
18 (struct i386_opcode_modifier): Extend jump field to 3 bits.
19 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
21 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
22 JumpInterSegment): Define.
23 * i386-tbl.h: Re-generate.
25 2019-11-14 Jan Beulich <jbeulich@suse.com>
27 * i386-gen.c (operand_type_init): Remove
28 OPERAND_TYPE_JUMPABSOLUTE entry.
29 (opcode_modifiers): Add JumpAbsolute entry.
30 (operand_types): Remove JumpAbsolute entry.
31 * i386-opc.h (JumpAbsolute): Move between enums.
32 (struct i386_opcode_modifier): Add jumpabsolute field.
33 (union i386_operand_type): Remove jumpabsolute field.
34 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
35 * i386-init.h, i386-tbl.h: Re-generate.
37 2019-11-14 Jan Beulich <jbeulich@suse.com>
39 * i386-gen.c (opcode_modifiers): Add AnySize entry.
40 (operand_types): Remove AnySize entry.
41 * i386-opc.h (AnySize): Move between enums.
42 (struct i386_opcode_modifier): Add anysize field.
43 (OTUnused): Un-comment.
44 (union i386_operand_type): Remove anysize field.
45 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
46 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
47 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
49 * i386-tbl.h: Re-generate.
51 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
53 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
54 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
55 use the floating point register (FPR).
57 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
59 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
61 (is_mve_encoding_conflict): Update cmode conflict checks for
64 2019-11-12 Jan Beulich <jbeulich@suse.com>
66 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
68 (operand_types): Remove EsSeg entry.
69 (main): Replace stale use of OTMax.
70 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
71 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
73 (OTUnused): Comment out.
74 (union i386_operand_type): Remove esseg field.
75 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
76 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
77 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
78 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
79 * i386-init.h, i386-tbl.h: Re-generate.
81 2019-11-12 Jan Beulich <jbeulich@suse.com>
83 * i386-gen.c (operand_instances): Add RegB entry.
84 * i386-opc.h (enum operand_instance): Add RegB.
85 * i386-opc.tbl (RegC, RegD, RegB): Define.
86 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
87 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
88 monitorx, mwaitx): Drop ImmExt and convert encodings
90 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
91 (edx, rdx): Add Instance=RegD.
92 (ebx, rbx): Add Instance=RegB.
93 * i386-tbl.h: Re-generate.
95 2019-11-12 Jan Beulich <jbeulich@suse.com>
97 * i386-gen.c (operand_type_init): Adjust
98 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
99 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
100 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
101 (operand_instances): New.
102 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
103 (output_operand_type): New parameter "instance". Process it.
104 (process_i386_operand_type): New local variable "instance".
105 (main): Adjust static assertions.
106 * i386-opc.h (INSTANCE_WIDTH): Define.
107 (enum operand_instance): New.
108 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
109 (union i386_operand_type): Replace acc, inoutportreg, and
110 shiftcount by instance.
111 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
112 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
114 * i386-init.h, i386-tbl.h: Re-generate.
116 2019-11-11 Jan Beulich <jbeulich@suse.com>
118 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
119 smaxp/sminp entries' "tied_operand" field to 2.
121 2019-11-11 Jan Beulich <jbeulich@suse.com>
123 * aarch64-opc.c (operand_general_constraint_met_p): Replace
124 "index" local variable by that of the already existing "num".
126 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
129 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
130 * i386-tbl.h: Regenerated.
132 2019-11-08 Jan Beulich <jbeulich@suse.com>
134 * i386-gen.c (operand_type_init): Add Class= to
135 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
136 OPERAND_TYPE_REGBND entry.
137 (operand_classes): Add RegMask and RegBND entries.
138 (operand_types): Drop RegMask and RegBND entry.
139 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
140 (RegMask, RegBND): Delete.
141 (union i386_operand_type): Remove regmask and regbnd fields.
142 * i386-opc.tbl (RegMask, RegBND): Define.
143 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
145 * i386-init.h, i386-tbl.h: Re-generate.
147 2019-11-08 Jan Beulich <jbeulich@suse.com>
149 * i386-gen.c (operand_type_init): Add Class= to
150 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
151 OPERAND_TYPE_REGZMM entries.
152 (operand_classes): Add RegMMX and RegSIMD entries.
153 (operand_types): Drop RegMMX and RegSIMD entries.
154 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
155 (RegMMX, RegSIMD): Delete.
156 (union i386_operand_type): Remove regmmx and regsimd fields.
157 * i386-opc.tbl (RegMMX): Define.
158 (RegXMM, RegYMM, RegZMM): Add Class=.
159 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
161 * i386-init.h, i386-tbl.h: Re-generate.
163 2019-11-08 Jan Beulich <jbeulich@suse.com>
165 * i386-gen.c (operand_type_init): Add Class= to
166 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
168 (operand_classes): Add RegCR, RegDR, and RegTR entries.
169 (operand_types): Drop Control, Debug, and Test entries.
170 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
171 (Control, Debug, Test): Delete.
172 (union i386_operand_type): Remove control, debug, and test
174 * i386-opc.tbl (Control, Debug, Test): Define.
175 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
176 Class=RegDR, and Test by Class=RegTR.
177 * i386-init.h, i386-tbl.h: Re-generate.
179 2019-11-08 Jan Beulich <jbeulich@suse.com>
181 * i386-gen.c (operand_type_init): Add Class= to
182 OPERAND_TYPE_SREG entry.
183 (operand_classes): Add SReg entry.
184 (operand_types): Drop SReg entry.
185 * i386-opc.h (enum operand_class): Add SReg.
187 (union i386_operand_type): Remove sreg field.
188 * i386-opc.tbl (SReg): Define.
189 * i386-reg.tbl: Replace SReg by Class=SReg.
190 * i386-init.h, i386-tbl.h: Re-generate.
192 2019-11-08 Jan Beulich <jbeulich@suse.com>
194 * i386-gen.c (operand_type_init): Add Class=. New
195 OPERAND_TYPE_ANYIMM entry.
196 (operand_classes): New.
197 (operand_types): Drop Reg entry.
198 (output_operand_type): New parameter "class". Process it.
199 (process_i386_operand_type): New local variable "class".
200 (main): Adjust static assertions.
201 * i386-opc.h (CLASS_WIDTH): Define.
202 (enum operand_class): New.
203 (Reg): Replace by Class. Adjust comment.
204 (union i386_operand_type): Replace reg by class.
205 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
207 * i386-reg.tbl: Replace Reg by Class=Reg.
208 * i386-init.h: Re-generate.
210 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
212 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
213 (aarch64_opcode_table): Add data gathering hint mnemonic.
214 * opcodes/aarch64-dis-2.c: Account for new instruction.
216 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
218 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
221 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
223 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
224 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
225 aarch64_feature_f64mm): New feature sets.
226 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
227 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
229 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
231 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
232 (OP_SVE_QQQ): New qualifier.
233 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
234 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
235 the movprfx constraint.
236 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
237 (aarch64_opcode_table): Define new instructions smmla,
238 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
240 * aarch64-opc.c (operand_general_constraint_met_p): Handle
241 AARCH64_OPND_SVE_ADDR_RI_S4x32.
242 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
243 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
244 Account for new instructions.
245 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
247 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
249 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
250 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
252 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
254 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
255 (neon_opcodes): Add bfloat SIMD instructions.
256 (print_insn_coprocessor): Add new control character %b to print
257 condition code without checking cp_num.
258 (print_insn_neon): Account for BFloat16 instructions that have no
259 special top-byte handling.
261 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
262 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
264 * arm-dis.c (print_insn_coprocessor,
265 print_insn_generic_coprocessor): Create wrapper functions around
266 the implementation of the print_insn_coprocessor control codes.
267 (print_insn_coprocessor_1): Original print_insn_coprocessor
268 function that now takes which array to look at as an argument.
269 (print_insn_arm): Use both print_insn_coprocessor and
270 print_insn_generic_coprocessor.
271 (print_insn_thumb32): As above.
273 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
274 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
276 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
277 in reglane special case.
278 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
279 aarch64_find_next_opcode): Account for new instructions.
280 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
281 in reglane special case.
282 * aarch64-opc.c (struct operand_qualifier_data): Add data for
283 new AARCH64_OPND_QLF_S_2H qualifier.
284 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
285 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
286 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
288 (BFLOAT_SVE, BFLOAT): New feature set macros.
289 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
291 (aarch64_opcode_table): Define new instructions bfdot,
292 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
295 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
296 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
298 * aarch64-tbl.h (ARMV8_6): New macro.
300 2019-11-07 Jan Beulich <jbeulich@suse.com>
302 * i386-dis.c (prefix_table): Add mcommit.
303 (rm_table): Add rdpru.
304 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
305 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
306 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
307 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
308 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
309 * i386-opc.tbl (mcommit, rdpru): New.
310 * i386-init.h, i386-tbl.h: Re-generate.
312 2019-11-07 Jan Beulich <jbeulich@suse.com>
314 * i386-dis.c (OP_Mwait): Drop local variable "names", use
316 (OP_Monitor): Drop local variable "op1_names", re-purpose
317 "names" for it instead, and replace former "names" uses by
320 2019-11-07 Jan Beulich <jbeulich@suse.com>
323 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
325 * opcodes/i386-tbl.h: Re-generate.
327 2019-11-05 Jan Beulich <jbeulich@suse.com>
329 * i386-dis.c (OP_Mwaitx): Delete.
330 (prefix_table): Use OP_Mwait for mwaitx entry.
331 (OP_Mwait): Also handle mwaitx.
333 2019-11-05 Jan Beulich <jbeulich@suse.com>
335 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
336 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
337 (prefix_table): Add respective entries.
338 (rm_table): Link to those entries.
340 2019-11-05 Jan Beulich <jbeulich@suse.com>
342 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
343 (REG_0F1C_P_0_MOD_0): ... this.
344 (REG_0F1E_MOD_3): Rename to ...
345 (REG_0F1E_P_1_MOD_3): ... this.
346 (RM_0F01_REG_5): Rename to ...
347 (RM_0F01_REG_5_MOD_3): ... this.
348 (RM_0F01_REG_7): Rename to ...
349 (RM_0F01_REG_7_MOD_3): ... this.
350 (RM_0F1E_MOD_3_REG_7): Rename to ...
351 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
352 (RM_0FAE_REG_6): Rename to ...
353 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
354 (RM_0FAE_REG_7): Rename to ...
355 (RM_0FAE_REG_7_MOD_3): ... this.
356 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
357 (PREFIX_0F01_REG_5_MOD_0): ... this.
358 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
359 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
360 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
361 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
362 (PREFIX_0FAE_REG_0): Rename to ...
363 (PREFIX_0FAE_REG_0_MOD_3): ... this.
364 (PREFIX_0FAE_REG_1): Rename to ...
365 (PREFIX_0FAE_REG_1_MOD_3): ... this.
366 (PREFIX_0FAE_REG_2): Rename to ...
367 (PREFIX_0FAE_REG_2_MOD_3): ... this.
368 (PREFIX_0FAE_REG_3): Rename to ...
369 (PREFIX_0FAE_REG_3_MOD_3): ... this.
370 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
371 (PREFIX_0FAE_REG_4_MOD_0): ... this.
372 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
373 (PREFIX_0FAE_REG_4_MOD_3): ... this.
374 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
375 (PREFIX_0FAE_REG_5_MOD_0): ... this.
376 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
377 (PREFIX_0FAE_REG_5_MOD_3): ... this.
378 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
379 (PREFIX_0FAE_REG_6_MOD_0): ... this.
380 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
381 (PREFIX_0FAE_REG_6_MOD_3): ... this.
382 (PREFIX_0FAE_REG_7): Rename to ...
383 (PREFIX_0FAE_REG_7_MOD_0): ... this.
384 (PREFIX_MOD_0_0FC3): Rename to ...
385 (PREFIX_0FC3_MOD_0): ... this.
386 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
387 (PREFIX_0FC7_REG_6_MOD_0): ... this.
388 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
389 (PREFIX_0FC7_REG_6_MOD_3): ... this.
390 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
391 (PREFIX_0FC7_REG_7_MOD_3): ... this.
392 (reg_table, prefix_table, mod_table, rm_table): Adjust
395 2019-11-04 Nick Clifton <nickc@redhat.com>
397 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
398 of a v850 system register. Move the v850_sreg_names array into
400 (get_v850_reg_name): Likewise for ordinary register names.
401 (get_v850_vreg_name): Likewise for vector register names.
402 (get_v850_cc_name): Likewise for condition codes.
403 * get_v850_float_cc_name): Likewise for floating point condition
405 (get_v850_cacheop_name): Likewise for cache-ops.
406 (get_v850_prefop_name): Likewise for pref-ops.
407 (disassemble): Use the new accessor functions.
409 2019-10-30 Delia Burduv <delia.burduv@arm.com>
411 * aarch64-opc.c (print_immediate_offset_address): Don't print the
412 immediate for the writeback form of ldraa/ldrab if it is 0.
413 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
414 * aarch64-opc-2.c: Regenerated.
416 2019-10-30 Jan Beulich <jbeulich@suse.com>
418 * i386-gen.c (operand_type_shorthands): Delete.
419 (operand_type_init): Expand previous shorthands.
420 (set_bitfield_from_shorthand): Rename back to ...
421 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
422 of operand_type_init[].
423 (set_bitfield): Adjust call to the above function.
424 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
425 RegXMM, RegYMM, RegZMM): Define.
426 * i386-reg.tbl: Expand prior shorthands.
428 2019-10-30 Jan Beulich <jbeulich@suse.com>
430 * i386-gen.c (output_i386_opcode): Change order of fields
432 * i386-opc.h (struct insn_template): Move operands field.
433 Convert extension_opcode field to unsigned short.
434 * i386-tbl.h: Re-generate.
436 2019-10-30 Jan Beulich <jbeulich@suse.com>
438 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
440 * i386-opc.h (W): Extend comment.
441 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
442 general purpose variants not allowing for byte operands.
443 * i386-tbl.h: Re-generate.
445 2019-10-29 Nick Clifton <nickc@redhat.com>
447 * tic30-dis.c (print_branch): Correct size of operand array.
449 2019-10-29 Nick Clifton <nickc@redhat.com>
451 * d30v-dis.c (print_insn): Check that operand index is valid
452 before attempting to access the operands array.
454 2019-10-29 Nick Clifton <nickc@redhat.com>
456 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
457 locating the bit to be tested.
459 2019-10-29 Nick Clifton <nickc@redhat.com>
461 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
463 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
464 (print_insn_s12z): Check for illegal size values.
466 2019-10-28 Nick Clifton <nickc@redhat.com>
468 * csky-dis.c (csky_chars_to_number): Check for a negative
469 count. Use an unsigned integer to construct the return value.
471 2019-10-28 Nick Clifton <nickc@redhat.com>
473 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
474 operand buffer. Set value to 15 not 13.
475 (get_register_operand): Use OPERAND_BUFFER_LEN.
476 (get_indirect_operand): Likewise.
477 (print_two_operand): Likewise.
478 (print_three_operand): Likewise.
479 (print_oar_insn): Likewise.
481 2019-10-28 Nick Clifton <nickc@redhat.com>
483 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
484 (bit_extract_simple): Likewise.
485 (bit_copy): Likewise.
486 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
487 index_offset array are not accessed.
489 2019-10-28 Nick Clifton <nickc@redhat.com>
491 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
494 2019-10-25 Nick Clifton <nickc@redhat.com>
496 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
497 access to opcodes.op array element.
499 2019-10-23 Nick Clifton <nickc@redhat.com>
501 * rx-dis.c (get_register_name): Fix spelling typo in error
503 (get_condition_name, get_flag_name, get_double_register_name)
504 (get_double_register_high_name, get_double_register_low_name)
505 (get_double_control_register_name, get_double_condition_name)
506 (get_opsize_name, get_size_name): Likewise.
508 2019-10-22 Nick Clifton <nickc@redhat.com>
510 * rx-dis.c (get_size_name): New function. Provides safe
511 access to name array.
512 (get_opsize_name): Likewise.
513 (print_insn_rx): Use the accessor functions.
515 2019-10-16 Nick Clifton <nickc@redhat.com>
517 * rx-dis.c (get_register_name): New function. Provides safe
518 access to name array.
519 (get_condition_name, get_flag_name, get_double_register_name)
520 (get_double_register_high_name, get_double_register_low_name)
521 (get_double_control_register_name, get_double_condition_name):
523 (print_insn_rx): Use the accessor functions.
525 2019-10-09 Nick Clifton <nickc@redhat.com>
528 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
531 2019-10-07 Jan Beulich <jbeulich@suse.com>
533 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
534 (cmpsd): Likewise. Move EsSeg to other operand.
535 * opcodes/i386-tbl.h: Re-generate.
537 2019-09-23 Alan Modra <amodra@gmail.com>
539 * m68k-dis.c: Include cpu-m68k.h
541 2019-09-23 Alan Modra <amodra@gmail.com>
543 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
544 "elf/mips.h" earlier.
546 2018-09-20 Jan Beulich <jbeulich@suse.com>
549 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
551 * i386-tbl.h: Re-generate.
553 2019-09-18 Alan Modra <amodra@gmail.com>
555 * arc-ext.c: Update throughout for bfd section macro changes.
557 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
559 * Makefile.in: Re-generate.
560 * configure: Re-generate.
562 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
564 * riscv-opc.c (riscv_opcodes): Change subset field
565 to insn_class field for all instructions.
566 (riscv_insn_types): Likewise.
568 2019-09-16 Phil Blundell <pb@pbcl.net>
570 * configure: Regenerated.
572 2019-09-10 Miod Vallat <miod@online.fr>
575 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
577 2019-09-09 Phil Blundell <pb@pbcl.net>
579 binutils 2.33 branch created.
581 2019-09-03 Nick Clifton <nickc@redhat.com>
584 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
585 greater than zero before indexing via (bufcnt -1).
587 2019-09-03 Nick Clifton <nickc@redhat.com>
590 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
591 (MAX_SPEC_REG_NAME_LEN): Define.
592 (struct mmix_dis_info): Use defined constants for array lengths.
593 (get_reg_name): New function.
594 (get_sprec_reg_name): New function.
595 (print_insn_mmix): Use new functions.
597 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
599 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
600 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
601 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
603 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
605 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
606 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
607 (aarch64_sys_reg_supported_p): Update checks for the above.
609 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
611 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
612 cases MVE_SQRSHRL and MVE_UQRSHLL.
613 (print_insn_mve): Add case for specifier 'k' to check
614 specific bit of the instruction.
616 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
619 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
620 encountering an unknown machine type.
621 (print_insn_arc): Handle arc_insn_length returning 0. In error
622 cases return -1 rather than calling abort.
624 2019-08-07 Jan Beulich <jbeulich@suse.com>
626 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
627 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
629 * i386-tbl.h: Re-generate.
631 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
633 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
636 2019-07-30 Mel Chen <mel.chen@sifive.com>
638 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
639 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
641 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
644 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
646 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
647 and MPY class instructions.
648 (parse_option): Add nps400 option.
649 (print_arc_disassembler_options): Add nps400 info.
651 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
653 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
656 * arc-opc.c (RAD_CHK): Add.
657 * arc-tbl.h: Regenerate.
659 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
661 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
662 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
664 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
666 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
667 instructions as UNPREDICTABLE.
669 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
671 * bpf-desc.c: Regenerated.
673 2019-07-17 Jan Beulich <jbeulich@suse.com>
675 * i386-gen.c (static_assert): Define.
677 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
678 (Opcode_Modifier_Num): ... this.
681 2019-07-16 Jan Beulich <jbeulich@suse.com>
683 * i386-gen.c (operand_types): Move RegMem ...
684 (opcode_modifiers): ... here.
685 * i386-opc.h (RegMem): Move to opcode modifer enum.
686 (union i386_operand_type): Move regmem field ...
687 (struct i386_opcode_modifier): ... here.
688 * i386-opc.tbl (RegMem): Define.
689 (mov, movq): Move RegMem on segment, control, debug, and test
691 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
692 to non-SSE2AVX flavor.
693 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
694 Move RegMem on register only flavors. Drop IgnoreSize from
695 legacy encoding flavors.
696 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
698 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
699 register only flavors.
700 (vmovd): Move RegMem and drop IgnoreSize on register only
701 flavor. Change opcode and operand order to store form.
702 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
704 2019-07-16 Jan Beulich <jbeulich@suse.com>
706 * i386-gen.c (operand_type_init, operand_types): Replace SReg
708 * i386-opc.h (SReg2, SReg3): Replace by ...
710 (union i386_operand_type): Replace sreg fields.
711 * i386-opc.tbl (mov, ): Use SReg.
712 (push, pop): Likewies. Drop i386 and x86-64 specific segment
714 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
715 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
717 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
719 * bpf-desc.c: Regenerate.
720 * bpf-opc.c: Likewise.
721 * bpf-opc.h: Likewise.
723 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
725 * bpf-desc.c: Regenerate.
726 * bpf-opc.c: Likewise.
728 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
730 * arm-dis.c (print_insn_coprocessor): Rename index to
733 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
735 * riscv-opc.c (riscv_insn_types): Add r4 type.
737 * riscv-opc.c (riscv_insn_types): Add b and j type.
739 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
740 format for sb type and correct s type.
742 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
744 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
745 SVE FMOV alias of FCPY.
747 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
749 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
750 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
752 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
754 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
755 registers in an instruction prefixed by MOVPRFX.
757 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
759 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
760 sve_size_13 icode to account for variant behaviour of
762 * aarch64-dis-2.c: Regenerate.
763 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
764 sve_size_13 icode to account for variant behaviour of
766 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
767 (OP_SVE_VVV_Q_D): Add new qualifier.
768 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
769 (struct aarch64_opcode): Split pmull{t,b} into those requiring
772 2019-07-01 Jan Beulich <jbeulich@suse.com>
774 * opcodes/i386-gen.c (operand_type_init): Remove
775 OPERAND_TYPE_VEC_IMM4 entry.
776 (operand_types): Remove Vec_Imm4.
777 * opcodes/i386-opc.h (Vec_Imm4): Delete.
778 (union i386_operand_type): Remove vec_imm4.
779 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
780 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
782 2019-07-01 Jan Beulich <jbeulich@suse.com>
784 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
785 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
786 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
787 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
788 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
789 monitorx, mwaitx): Drop ImmExt from operand-less forms.
790 * i386-tbl.h: Re-generate.
792 2019-07-01 Jan Beulich <jbeulich@suse.com>
794 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
796 * i386-tbl.h: Re-generate.
798 2019-07-01 Jan Beulich <jbeulich@suse.com>
800 * i386-opc.tbl (C): New.
801 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
802 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
803 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
804 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
805 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
806 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
807 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
808 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
809 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
810 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
811 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
812 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
813 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
814 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
815 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
816 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
817 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
818 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
819 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
820 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
821 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
822 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
823 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
824 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
825 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
826 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
828 * i386-tbl.h: Re-generate.
830 2019-07-01 Jan Beulich <jbeulich@suse.com>
832 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
834 * i386-tbl.h: Re-generate.
836 2019-07-01 Jan Beulich <jbeulich@suse.com>
838 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
839 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
840 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
841 * i386-tbl.h: Re-generate.
843 2019-07-01 Jan Beulich <jbeulich@suse.com>
845 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
846 Disp8MemShift from register only templates.
847 * i386-tbl.h: Re-generate.
849 2019-07-01 Jan Beulich <jbeulich@suse.com>
851 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
852 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
853 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
854 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
855 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
856 EVEX_W_0F11_P_3_M_1): Delete.
857 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
858 EVEX_W_0F11_P_3): New.
859 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
860 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
861 MOD_EVEX_0F11_PREFIX_3 table entries.
862 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
863 PREFIX_EVEX_0F11 table entries.
864 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
865 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
866 EVEX_W_0F11_P_3_M_{0,1} table entries.
868 2019-07-01 Jan Beulich <jbeulich@suse.com>
870 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
873 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
876 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
877 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
878 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
879 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
880 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
881 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
882 EVEX_LEN_0F38C7_R_6_P_2_W_1.
883 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
884 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
885 PREFIX_EVEX_0F38C6_REG_6 entries.
886 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
887 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
888 EVEX_W_0F38C7_R_6_P_2 entries.
889 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
890 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
891 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
892 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
893 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
894 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
895 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
897 2019-06-27 Jan Beulich <jbeulich@suse.com>
899 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
900 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
901 VEX_LEN_0F2D_P_3): Delete.
902 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
903 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
904 (prefix_table): ... here.
906 2019-06-27 Jan Beulich <jbeulich@suse.com>
908 * i386-dis.c (Iq): Delete.
910 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
912 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
913 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
914 (OP_E_memory): Also honor needindex when deciding whether an
915 address size prefix needs printing.
916 (OP_I): Remove handling of q_mode. Add handling of d_mode.
918 2019-06-26 Jim Wilson <jimw@sifive.com>
921 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
922 Set info->display_endian to info->endian_code.
924 2019-06-25 Jan Beulich <jbeulich@suse.com>
926 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
927 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
928 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
929 OPERAND_TYPE_ACC64 entries.
930 * i386-init.h: Re-generate.
932 2019-06-25 Jan Beulich <jbeulich@suse.com>
934 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
936 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
938 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
940 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
941 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
943 2019-06-25 Jan Beulich <jbeulich@suse.com>
945 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
948 2019-06-25 Jan Beulich <jbeulich@suse.com>
950 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
951 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
953 * i386-opc.tbl (movnti): Add IgnoreSize.
954 * i386-tbl.h: Re-generate.
956 2019-06-25 Jan Beulich <jbeulich@suse.com>
958 * i386-opc.tbl (and): Mark Imm8S form for optimization.
959 * i386-tbl.h: Re-generate.
961 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
963 * i386-dis-evex.h: Break into ...
964 * i386-dis-evex-len.h: New file.
965 * i386-dis-evex-mod.h: Likewise.
966 * i386-dis-evex-prefix.h: Likewise.
967 * i386-dis-evex-reg.h: Likewise.
968 * i386-dis-evex-w.h: Likewise.
969 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
970 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
973 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
976 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
977 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
979 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
980 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
981 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
982 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
983 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
984 EVEX_LEN_0F385B_P_2_W_1.
985 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
986 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
987 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
988 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
989 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
990 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
991 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
992 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
993 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
994 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
996 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
999 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1000 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1001 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1002 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1003 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1004 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1005 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1006 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1007 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1008 EVEX_LEN_0F3A43_P_2_W_1.
1009 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1010 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1011 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1012 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1013 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1014 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1015 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1016 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1017 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1018 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1019 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1020 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1022 2019-06-14 Nick Clifton <nickc@redhat.com>
1024 * po/fr.po; Updated French translation.
1026 2019-06-13 Stafford Horne <shorne@gmail.com>
1028 * or1k-asm.c: Regenerated.
1029 * or1k-desc.c: Regenerated.
1030 * or1k-desc.h: Regenerated.
1031 * or1k-dis.c: Regenerated.
1032 * or1k-ibld.c: Regenerated.
1033 * or1k-opc.c: Regenerated.
1034 * or1k-opc.h: Regenerated.
1035 * or1k-opinst.c: Regenerated.
1037 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1039 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1041 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1044 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1045 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1046 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1047 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1048 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1049 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1050 EVEX_LEN_0F3A1B_P_2_W_1.
1051 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1052 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1053 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1054 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1055 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1056 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1057 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1058 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1060 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1063 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1064 EVEX.vvvv when disassembling VEX and EVEX instructions.
1065 (OP_VEX): Set vex.register_specifier to 0 after readding
1066 vex.register_specifier.
1067 (OP_Vex_2src_1): Likewise.
1068 (OP_Vex_2src_2): Likewise.
1069 (OP_LWP_E): Likewise.
1070 (OP_EX_Vex): Don't check vex.register_specifier.
1071 (OP_XMM_Vex): Likewise.
1073 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1074 Lili Cui <lili.cui@intel.com>
1076 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1077 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1079 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1080 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1081 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1082 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1083 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1084 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1085 * i386-init.h: Regenerated.
1086 * i386-tbl.h: Likewise.
1088 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1089 Lili Cui <lili.cui@intel.com>
1091 * doc/c-i386.texi: Document enqcmd.
1092 * testsuite/gas/i386/enqcmd-intel.d: New file.
1093 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1094 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1095 * testsuite/gas/i386/enqcmd.d: Likewise.
1096 * testsuite/gas/i386/enqcmd.s: Likewise.
1097 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1098 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1099 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1100 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1101 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1102 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1103 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1106 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1108 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1110 2019-06-03 Alan Modra <amodra@gmail.com>
1112 * ppc-dis.c (prefix_opcd_indices): Correct size.
1114 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1117 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1119 * i386-tbl.h: Regenerated.
1121 2019-05-24 Alan Modra <amodra@gmail.com>
1123 * po/POTFILES.in: Regenerate.
1125 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1126 Alan Modra <amodra@gmail.com>
1128 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1129 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1130 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1131 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1132 XTOP>): Define and add entries.
1133 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1134 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1135 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1136 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1138 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1139 Alan Modra <amodra@gmail.com>
1141 * ppc-dis.c (ppc_opts): Add "future" entry.
1142 (PREFIX_OPCD_SEGS): Define.
1143 (prefix_opcd_indices): New array.
1144 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1145 (lookup_prefix): New function.
1146 (print_insn_powerpc): Handle 64-bit prefix instructions.
1147 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1148 (PMRR, POWERXX): Define.
1149 (prefix_opcodes): New instruction table.
1150 (prefix_num_opcodes): New constant.
1152 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1154 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1155 * configure: Regenerated.
1156 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1158 (HFILES): Add bpf-desc.h and bpf-opc.h.
1159 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1160 bpf-ibld.c and bpf-opc.c.
1162 * Makefile.in: Regenerated.
1163 * disassemble.c (ARCH_bpf): Define.
1164 (disassembler): Add case for bfd_arch_bpf.
1165 (disassemble_init_for_target): Likewise.
1166 (enum epbf_isa_attr): Define.
1167 * disassemble.h: extern print_insn_bpf.
1168 * bpf-asm.c: Generated.
1169 * bpf-opc.h: Likewise.
1170 * bpf-opc.c: Likewise.
1171 * bpf-ibld.c: Likewise.
1172 * bpf-dis.c: Likewise.
1173 * bpf-desc.h: Likewise.
1174 * bpf-desc.c: Likewise.
1176 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1178 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1179 and VMSR with the new operands.
1181 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1183 * arm-dis.c (enum mve_instructions): New enum
1184 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1186 (mve_opcodes): New instructions as above.
1187 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1189 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1191 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1193 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1194 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1195 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1196 uqshl, urshrl and urshr.
1197 (is_mve_okay_in_it): Add new instructions to TRUE list.
1198 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1199 (print_insn_mve): Updated to accept new %j,
1200 %<bitfield>m and %<bitfield>n patterns.
1202 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1204 * mips-opc.c (mips_builtin_opcodes): Change source register
1205 constraint for DAUI.
1207 2019-05-20 Nick Clifton <nickc@redhat.com>
1209 * po/fr.po: Updated French translation.
1211 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1212 Michael Collison <michael.collison@arm.com>
1214 * arm-dis.c (thumb32_opcodes): Add new instructions.
1215 (enum mve_instructions): Likewise.
1216 (enum mve_undefined): Add new reasons.
1217 (is_mve_encoding_conflict): Handle new instructions.
1218 (is_mve_undefined): Likewise.
1219 (is_mve_unpredictable): Likewise.
1220 (print_mve_undefined): Likewise.
1221 (print_mve_size): Likewise.
1223 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1224 Michael Collison <michael.collison@arm.com>
1226 * arm-dis.c (thumb32_opcodes): Add new instructions.
1227 (enum mve_instructions): Likewise.
1228 (is_mve_encoding_conflict): Handle new instructions.
1229 (is_mve_undefined): Likewise.
1230 (is_mve_unpredictable): Likewise.
1231 (print_mve_size): Likewise.
1233 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1234 Michael Collison <michael.collison@arm.com>
1236 * arm-dis.c (thumb32_opcodes): Add new instructions.
1237 (enum mve_instructions): Likewise.
1238 (is_mve_encoding_conflict): Likewise.
1239 (is_mve_unpredictable): Likewise.
1240 (print_mve_size): Likewise.
1242 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1243 Michael Collison <michael.collison@arm.com>
1245 * arm-dis.c (thumb32_opcodes): Add new instructions.
1246 (enum mve_instructions): Likewise.
1247 (is_mve_encoding_conflict): Handle new instructions.
1248 (is_mve_undefined): Likewise.
1249 (is_mve_unpredictable): Likewise.
1250 (print_mve_size): Likewise.
1252 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1253 Michael Collison <michael.collison@arm.com>
1255 * arm-dis.c (thumb32_opcodes): Add new instructions.
1256 (enum mve_instructions): Likewise.
1257 (is_mve_encoding_conflict): Handle new instructions.
1258 (is_mve_undefined): Likewise.
1259 (is_mve_unpredictable): Likewise.
1260 (print_mve_size): Likewise.
1261 (print_insn_mve): Likewise.
1263 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1264 Michael Collison <michael.collison@arm.com>
1266 * arm-dis.c (thumb32_opcodes): Add new instructions.
1267 (print_insn_thumb32): Handle new instructions.
1269 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1270 Michael Collison <michael.collison@arm.com>
1272 * arm-dis.c (enum mve_instructions): Add new instructions.
1273 (enum mve_undefined): Add new reasons.
1274 (is_mve_encoding_conflict): Handle new instructions.
1275 (is_mve_undefined): Likewise.
1276 (is_mve_unpredictable): Likewise.
1277 (print_mve_undefined): Likewise.
1278 (print_mve_size): Likewise.
1279 (print_mve_shift_n): Likewise.
1280 (print_insn_mve): Likewise.
1282 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1283 Michael Collison <michael.collison@arm.com>
1285 * arm-dis.c (enum mve_instructions): Add new instructions.
1286 (is_mve_encoding_conflict): Handle new instructions.
1287 (is_mve_unpredictable): Likewise.
1288 (print_mve_rotate): Likewise.
1289 (print_mve_size): Likewise.
1290 (print_insn_mve): Likewise.
1292 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1293 Michael Collison <michael.collison@arm.com>
1295 * arm-dis.c (enum mve_instructions): Add new instructions.
1296 (is_mve_encoding_conflict): Handle new instructions.
1297 (is_mve_unpredictable): Likewise.
1298 (print_mve_size): Likewise.
1299 (print_insn_mve): Likewise.
1301 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1302 Michael Collison <michael.collison@arm.com>
1304 * arm-dis.c (enum mve_instructions): Add new instructions.
1305 (enum mve_undefined): Add new reasons.
1306 (is_mve_encoding_conflict): Handle new instructions.
1307 (is_mve_undefined): Likewise.
1308 (is_mve_unpredictable): Likewise.
1309 (print_mve_undefined): Likewise.
1310 (print_mve_size): Likewise.
1311 (print_insn_mve): Likewise.
1313 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1314 Michael Collison <michael.collison@arm.com>
1316 * arm-dis.c (enum mve_instructions): Add new instructions.
1317 (is_mve_encoding_conflict): Handle new instructions.
1318 (is_mve_undefined): Likewise.
1319 (is_mve_unpredictable): Likewise.
1320 (print_mve_size): Likewise.
1321 (print_insn_mve): Likewise.
1323 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1324 Michael Collison <michael.collison@arm.com>
1326 * arm-dis.c (enum mve_instructions): Add new instructions.
1327 (enum mve_unpredictable): Add new reasons.
1328 (enum mve_undefined): Likewise.
1329 (is_mve_okay_in_it): Handle new isntructions.
1330 (is_mve_encoding_conflict): Likewise.
1331 (is_mve_undefined): Likewise.
1332 (is_mve_unpredictable): Likewise.
1333 (print_mve_vmov_index): Likewise.
1334 (print_simd_imm8): Likewise.
1335 (print_mve_undefined): Likewise.
1336 (print_mve_unpredictable): Likewise.
1337 (print_mve_size): Likewise.
1338 (print_insn_mve): Likewise.
1340 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1341 Michael Collison <michael.collison@arm.com>
1343 * arm-dis.c (enum mve_instructions): Add new instructions.
1344 (enum mve_unpredictable): Add new reasons.
1345 (enum mve_undefined): Likewise.
1346 (is_mve_encoding_conflict): Handle new instructions.
1347 (is_mve_undefined): Likewise.
1348 (is_mve_unpredictable): Likewise.
1349 (print_mve_undefined): Likewise.
1350 (print_mve_unpredictable): Likewise.
1351 (print_mve_rounding_mode): Likewise.
1352 (print_mve_vcvt_size): Likewise.
1353 (print_mve_size): Likewise.
1354 (print_insn_mve): Likewise.
1356 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1357 Michael Collison <michael.collison@arm.com>
1359 * arm-dis.c (enum mve_instructions): Add new instructions.
1360 (enum mve_unpredictable): Add new reasons.
1361 (enum mve_undefined): Likewise.
1362 (is_mve_undefined): Handle new instructions.
1363 (is_mve_unpredictable): Likewise.
1364 (print_mve_undefined): Likewise.
1365 (print_mve_unpredictable): Likewise.
1366 (print_mve_size): Likewise.
1367 (print_insn_mve): Likewise.
1369 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1370 Michael Collison <michael.collison@arm.com>
1372 * arm-dis.c (enum mve_instructions): Add new instructions.
1373 (enum mve_undefined): Add new reasons.
1374 (insns): Add new instructions.
1375 (is_mve_encoding_conflict):
1376 (print_mve_vld_str_addr): New print function.
1377 (is_mve_undefined): Handle new instructions.
1378 (is_mve_unpredictable): Likewise.
1379 (print_mve_undefined): Likewise.
1380 (print_mve_size): Likewise.
1381 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1382 (print_insn_mve): Handle new operands.
1384 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1385 Michael Collison <michael.collison@arm.com>
1387 * arm-dis.c (enum mve_instructions): Add new instructions.
1388 (enum mve_unpredictable): Add new reasons.
1389 (is_mve_encoding_conflict): Handle new instructions.
1390 (is_mve_unpredictable): Likewise.
1391 (mve_opcodes): Add new instructions.
1392 (print_mve_unpredictable): Handle new reasons.
1393 (print_mve_register_blocks): New print function.
1394 (print_mve_size): Handle new instructions.
1395 (print_insn_mve): Likewise.
1397 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1398 Michael Collison <michael.collison@arm.com>
1400 * arm-dis.c (enum mve_instructions): Add new instructions.
1401 (enum mve_unpredictable): Add new reasons.
1402 (enum mve_undefined): Likewise.
1403 (is_mve_encoding_conflict): Handle new instructions.
1404 (is_mve_undefined): Likewise.
1405 (is_mve_unpredictable): Likewise.
1406 (coprocessor_opcodes): Move NEON VDUP from here...
1407 (neon_opcodes): ... to here.
1408 (mve_opcodes): Add new instructions.
1409 (print_mve_undefined): Handle new reasons.
1410 (print_mve_unpredictable): Likewise.
1411 (print_mve_size): Handle new instructions.
1412 (print_insn_neon): Handle vdup.
1413 (print_insn_mve): Handle new operands.
1415 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1416 Michael Collison <michael.collison@arm.com>
1418 * arm-dis.c (enum mve_instructions): Add new instructions.
1419 (enum mve_unpredictable): Add new values.
1420 (mve_opcodes): Add new instructions.
1421 (vec_condnames): New array with vector conditions.
1422 (mve_predicatenames): New array with predicate suffixes.
1423 (mve_vec_sizename): New array with vector sizes.
1424 (enum vpt_pred_state): New enum with vector predication states.
1425 (struct vpt_block): New struct type for vpt blocks.
1426 (vpt_block_state): Global struct to keep track of state.
1427 (mve_extract_pred_mask): New helper function.
1428 (num_instructions_vpt_block): Likewise.
1429 (mark_outside_vpt_block): Likewise.
1430 (mark_inside_vpt_block): Likewise.
1431 (invert_next_predicate_state): Likewise.
1432 (update_next_predicate_state): Likewise.
1433 (update_vpt_block_state): Likewise.
1434 (is_vpt_instruction): Likewise.
1435 (is_mve_encoding_conflict): Add entries for new instructions.
1436 (is_mve_unpredictable): Likewise.
1437 (print_mve_unpredictable): Handle new cases.
1438 (print_instruction_predicate): Likewise.
1439 (print_mve_size): New function.
1440 (print_vec_condition): New function.
1441 (print_insn_mve): Handle vpt blocks and new print operands.
1443 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1445 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1446 8, 14 and 15 for Armv8.1-M Mainline.
1448 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1449 Michael Collison <michael.collison@arm.com>
1451 * arm-dis.c (enum mve_instructions): New enum.
1452 (enum mve_unpredictable): Likewise.
1453 (enum mve_undefined): Likewise.
1454 (struct mopcode32): New struct.
1455 (is_mve_okay_in_it): New function.
1456 (is_mve_architecture): Likewise.
1457 (arm_decode_field): Likewise.
1458 (arm_decode_field_multiple): Likewise.
1459 (is_mve_encoding_conflict): Likewise.
1460 (is_mve_undefined): Likewise.
1461 (is_mve_unpredictable): Likewise.
1462 (print_mve_undefined): Likewise.
1463 (print_mve_unpredictable): Likewise.
1464 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1465 (print_insn_mve): New function.
1466 (print_insn_thumb32): Handle MVE architecture.
1467 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1469 2019-05-10 Nick Clifton <nickc@redhat.com>
1472 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1473 end of the table prematurely.
1475 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1477 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1480 2019-05-11 Alan Modra <amodra@gmail.com>
1482 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1483 when -Mraw is in effect.
1485 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1487 * aarch64-dis-2.c: Regenerate.
1488 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1489 (OP_SVE_BBB): New variant set.
1490 (OP_SVE_DDDD): New variant set.
1491 (OP_SVE_HHH): New variant set.
1492 (OP_SVE_HHHU): New variant set.
1493 (OP_SVE_SSS): New variant set.
1494 (OP_SVE_SSSU): New variant set.
1495 (OP_SVE_SHH): New variant set.
1496 (OP_SVE_SBBU): New variant set.
1497 (OP_SVE_DSS): New variant set.
1498 (OP_SVE_DHHU): New variant set.
1499 (OP_SVE_VMV_HSD_BHS): New variant set.
1500 (OP_SVE_VVU_HSD_BHS): New variant set.
1501 (OP_SVE_VVVU_SD_BH): New variant set.
1502 (OP_SVE_VVVU_BHSD): New variant set.
1503 (OP_SVE_VVV_QHD_DBS): New variant set.
1504 (OP_SVE_VVV_HSD_BHS): New variant set.
1505 (OP_SVE_VVV_HSD_BHS2): New variant set.
1506 (OP_SVE_VVV_BHS_HSD): New variant set.
1507 (OP_SVE_VV_BHS_HSD): New variant set.
1508 (OP_SVE_VVV_SD): New variant set.
1509 (OP_SVE_VVU_BHS_HSD): New variant set.
1510 (OP_SVE_VZVV_SD): New variant set.
1511 (OP_SVE_VZVV_BH): New variant set.
1512 (OP_SVE_VZV_SD): New variant set.
1513 (aarch64_opcode_table): Add sve2 instructions.
1515 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1517 * aarch64-asm-2.c: Regenerated.
1518 * aarch64-dis-2.c: Regenerated.
1519 * aarch64-opc-2.c: Regenerated.
1520 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1521 for SVE_SHLIMM_UNPRED_22.
1522 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1523 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1526 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1528 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1529 sve_size_tsz_bhs iclass encode.
1530 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1531 sve_size_tsz_bhs iclass decode.
1533 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1535 * aarch64-asm-2.c: Regenerated.
1536 * aarch64-dis-2.c: Regenerated.
1537 * aarch64-opc-2.c: Regenerated.
1538 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1539 for SVE_Zm4_11_INDEX.
1540 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1541 (fields): Handle SVE_i2h field.
1542 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1543 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1545 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1547 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1548 sve_shift_tsz_bhsd iclass encode.
1549 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1550 sve_shift_tsz_bhsd iclass decode.
1552 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1554 * aarch64-asm-2.c: Regenerated.
1555 * aarch64-dis-2.c: Regenerated.
1556 * aarch64-opc-2.c: Regenerated.
1557 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1558 (aarch64_encode_variant_using_iclass): Handle
1559 sve_shift_tsz_hsd iclass encode.
1560 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1561 sve_shift_tsz_hsd iclass decode.
1562 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1563 for SVE_SHRIMM_UNPRED_22.
1564 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1565 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1568 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1570 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1571 sve_size_013 iclass encode.
1572 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1573 sve_size_013 iclass decode.
1575 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1577 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1578 sve_size_bh iclass encode.
1579 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1580 sve_size_bh iclass decode.
1582 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1584 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1585 sve_size_sd2 iclass encode.
1586 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1587 sve_size_sd2 iclass decode.
1588 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1589 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1591 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1593 * aarch64-asm-2.c: Regenerated.
1594 * aarch64-dis-2.c: Regenerated.
1595 * aarch64-opc-2.c: Regenerated.
1596 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1598 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1599 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1601 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1603 * aarch64-asm-2.c: Regenerated.
1604 * aarch64-dis-2.c: Regenerated.
1605 * aarch64-opc-2.c: Regenerated.
1606 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1607 for SVE_Zm3_11_INDEX.
1608 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1609 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1610 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1612 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1614 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1616 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1617 sve_size_hsd2 iclass encode.
1618 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1619 sve_size_hsd2 iclass decode.
1620 * aarch64-opc.c (fields): Handle SVE_size field.
1621 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1623 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1625 * aarch64-asm-2.c: Regenerated.
1626 * aarch64-dis-2.c: Regenerated.
1627 * aarch64-opc-2.c: Regenerated.
1628 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1630 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1631 (fields): Handle SVE_rot3 field.
1632 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1633 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1635 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1637 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1640 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1643 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1644 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1645 aarch64_feature_sve2bitperm): New feature sets.
1646 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1647 for feature set addresses.
1648 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1649 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1651 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1652 Faraz Shahbazker <fshahbazker@wavecomp.com>
1654 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1655 argument and set ASE_EVA_R6 appropriately.
1656 (set_default_mips_dis_options): Pass ISA to above.
1657 (parse_mips_dis_option): Likewise.
1658 * mips-opc.c (EVAR6): New macro.
1659 (mips_builtin_opcodes): Add llwpe, scwpe.
1661 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1663 * aarch64-asm-2.c: Regenerated.
1664 * aarch64-dis-2.c: Regenerated.
1665 * aarch64-opc-2.c: Regenerated.
1666 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1667 AARCH64_OPND_TME_UIMM16.
1668 (aarch64_print_operand): Likewise.
1669 * aarch64-tbl.h (QL_IMM_NIL): New.
1672 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1674 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1676 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1678 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1679 Faraz Shahbazker <fshahbazker@wavecomp.com>
1681 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1683 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1685 * s12z-opc.h: Add extern "C" bracketing to help
1686 users who wish to use this interface in c++ code.
1688 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1690 * s12z-opc.c (bm_decode): Handle bit map operations with the
1693 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1695 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1696 specifier. Add entries for VLDR and VSTR of system registers.
1697 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1698 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1699 of %J and %K format specifier.
1701 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1703 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1704 Add new entries for VSCCLRM instruction.
1705 (print_insn_coprocessor): Handle new %C format control code.
1707 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1709 * arm-dis.c (enum isa): New enum.
1710 (struct sopcode32): New structure.
1711 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1712 set isa field of all current entries to ANY.
1713 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1714 Only match an entry if its isa field allows the current mode.
1716 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1718 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1720 (print_insn_thumb32): Add logic to print %n CLRM register list.
1722 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1724 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1727 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1729 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1730 (print_insn_thumb32): Edit the switch case for %Z.
1732 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1734 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1736 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1738 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1740 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1742 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1744 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1746 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1747 Arm register with r13 and r15 unpredictable.
1748 (thumb32_opcodes): New instructions for bfx and bflx.
1750 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1752 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1754 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1756 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1758 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1760 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1762 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1764 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1766 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1768 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1769 "optr". ("operator" is a reserved word in c++).
1771 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1773 * aarch64-opc.c (aarch64_print_operand): Add case for
1775 (verify_constraints): Likewise.
1776 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1777 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1778 to accept Rt|SP as first operand.
1779 (AARCH64_OPERANDS): Add new Rt_SP.
1780 * aarch64-asm-2.c: Regenerated.
1781 * aarch64-dis-2.c: Regenerated.
1782 * aarch64-opc-2.c: Regenerated.
1784 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1786 * aarch64-asm-2.c: Regenerated.
1787 * aarch64-dis-2.c: Likewise.
1788 * aarch64-opc-2.c: Likewise.
1789 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1791 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1793 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1795 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1797 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1798 * i386-init.h: Regenerated.
1800 2019-04-07 Alan Modra <amodra@gmail.com>
1802 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1803 op_separator to control printing of spaces, comma and parens
1804 rather than need_comma, need_paren and spaces vars.
1806 2019-04-07 Alan Modra <amodra@gmail.com>
1809 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1810 (print_insn_neon, print_insn_arm): Likewise.
1812 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1814 * i386-dis-evex.h (evex_table): Updated to support BF16
1816 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1817 and EVEX_W_0F3872_P_3.
1818 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1819 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1820 * i386-opc.h (enum): Add CpuAVX512_BF16.
1821 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1822 * i386-opc.tbl: Add AVX512 BF16 instructions.
1823 * i386-init.h: Regenerated.
1824 * i386-tbl.h: Likewise.
1826 2019-04-05 Alan Modra <amodra@gmail.com>
1828 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1829 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1830 to favour printing of "-" branch hint when using the "y" bit.
1831 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1833 2019-04-05 Alan Modra <amodra@gmail.com>
1835 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1836 opcode until first operand is output.
1838 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1841 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1842 (valid_bo_post_v2): Add support for 'at' branch hints.
1843 (insert_bo): Only error on branch on ctr.
1844 (get_bo_hint_mask): New function.
1845 (insert_boe): Add new 'branch_taken' formal argument. Add support
1846 for inserting 'at' branch hints.
1847 (extract_boe): Add new 'branch_taken' formal argument. Add support
1848 for extracting 'at' branch hints.
1849 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1850 (BOE): Delete operand.
1851 (BOM, BOP): New operands.
1853 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1854 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1855 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1856 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1857 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1858 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1859 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1860 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1861 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1862 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1863 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1864 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1865 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1866 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1867 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1868 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1869 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1870 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1871 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1872 bttarl+>: New extended mnemonics.
1874 2019-03-28 Alan Modra <amodra@gmail.com>
1877 * ppc-opc.c (BTF): Define.
1878 (powerpc_opcodes): Use for mtfsb*.
1879 * ppc-dis.c (print_insn_powerpc): Print fields with both
1880 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1882 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1884 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1885 (mapping_symbol_for_insn): Implement new algorithm.
1886 (print_insn): Remove duplicate code.
1888 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1890 * aarch64-dis.c (print_insn_aarch64):
1893 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1895 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1898 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1900 * aarch64-dis.c (last_stop_offset): New.
1901 (print_insn_aarch64): Use stop_offset.
1903 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1906 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1908 * i386-init.h: Regenerated.
1910 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1913 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1914 vmovdqu16, vmovdqu32 and vmovdqu64.
1915 * i386-tbl.h: Regenerated.
1917 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1919 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1920 from vstrszb, vstrszh, and vstrszf.
1922 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1924 * s390-opc.txt: Add instruction descriptions.
1926 2019-02-08 Jim Wilson <jimw@sifive.com>
1928 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1931 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1933 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1935 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1938 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1939 * aarch64-opc.c (verify_elem_sd): New.
1940 (fields): Add FLD_sz entr.
1941 * aarch64-tbl.h (_SIMD_INSN): New.
1942 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1943 fmulx scalar and vector by element isns.
1945 2019-02-07 Nick Clifton <nickc@redhat.com>
1947 * po/sv.po: Updated Swedish translation.
1949 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1951 * s390-mkopc.c (main): Accept arch13 as cpu string.
1952 * s390-opc.c: Add new instruction formats and instruction opcode
1954 * s390-opc.txt: Add new arch13 instructions.
1956 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1958 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1959 (aarch64_opcode): Change encoding for stg, stzg
1961 * aarch64-asm-2.c: Regenerated.
1962 * aarch64-dis-2.c: Regenerated.
1963 * aarch64-opc-2.c: Regenerated.
1965 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1967 * aarch64-asm-2.c: Regenerated.
1968 * aarch64-dis-2.c: Likewise.
1969 * aarch64-opc-2.c: Likewise.
1970 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1972 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1973 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1975 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1976 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1977 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1978 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1979 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1980 case for ldstgv_indexed.
1981 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1982 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1983 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1984 * aarch64-asm-2.c: Regenerated.
1985 * aarch64-dis-2.c: Regenerated.
1986 * aarch64-opc-2.c: Regenerated.
1988 2019-01-23 Nick Clifton <nickc@redhat.com>
1990 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1992 2019-01-21 Nick Clifton <nickc@redhat.com>
1994 * po/de.po: Updated German translation.
1995 * po/uk.po: Updated Ukranian translation.
1997 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1998 * mips-dis.c (mips_arch_choices): Fix typo in
1999 gs464, gs464e and gs264e descriptors.
2001 2019-01-19 Nick Clifton <nickc@redhat.com>
2003 * configure: Regenerate.
2004 * po/opcodes.pot: Regenerate.
2006 2018-06-24 Nick Clifton <nickc@redhat.com>
2008 2.32 branch created.
2010 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2012 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2014 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2017 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2019 * configure: Regenerate.
2021 2019-01-07 Alan Modra <amodra@gmail.com>
2023 * configure: Regenerate.
2024 * po/POTFILES.in: Regenerate.
2026 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2028 * s12z-opc.c: New file.
2029 * s12z-opc.h: New file.
2030 * s12z-dis.c: Removed all code not directly related to display
2031 of instructions. Used the interface provided by the new files
2033 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2034 * Makefile.in: Regenerate.
2035 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2036 * configure: Regenerate.
2038 2019-01-01 Alan Modra <amodra@gmail.com>
2040 Update year range in copyright notice of all files.
2042 For older changes see ChangeLog-2018
2044 Copyright (C) 2019 Free Software Foundation, Inc.
2046 Copying and distribution of this file, with or without modification,
2047 are permitted in any medium without royalty provided the copyright
2048 notice and this notice are preserved.
2054 version-control: never