opcodes/ChangeLog

   1 2020-02-17  Jan Beulich  <jbeulich@suse.com>
   2
   3         PR gas/6518
   4         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
   5         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
   6         into Intel syntax instance (with Unpsecified) and AT&T one
   7         (without).
   8         (vcvtneps2bf16): Likewise, along with folding the two so far
   9         separate ones.
  10         * i386-tbl.h: Re-generate.
  11
  12 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  15         CPU_ANY_SSE4A_FLAGS.
  16
  17 2020-02-17  Alan Modra  <amodra@gmail.com>
  18
  19         * i386-gen.c (cpu_flag_init): Correct last change.
  20
  21 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  24         CPU_ANY_SSE4_FLAGS.
  25
  26 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  27
  28         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  29         (movzx): Likewise.
  30
  31 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  32
  33         PR gas/25438
  34         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  35         destination for Cpu64-only variant.
  36         (movzx): Fold patterns.
  37         * i386-tbl.h: Re-generate.
  38
  39 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  42         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  43         CPU_ANY_SSE4_FLAGS entry.
  44         * i386-init.h: Re-generate.
  45
  46 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  49         with Unspecified, making the present one AT&T syntax only.
  50         * i386-tbl.h: Re-generate.
  51
  52 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  55         * i386-tbl.h: Re-generate.
  56
  57 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  58
  59         PR gas/24546
  60         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  61         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  62         Amd64 and Intel64 templates.
  63         (call, jmp): Likewise for far indirect variants. Dro
  64         Unspecified.
  65         * i386-tbl.h: Re-generate.
  66
  67 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  70         * i386-opc.h (ShortForm): Delete.
  71         (struct i386_opcode_modifier): Remove shortform field.
  72         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  73         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  74         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  75         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  76         Drop ShortForm.
  77         * i386-tbl.h: Re-generate.
  78
  79 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  82         fucompi): Drop ShortForm from operand-less templates.
  83         * i386-tbl.h: Re-generate.
  84
  85 2020-02-11  Alan Modra  <amodra@gmail.com>
  86
  87         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  88         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  89         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  90         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  91         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  92
  93 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  94
  95         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  96         (cde_opcodes): Add VCX* instructions.
  97
  98 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  99             Matthew Malcomson  <matthew.malcomson@arm.com>
 100
 101         * arm-dis.c (struct cdeopcode32): New.
 102         (CDE_OPCODE): New macro.
 103         (cde_opcodes): New disassembly table.
 104         (regnames): New option to table.
 105         (cde_coprocs): New global variable.
 106         (print_insn_cde): New
 107         (print_insn_thumb32): Use print_insn_cde.
 108         (parse_arm_disassembler_options): Parse coprocN args.
 109
 110 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         PR gas/25516
 113         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 114         with ISA64.
 115         * i386-opc.h (AMD64): Removed.
 116         (Intel64): Likewose.
 117         (AMD64): New.
 118         (INTEL64): Likewise.
 119         (INTEL64ONLY): Likewise.
 120         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 121         * i386-opc.tbl (Amd64): New.
 122         (Intel64): Likewise.
 123         (Intel64Only): Likewise.
 124         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 125         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 126         * i386-tbl.h: Regenerated.
 127
 128 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 129
 130         PR 25469
 131         * z80-dis.c: Add support for GBZ80 opcodes.
 132
 133 2020-02-04  Alan Modra  <amodra@gmail.com>
 134
 135         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 136
 137 2020-02-03  Alan Modra  <amodra@gmail.com>
 138
 139         * m32c-ibld.c: Regenerate.
 140
 141 2020-02-01  Alan Modra  <amodra@gmail.com>
 142
 143         * frv-ibld.c: Regenerate.
 144
 145 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 148         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 149         (OP_E_memory): Replace xmm_mdq_mode case label by
 150         vex_scalar_w_dq_mode one.
 151         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 152
 153 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 156         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 157         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 158         (intel_operand_size): Drop vex_w_dq_mode case label.
 159
 160 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 161
 162         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 163         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 164
 165 2020-01-30  Alan Modra  <amodra@gmail.com>
 166
 167         * m32c-ibld.c: Regenerate.
 168
 169 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 170
 171         * bpf-opc.c: Regenerate.
 172
 173 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 176         (dis386): Use them to replace C2/C3 table entries.
 177         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 178         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 179         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 180         * i386-tbl.h: Re-generate.
 181
 182 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 185         forms.
 186         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 187         DefaultSize.
 188         * i386-tbl.h: Re-generate.
 189
 190 2020-01-30  Alan Modra  <amodra@gmail.com>
 191
 192         * tic4x-dis.c (tic4x_dp): Make unsigned.
 193
 194 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 195             Jan Beulich  <jbeulich@suse.com>
 196
 197         PR binutils/25445
 198         * i386-dis.c (MOVSXD_Fixup): New function.
 199         (movsxd_mode): New enum.
 200         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 201         (intel_operand_size): Handle movsxd_mode.
 202         (OP_E_register): Likewise.
 203         (OP_G): Likewise.
 204         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 205         register on movsxd.  Add movsxd with 16-bit destination register
 206         for AMD64 and Intel64 ISAs.
 207         * i386-tbl.h: Regenerated.
 208
 209 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 210
 211         PR 25403
 212         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 213         * aarch64-asm-2.c: Regenerate
 214         * aarch64-dis-2.c: Likewise.
 215         * aarch64-opc-2.c: Likewise.
 216
 217 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-opc.tbl (sysret): Drop DefaultSize.
 220         * i386-tbl.h: Re-generate.
 221
 222 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 225         Dword.
 226         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 227         * i386-tbl.h: Re-generate.
 228
 229 2020-01-20  Nick Clifton  <nickc@redhat.com>
 230
 231         * po/de.po: Updated German translation.
 232         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 233         * po/uk.po: Updated Ukranian translation.
 234
 235 2020-01-20  Alan Modra  <amodra@gmail.com>
 236
 237         * hppa-dis.c (fput_const): Remove useless cast.
 238
 239 2020-01-20  Alan Modra  <amodra@gmail.com>
 240
 241         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 242
 243 2020-01-18  Nick Clifton  <nickc@redhat.com>
 244
 245         * configure: Regenerate.
 246         * po/opcodes.pot: Regenerate.
 247
 248 2020-01-18  Nick Clifton  <nickc@redhat.com>
 249
 250         Binutils 2.34 branch created.
 251
 252 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 253
 254         * opintl.h: Fix spelling error (seperate).
 255
 256 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 257
 258         * i386-opc.tbl: Add {vex} pseudo prefix.
 259         * i386-tbl.h: Regenerated.
 260
 261 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 262
 263         PR 25376
 264         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 265         (neon_opcodes): Likewise.
 266         (select_arm_features): Make sure we enable MVE bits when selecting
 267         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 268         any architecture.
 269
 270 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-opc.tbl: Drop stale comment from XOP section.
 273
 274 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 277         (extractps): Add VexWIG to SSE2AVX forms.
 278         * i386-tbl.h: Re-generate.
 279
 280 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 283         Size64 from and use VexW1 on SSE2AVX forms.
 284         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 285         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 286         * i386-tbl.h: Re-generate.
 287
 288 2020-01-15  Alan Modra  <amodra@gmail.com>
 289
 290         * tic4x-dis.c (tic4x_version): Make unsigned long.
 291         (optab, optab_special, registernames): New file scope vars.
 292         (tic4x_print_register): Set up registernames rather than
 293         malloc'd registertable.
 294         (tic4x_disassemble): Delete optable and optable_special.  Use
 295         optab and optab_special instead.  Throw away old optab,
 296         optab_special and registernames when info->mach changes.
 297
 298 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 299
 300         PR 25377
 301         * z80-dis.c (suffix): Use .db instruction to generate double
 302         prefix.
 303
 304 2020-01-14  Alan Modra  <amodra@gmail.com>
 305
 306         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 307         values to unsigned before shifting.
 308
 309 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 310
 311         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 312         flow instructions.
 313         (print_insn_thumb16, print_insn_thumb32): Likewise.
 314         (print_insn): Initialize the insn info.
 315         * i386-dis.c (print_insn): Initialize the insn info fields, and
 316         detect jumps.
 317
 318 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 319
 320         * arc-opc.c (C_NE): Make it required.
 321
 322 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 323
 324         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 325         reserved register name.
 326
 327 2020-01-13  Alan Modra  <amodra@gmail.com>
 328
 329         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 330         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 331
 332 2020-01-13  Alan Modra  <amodra@gmail.com>
 333
 334         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 335         result of wasm_read_leb128 in a uint64_t and check that bits
 336         are not lost when copying to other locals.  Use uint32_t for
 337         most locals.  Use PRId64 when printing int64_t.
 338
 339 2020-01-13  Alan Modra  <amodra@gmail.com>
 340
 341         * score-dis.c: Formatting.
 342         * score7-dis.c: Formatting.
 343
 344 2020-01-13  Alan Modra  <amodra@gmail.com>
 345
 346         * score-dis.c (print_insn_score48): Use unsigned variables for
 347         unsigned values.  Don't left shift negative values.
 348         (print_insn_score32): Likewise.
 349         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 350
 351 2020-01-13  Alan Modra  <amodra@gmail.com>
 352
 353         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 354
 355 2020-01-13  Alan Modra  <amodra@gmail.com>
 356
 357         * fr30-ibld.c: Regenerate.
 358
 359 2020-01-13  Alan Modra  <amodra@gmail.com>
 360
 361         * xgate-dis.c (print_insn): Don't left shift signed value.
 362         (ripBits): Formatting, use 1u.
 363
 364 2020-01-10  Alan Modra  <amodra@gmail.com>
 365
 366         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 367         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 368
 369 2020-01-10  Alan Modra  <amodra@gmail.com>
 370
 371         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 372         and XRREG value earlier to avoid a shift with negative exponent.
 373         * m10200-dis.c (disassemble): Similarly.
 374
 375 2020-01-09  Nick Clifton  <nickc@redhat.com>
 376
 377         PR 25224
 378         * z80-dis.c (ld_ii_ii): Use correct cast.
 379
 380 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 381
 382         PR 25224
 383         * z80-dis.c (ld_ii_ii): Use character constant when checking
 384         opcode byte value.
 385
 386 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-dis.c (SEP_Fixup): New.
 389         (SEP): Define.
 390         (dis386_twobyte): Use it for sysenter/sysexit.
 391         (enum x86_64_isa): Change amd64 enumerator to value 1.
 392         (OP_J): Compare isa64 against intel64 instead of amd64.
 393         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 394         forms.
 395         * i386-tbl.h: Re-generate.
 396
 397 2020-01-08  Alan Modra  <amodra@gmail.com>
 398
 399         * z8k-dis.c: Include libiberty.h
 400         (instr_data_s): Make max_fetched unsigned.
 401         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 402         Don't exceed byte_info bounds.
 403         (output_instr): Make num_bytes unsigned.
 404         (unpack_instr): Likewise for nibl_count and loop.
 405         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 406         idx unsigned.
 407         * z8k-opc.h: Regenerate.
 408
 409 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 410
 411         * arc-tbl.h (llock): Use 'LLOCK' as class.
 412         (llockd): Likewise.
 413         (scond): Use 'SCOND' as class.
 414         (scondd): Likewise.
 415         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 416         (scondd): Likewise.
 417
 418 2020-01-06  Alan Modra  <amodra@gmail.com>
 419
 420         * m32c-ibld.c: Regenerate.
 421
 422 2020-01-06  Alan Modra  <amodra@gmail.com>
 423
 424         PR 25344
 425         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 426         Peek at next byte to prevent recursion on repeated prefix bytes.
 427         Ensure uninitialised "mybuf" is not accessed.
 428         (print_insn_z80): Don't zero n_fetch and n_used here,..
 429         (print_insn_z80_buf): ..do it here instead.
 430
 431 2020-01-04  Alan Modra  <amodra@gmail.com>
 432
 433         * m32r-ibld.c: Regenerate.
 434
 435 2020-01-04  Alan Modra  <amodra@gmail.com>
 436
 437         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 438
 439 2020-01-04  Alan Modra  <amodra@gmail.com>
 440
 441         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 442
 443 2020-01-04  Alan Modra  <amodra@gmail.com>
 444
 445         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 446
 447 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 448
 449         * aarch64-tbl.h (aarch64_opcode_table): Use
 450         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 451
 452 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 453
 454         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 455         forms of SUDOT and USDOT.
 456
 457 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 458
 459         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 460         uzip{1,2}.
 461         * opcodes/aarch64-dis-2.c: Re-generate.
 462
 463 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 464
 465         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 466         FMMLA encoding.
 467         * opcodes/aarch64-dis-2.c: Re-generate.
 468
 469 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 470
 471         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 472
 473 2020-01-01  Alan Modra  <amodra@gmail.com>
 474
 475         Update year range in copyright notice of all files.
 476
 477 For older changes see ChangeLog-2019
 478 \f
 479 Copyright (C) 2020 Free Software Foundation, Inc.
 480
 481 Copying and distribution of this file, with or without modification,
 482 are permitted in any medium without royalty provided the copyright
 483 notice and this notice are preserved.
 484
 485 Local Variables:
 486 mode: change-log
 487 left-margin: 8
 488 fill-column: 74
 489 version-control: never
 490 End: