opcodes/ChangeLog

   1 2019-10-28  Nick Clifton  <nickc@redhat.com>
   2
   3         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
   4         (bit_extract_simple): Likewise.
   5         (bit_copy): Likewise.
   6         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
   7         index_offset array are not accessed.
   8
   9 2019-10-28  Nick Clifton  <nickc@redhat.com>
  10
  11         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  12         operand.
  13
  14 2019-10-25  Nick Clifton  <nickc@redhat.com>
  15
  16         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  17         access to opcodes.op array element.
  18
  19 2019-10-23  Nick Clifton  <nickc@redhat.com>
  20
  21         * rx-dis.c (get_register_name): Fix spelling typo in error
  22         message.
  23         (get_condition_name, get_flag_name, get_double_register_name)
  24         (get_double_register_high_name, get_double_register_low_name)
  25         (get_double_control_register_name, get_double_condition_name)
  26         (get_opsize_name, get_size_name): Likewise.
  27
  28 2019-10-22  Nick Clifton  <nickc@redhat.com>
  29
  30         * rx-dis.c (get_size_name): New function.  Provides safe
  31         access to name array.
  32         (get_opsize_name): Likewise.
  33         (print_insn_rx): Use the accessor functions.
  34
  35 2019-10-16  Nick Clifton  <nickc@redhat.com>
  36
  37         * rx-dis.c (get_register_name): New function.  Provides safe
  38         access to name array.
  39         (get_condition_name, get_flag_name, get_double_register_name)
  40         (get_double_register_high_name, get_double_register_low_name)
  41         (get_double_control_register_name, get_double_condition_name):
  42         Likewise.
  43         (print_insn_rx): Use the accessor functions.
  44
  45 2019-10-09  Nick Clifton  <nickc@redhat.com>
  46
  47         PR 25041
  48         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  49         instructions.
  50
  51 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  52
  53         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  54         (cmpsd): Likewise. Move EsSeg to other operand.
  55         * opcodes/i386-tbl.h: Re-generate.
  56
  57 2019-09-23  Alan Modra  <amodra@gmail.com>
  58
  59         * m68k-dis.c: Include cpu-m68k.h
  60
  61 2019-09-23  Alan Modra  <amodra@gmail.com>
  62
  63         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  64         "elf/mips.h" earlier.
  65
  66 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  67
  68         PR gas/25012
  69         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  70         with SReg operand.
  71         * i386-tbl.h: Re-generate.
  72
  73 2019-09-18  Alan Modra  <amodra@gmail.com>
  74
  75         * arc-ext.c: Update throughout for bfd section macro changes.
  76
  77 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  78
  79         * Makefile.in: Re-generate.
  80         * configure: Re-generate.
  81
  82 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  83
  84         * riscv-opc.c (riscv_opcodes): Change subset field
  85         to insn_class field for all instructions.
  86         (riscv_insn_types): Likewise.
  87
  88 2019-09-16  Phil Blundell  <pb@pbcl.net>
  89
  90         * configure: Regenerated.
  91
  92 2019-09-10  Miod Vallat  <miod@online.fr>
  93
  94         PR 24982
  95         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  96
  97 2019-09-09  Phil Blundell  <pb@pbcl.net>
  98
  99         binutils 2.33 branch created.
 100
 101 2019-09-03  Nick Clifton  <nickc@redhat.com>
 102
 103         PR 24961
 104         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 105         greater than zero before indexing via (bufcnt -1).
 106
 107 2019-09-03  Nick Clifton  <nickc@redhat.com>
 108
 109         PR 24958
 110         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 111         (MAX_SPEC_REG_NAME_LEN): Define.
 112         (struct mmix_dis_info): Use defined constants for array lengths.
 113         (get_reg_name): New function.
 114         (get_sprec_reg_name): New function.
 115         (print_insn_mmix): Use new functions.
 116
 117 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 118
 119         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 120         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 121         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 122
 123 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 124
 125         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 126         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 127         (aarch64_sys_reg_supported_p): Update checks for the above.
 128
 129 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 130
 131         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 132         cases MVE_SQRSHRL and MVE_UQRSHLL.
 133         (print_insn_mve): Add case for specifier 'k' to check
 134         specific bit of the instruction.
 135
 136 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 137
 138         PR 24854
 139         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 140         encountering an unknown machine type.
 141         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 142         cases return -1 rather than calling abort.
 143
 144 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 145
 146         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 147         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 148         IgnoreSize.
 149         * i386-tbl.h: Re-generate.
 150
 151 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 152
 153         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 154         instructions.
 155
 156 2019-07-30  Mel Chen <mel.chen@sifive.com>
 157
 158         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 159         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 160
 161         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 162         fscsr.
 163
 164 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 165
 166         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 167         and MPY class instructions.
 168         (parse_option): Add nps400 option.
 169         (print_arc_disassembler_options): Add nps400 info.
 170
 171 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 172
 173         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 174         (bspop): Likewise.
 175         (modapp): Likewise.
 176         * arc-opc.c (RAD_CHK): Add.
 177         * arc-tbl.h: Regenerate.
 178
 179 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 180
 181         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 182         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 183
 184 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 185
 186         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 187         instructions as UNPREDICTABLE.
 188
 189 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 190
 191         * bpf-desc.c: Regenerated.
 192
 193 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-gen.c (static_assert): Define.
 196         (main): Use it.
 197         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 198         (Opcode_Modifier_Num): ... this.
 199         (Mem): Delete.
 200
 201 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-gen.c (operand_types): Move RegMem ...
 204         (opcode_modifiers): ... here.
 205         * i386-opc.h (RegMem): Move to opcode modifer enum.
 206         (union i386_operand_type): Move regmem field ...
 207         (struct i386_opcode_modifier): ... here.
 208         * i386-opc.tbl (RegMem): Define.
 209         (mov, movq): Move RegMem on segment, control, debug, and test
 210         register flavors.
 211         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 212         to non-SSE2AVX flavor.
 213         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 214         Move RegMem on register only flavors. Drop IgnoreSize from
 215         legacy encoding flavors.
 216         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 217         flavors.
 218         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 219         register only flavors.
 220         (vmovd): Move RegMem and drop IgnoreSize on register only
 221         flavor. Change opcode and operand order to store form.
 222         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 223
 224 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 225
 226         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 227         entries.
 228         * i386-opc.h (SReg2, SReg3): Replace by ...
 229         (SReg): ... this.
 230         (union i386_operand_type): Replace sreg fields.
 231         * i386-opc.tbl (mov, ): Use SReg.
 232         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 233         register flavors.
 234         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 235         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 236
 237 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 238
 239         * bpf-desc.c: Regenerate.
 240         * bpf-opc.c: Likewise.
 241         * bpf-opc.h: Likewise.
 242
 243 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 244
 245         * bpf-desc.c: Regenerate.
 246         * bpf-opc.c: Likewise.
 247
 248 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 249
 250         * arm-dis.c (print_insn_coprocessor): Rename index to
 251         index_operand.
 252
 253 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 254
 255         * riscv-opc.c (riscv_insn_types): Add r4 type.
 256
 257         * riscv-opc.c (riscv_insn_types): Add b and j type.
 258
 259         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 260         format for sb type and correct s type.
 261
 262 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 263
 264         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 265         SVE FMOV alias of FCPY.
 266
 267 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 268
 269         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 270         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 271
 272 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 273
 274         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 275         registers in an instruction prefixed by MOVPRFX.
 276
 277 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 278
 279         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 280         sve_size_13 icode to account for variant behaviour of
 281         pmull{t,b}.
 282         * aarch64-dis-2.c: Regenerate.
 283         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 284         sve_size_13 icode to account for variant behaviour of
 285         pmull{t,b}.
 286         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 287         (OP_SVE_VVV_Q_D): Add new qualifier.
 288         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 289         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 290         AES and those not.
 291
 292 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 293
 294         * opcodes/i386-gen.c (operand_type_init): Remove
 295         OPERAND_TYPE_VEC_IMM4 entry.
 296         (operand_types): Remove Vec_Imm4.
 297         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 298         (union i386_operand_type): Remove vec_imm4.
 299         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 300         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 301
 302 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 305         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 306         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 307         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 308         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 309         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 310         * i386-tbl.h: Re-generate.
 311
 312 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 315         register operands.
 316         * i386-tbl.h: Re-generate.
 317
 318 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.tbl (C): New.
 321         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 322         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 323         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 324         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 325         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 326         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 327         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 328         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 329         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 330         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 331         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 332         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 333         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 334         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 335         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 336         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 337         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 338         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 339         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 340         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 341         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 342         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 343         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 344         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 345         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 346         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 347         flavors.
 348         * i386-tbl.h: Re-generate.
 349
 350 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 353         register operands.
 354         * i386-tbl.h: Re-generate.
 355
 356 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 357
 358         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 359         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 360         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 361         * i386-tbl.h: Re-generate.
 362
 363 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 366         Disp8MemShift from register only templates.
 367         * i386-tbl.h: Re-generate.
 368
 369 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 372         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 373         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 374         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 375         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 376         EVEX_W_0F11_P_3_M_1): Delete.
 377         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 378         EVEX_W_0F11_P_3): New.
 379         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 380         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 381         MOD_EVEX_0F11_PREFIX_3 table entries.
 382         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 383         PREFIX_EVEX_0F11 table entries.
 384         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 385         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 386         EVEX_W_0F11_P_3_M_{0,1} table entries.
 387
 388 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 391         Delete.
 392
 393 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         PR binutils/24719
 396         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 397         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 398         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 399         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 400         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 401         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 402         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 403         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 404         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 405         PREFIX_EVEX_0F38C6_REG_6 entries.
 406         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 407         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 408         EVEX_W_0F38C7_R_6_P_2 entries.
 409         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 410         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 411         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 412         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 413         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 414         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 415         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 416
 417 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 420         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 421         VEX_LEN_0F2D_P_3): Delete.
 422         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 423         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 424         (prefix_table): ... here.
 425
 426 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-dis.c (Iq): Delete.
 429         (Id): New.
 430         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 431         TBM insns.
 432         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 433         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 434         (OP_E_memory): Also honor needindex when deciding whether an
 435         address size prefix needs printing.
 436         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 437
 438 2019-06-26  Jim Wilson  <jimw@sifive.com>
 439
 440         PR binutils/24739
 441         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 442         Set info->display_endian to info->endian_code.
 443
 444 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 445
 446         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 447         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 448         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 449         OPERAND_TYPE_ACC64 entries.
 450         * i386-init.h: Re-generate.
 451
 452 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 455         Delete.
 456         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 457         of dqa_mode.
 458         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 459         entries here.
 460         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 461         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 462
 463 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 464
 465         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 466         variables.
 467
 468 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 471         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 472         movnti.
 473         * i386-opc.tbl (movnti): Add IgnoreSize.
 474         * i386-tbl.h: Re-generate.
 475
 476 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 479         * i386-tbl.h: Re-generate.
 480
 481 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         * i386-dis-evex.h: Break into ...
 484         * i386-dis-evex-len.h: New file.
 485         * i386-dis-evex-mod.h: Likewise.
 486         * i386-dis-evex-prefix.h: Likewise.
 487         * i386-dis-evex-reg.h: Likewise.
 488         * i386-dis-evex-w.h: Likewise.
 489         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 490         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 491         i386-dis-evex-mod.h.
 492
 493 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 494
 495         PR binutils/24700
 496         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 497         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 498         EVEX_W_0F385B_P_2.
 499         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 500         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 501         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 502         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 503         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 504         EVEX_LEN_0F385B_P_2_W_1.
 505         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 506         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 507         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 508         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 509         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 510         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 511         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 512         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 513         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 514         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 515
 516 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 517
 518         PR binutils/24691
 519         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 520         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 521         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 522         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 523         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 524         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 525         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 526         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 527         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 528         EVEX_LEN_0F3A43_P_2_W_1.
 529         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 530         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 531         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 532         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 533         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 534         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 535         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 536         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 537         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 538         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 539         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 540         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 541
 542 2019-06-14  Nick Clifton  <nickc@redhat.com>
 543
 544         * po/fr.po; Updated French translation.
 545
 546 2019-06-13  Stafford Horne  <shorne@gmail.com>
 547
 548         * or1k-asm.c: Regenerated.
 549         * or1k-desc.c: Regenerated.
 550         * or1k-desc.h: Regenerated.
 551         * or1k-dis.c: Regenerated.
 552         * or1k-ibld.c: Regenerated.
 553         * or1k-opc.c: Regenerated.
 554         * or1k-opc.h: Regenerated.
 555         * or1k-opinst.c: Regenerated.
 556
 557 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 558
 559         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 560
 561 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         PR binutils/24633
 564         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 565         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 566         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 567         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 568         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 569         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 570         EVEX_LEN_0F3A1B_P_2_W_1.
 571         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 572         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 573         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 574         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 575         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 576         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 577         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 578         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 579
 580 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         PR binutils/24626
 583         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 584         EVEX.vvvv when disassembling VEX and EVEX instructions.
 585         (OP_VEX): Set vex.register_specifier to 0 after readding
 586         vex.register_specifier.
 587         (OP_Vex_2src_1): Likewise.
 588         (OP_Vex_2src_2): Likewise.
 589         (OP_LWP_E): Likewise.
 590         (OP_EX_Vex): Don't check vex.register_specifier.
 591         (OP_XMM_Vex): Likewise.
 592
 593 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 594             Lili Cui  <lili.cui@intel.com>
 595
 596         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 597         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 598         instructions.
 599         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 600         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 601         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 602         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 603         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 604         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 605         * i386-init.h: Regenerated.
 606         * i386-tbl.h: Likewise.
 607
 608 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 609             Lili Cui  <lili.cui@intel.com>
 610
 611         * doc/c-i386.texi: Document enqcmd.
 612         * testsuite/gas/i386/enqcmd-intel.d: New file.
 613         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 614         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 615         * testsuite/gas/i386/enqcmd.d: Likewise.
 616         * testsuite/gas/i386/enqcmd.s: Likewise.
 617         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 618         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 619         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 620         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 621         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 622         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 623         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 624         and x86-64-enqcmd.
 625
 626 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 627
 628         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 629
 630 2019-06-03  Alan Modra  <amodra@gmail.com>
 631
 632         * ppc-dis.c (prefix_opcd_indices): Correct size.
 633
 634 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         PR gas/24625
 637         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 638         Disp8ShiftVL.
 639         * i386-tbl.h: Regenerated.
 640
 641 2019-05-24  Alan Modra  <amodra@gmail.com>
 642
 643         * po/POTFILES.in: Regenerate.
 644
 645 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 646             Alan Modra  <amodra@gmail.com>
 647
 648         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 649         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 650         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 651         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 652         XTOP>): Define and add entries.
 653         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 654         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 655         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 656         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 657
 658 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 659             Alan Modra  <amodra@gmail.com>
 660
 661         * ppc-dis.c (ppc_opts): Add "future" entry.
 662         (PREFIX_OPCD_SEGS): Define.
 663         (prefix_opcd_indices): New array.
 664         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 665         (lookup_prefix): New function.
 666         (print_insn_powerpc): Handle 64-bit prefix instructions.
 667         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 668         (PMRR, POWERXX): Define.
 669         (prefix_opcodes): New instruction table.
 670         (prefix_num_opcodes): New constant.
 671
 672 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 673
 674         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 675         * configure: Regenerated.
 676         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 677         and cpu/bpf.opc.
 678         (HFILES): Add bpf-desc.h and bpf-opc.h.
 679         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 680         bpf-ibld.c and bpf-opc.c.
 681         (BPF_DEPS): Define.
 682         * Makefile.in: Regenerated.
 683         * disassemble.c (ARCH_bpf): Define.
 684         (disassembler): Add case for bfd_arch_bpf.
 685         (disassemble_init_for_target): Likewise.
 686         (enum epbf_isa_attr): Define.
 687         * disassemble.h: extern print_insn_bpf.
 688         * bpf-asm.c: Generated.
 689         * bpf-opc.h: Likewise.
 690         * bpf-opc.c: Likewise.
 691         * bpf-ibld.c: Likewise.
 692         * bpf-dis.c: Likewise.
 693         * bpf-desc.h: Likewise.
 694         * bpf-desc.c: Likewise.
 695
 696 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 697
 698         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 699         and VMSR with the new operands.
 700
 701 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 702
 703         * arm-dis.c (enum mve_instructions): New enum
 704         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 705         and cneg.
 706         (mve_opcodes): New instructions as above.
 707         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 708         csneg and csel.
 709         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 710
 711 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 712
 713         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 714         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 715         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 716         uqshl, urshrl and urshr.
 717         (is_mve_okay_in_it): Add new instructions to TRUE list.
 718         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 719         (print_insn_mve): Updated to accept new %j,
 720         %<bitfield>m and %<bitfield>n patterns.
 721
 722 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 723
 724         * mips-opc.c (mips_builtin_opcodes): Change source register
 725         constraint for DAUI.
 726
 727 2019-05-20  Nick Clifton  <nickc@redhat.com>
 728
 729         * po/fr.po: Updated French translation.
 730
 731 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 732             Michael Collison <michael.collison@arm.com>
 733
 734         * arm-dis.c (thumb32_opcodes): Add new instructions.
 735         (enum mve_instructions): Likewise.
 736         (enum mve_undefined): Add new reasons.
 737         (is_mve_encoding_conflict): Handle new instructions.
 738         (is_mve_undefined): Likewise.
 739         (is_mve_unpredictable): Likewise.
 740         (print_mve_undefined): Likewise.
 741         (print_mve_size): Likewise.
 742
 743 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 744             Michael Collison <michael.collison@arm.com>
 745
 746         * arm-dis.c (thumb32_opcodes): Add new instructions.
 747         (enum mve_instructions): Likewise.
 748         (is_mve_encoding_conflict): Handle new instructions.
 749         (is_mve_undefined): Likewise.
 750         (is_mve_unpredictable): Likewise.
 751         (print_mve_size): Likewise.
 752
 753 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 754             Michael Collison <michael.collison@arm.com>
 755
 756         * arm-dis.c (thumb32_opcodes): Add new instructions.
 757         (enum mve_instructions): Likewise.
 758         (is_mve_encoding_conflict): Likewise.
 759         (is_mve_unpredictable): Likewise.
 760         (print_mve_size): Likewise.
 761
 762 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 763             Michael Collison <michael.collison@arm.com>
 764
 765         * arm-dis.c (thumb32_opcodes): Add new instructions.
 766         (enum mve_instructions): Likewise.
 767         (is_mve_encoding_conflict): Handle new instructions.
 768         (is_mve_undefined): Likewise.
 769         (is_mve_unpredictable): Likewise.
 770         (print_mve_size): Likewise.
 771
 772 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 773             Michael Collison <michael.collison@arm.com>
 774
 775         * arm-dis.c (thumb32_opcodes): Add new instructions.
 776         (enum mve_instructions): Likewise.
 777         (is_mve_encoding_conflict): Handle new instructions.
 778         (is_mve_undefined): Likewise.
 779         (is_mve_unpredictable): Likewise.
 780         (print_mve_size): Likewise.
 781         (print_insn_mve): Likewise.
 782
 783 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 784             Michael Collison <michael.collison@arm.com>
 785
 786         * arm-dis.c (thumb32_opcodes): Add new instructions.
 787         (print_insn_thumb32): Handle new instructions.
 788
 789 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 790             Michael Collison <michael.collison@arm.com>
 791
 792         * arm-dis.c (enum mve_instructions): Add new instructions.
 793         (enum mve_undefined): Add new reasons.
 794         (is_mve_encoding_conflict): Handle new instructions.
 795         (is_mve_undefined): Likewise.
 796         (is_mve_unpredictable): Likewise.
 797         (print_mve_undefined): Likewise.
 798         (print_mve_size): Likewise.
 799         (print_mve_shift_n): Likewise.
 800         (print_insn_mve): Likewise.
 801
 802 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 803             Michael Collison <michael.collison@arm.com>
 804
 805         * arm-dis.c (enum mve_instructions): Add new instructions.
 806         (is_mve_encoding_conflict): Handle new instructions.
 807         (is_mve_unpredictable): Likewise.
 808         (print_mve_rotate): Likewise.
 809         (print_mve_size): Likewise.
 810         (print_insn_mve): Likewise.
 811
 812 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 813             Michael Collison <michael.collison@arm.com>
 814
 815         * arm-dis.c (enum mve_instructions): Add new instructions.
 816         (is_mve_encoding_conflict): Handle new instructions.
 817         (is_mve_unpredictable): Likewise.
 818         (print_mve_size): Likewise.
 819         (print_insn_mve): Likewise.
 820
 821 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 822             Michael Collison <michael.collison@arm.com>
 823
 824         * arm-dis.c (enum mve_instructions): Add new instructions.
 825         (enum mve_undefined): Add new reasons.
 826         (is_mve_encoding_conflict): Handle new instructions.
 827         (is_mve_undefined): Likewise.
 828         (is_mve_unpredictable): Likewise.
 829         (print_mve_undefined): Likewise.
 830         (print_mve_size): Likewise.
 831         (print_insn_mve): Likewise.
 832
 833 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 834             Michael Collison <michael.collison@arm.com>
 835
 836         * arm-dis.c (enum mve_instructions): Add new instructions.
 837         (is_mve_encoding_conflict): Handle new instructions.
 838         (is_mve_undefined): Likewise.
 839         (is_mve_unpredictable): Likewise.
 840         (print_mve_size): Likewise.
 841         (print_insn_mve): Likewise.
 842
 843 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 844             Michael Collison <michael.collison@arm.com>
 845
 846         * arm-dis.c (enum mve_instructions): Add new instructions.
 847         (enum mve_unpredictable): Add new reasons.
 848         (enum mve_undefined): Likewise.
 849         (is_mve_okay_in_it): Handle new isntructions.
 850         (is_mve_encoding_conflict): Likewise.
 851         (is_mve_undefined): Likewise.
 852         (is_mve_unpredictable): Likewise.
 853         (print_mve_vmov_index): Likewise.
 854         (print_simd_imm8): Likewise.
 855         (print_mve_undefined): Likewise.
 856         (print_mve_unpredictable): Likewise.
 857         (print_mve_size): Likewise.
 858         (print_insn_mve): Likewise.
 859
 860 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 861             Michael Collison <michael.collison@arm.com>
 862
 863         * arm-dis.c (enum mve_instructions): Add new instructions.
 864         (enum mve_unpredictable): Add new reasons.
 865         (enum mve_undefined): Likewise.
 866         (is_mve_encoding_conflict): Handle new instructions.
 867         (is_mve_undefined): Likewise.
 868         (is_mve_unpredictable): Likewise.
 869         (print_mve_undefined): Likewise.
 870         (print_mve_unpredictable): Likewise.
 871         (print_mve_rounding_mode): Likewise.
 872         (print_mve_vcvt_size): Likewise.
 873         (print_mve_size): Likewise.
 874         (print_insn_mve): Likewise.
 875
 876 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 877             Michael Collison <michael.collison@arm.com>
 878
 879         * arm-dis.c (enum mve_instructions): Add new instructions.
 880         (enum mve_unpredictable): Add new reasons.
 881         (enum mve_undefined): Likewise.
 882         (is_mve_undefined): Handle new instructions.
 883         (is_mve_unpredictable): Likewise.
 884         (print_mve_undefined): Likewise.
 885         (print_mve_unpredictable): Likewise.
 886         (print_mve_size): Likewise.
 887         (print_insn_mve): Likewise.
 888
 889 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 890             Michael Collison <michael.collison@arm.com>
 891
 892         * arm-dis.c (enum mve_instructions): Add new instructions.
 893         (enum mve_undefined): Add new reasons.
 894         (insns): Add new instructions.
 895         (is_mve_encoding_conflict):
 896         (print_mve_vld_str_addr): New print function.
 897         (is_mve_undefined): Handle new instructions.
 898         (is_mve_unpredictable): Likewise.
 899         (print_mve_undefined): Likewise.
 900         (print_mve_size): Likewise.
 901         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 902         (print_insn_mve):  Handle new operands.
 903
 904 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 905             Michael Collison <michael.collison@arm.com>
 906
 907         * arm-dis.c (enum mve_instructions): Add new instructions.
 908         (enum mve_unpredictable): Add new reasons.
 909         (is_mve_encoding_conflict): Handle new instructions.
 910         (is_mve_unpredictable): Likewise.
 911         (mve_opcodes): Add new instructions.
 912         (print_mve_unpredictable): Handle new reasons.
 913         (print_mve_register_blocks): New print function.
 914         (print_mve_size): Handle new instructions.
 915         (print_insn_mve): Likewise.
 916
 917 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 918             Michael Collison <michael.collison@arm.com>
 919
 920         * arm-dis.c (enum mve_instructions): Add new instructions.
 921         (enum mve_unpredictable): Add new reasons.
 922         (enum mve_undefined): Likewise.
 923         (is_mve_encoding_conflict): Handle new instructions.
 924         (is_mve_undefined): Likewise.
 925         (is_mve_unpredictable): Likewise.
 926         (coprocessor_opcodes): Move NEON VDUP from here...
 927         (neon_opcodes): ... to here.
 928         (mve_opcodes): Add new instructions.
 929         (print_mve_undefined):  Handle new reasons.
 930         (print_mve_unpredictable): Likewise.
 931         (print_mve_size): Handle new instructions.
 932         (print_insn_neon): Handle vdup.
 933         (print_insn_mve): Handle new operands.
 934
 935 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 936             Michael Collison <michael.collison@arm.com>
 937
 938         * arm-dis.c (enum mve_instructions): Add new instructions.
 939         (enum mve_unpredictable): Add new values.
 940         (mve_opcodes): Add new instructions.
 941         (vec_condnames): New array with vector conditions.
 942         (mve_predicatenames): New array with predicate suffixes.
 943         (mve_vec_sizename): New array with vector sizes.
 944         (enum vpt_pred_state): New enum with vector predication states.
 945         (struct vpt_block): New struct type for vpt blocks.
 946         (vpt_block_state): Global struct to keep track of state.
 947         (mve_extract_pred_mask): New helper function.
 948         (num_instructions_vpt_block): Likewise.
 949         (mark_outside_vpt_block): Likewise.
 950         (mark_inside_vpt_block): Likewise.
 951         (invert_next_predicate_state): Likewise.
 952         (update_next_predicate_state): Likewise.
 953         (update_vpt_block_state): Likewise.
 954         (is_vpt_instruction): Likewise.
 955         (is_mve_encoding_conflict): Add entries for new instructions.
 956         (is_mve_unpredictable): Likewise.
 957         (print_mve_unpredictable): Handle new cases.
 958         (print_instruction_predicate): Likewise.
 959         (print_mve_size): New function.
 960         (print_vec_condition): New function.
 961         (print_insn_mve): Handle vpt blocks and new print operands.
 962
 963 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 964
 965         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 966         8, 14 and 15 for Armv8.1-M Mainline.
 967
 968 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 969             Michael Collison <michael.collison@arm.com>
 970
 971         * arm-dis.c (enum mve_instructions): New enum.
 972         (enum mve_unpredictable): Likewise.
 973         (enum mve_undefined): Likewise.
 974         (struct mopcode32): New struct.
 975         (is_mve_okay_in_it): New function.
 976         (is_mve_architecture): Likewise.
 977         (arm_decode_field): Likewise.
 978         (arm_decode_field_multiple): Likewise.
 979         (is_mve_encoding_conflict): Likewise.
 980         (is_mve_undefined): Likewise.
 981         (is_mve_unpredictable): Likewise.
 982         (print_mve_undefined): Likewise.
 983         (print_mve_unpredictable): Likewise.
 984         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 985         (print_insn_mve): New function.
 986         (print_insn_thumb32): Handle MVE architecture.
 987         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 988
 989 2019-05-10  Nick Clifton  <nickc@redhat.com>
 990
 991         PR 24538
 992         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 993         end of the table prematurely.
 994
 995 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 996
 997         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 998         macros for R6.
 999
1000 2019-05-11  Alan Modra  <amodra@gmail.com>
1001
1002         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1003         when -Mraw is in effect.
1004
1005 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1006
1007         * aarch64-dis-2.c: Regenerate.
1008         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1009         (OP_SVE_BBB): New variant set.
1010         (OP_SVE_DDDD): New variant set.
1011         (OP_SVE_HHH): New variant set.
1012         (OP_SVE_HHHU): New variant set.
1013         (OP_SVE_SSS): New variant set.
1014         (OP_SVE_SSSU): New variant set.
1015         (OP_SVE_SHH): New variant set.
1016         (OP_SVE_SBBU): New variant set.
1017         (OP_SVE_DSS): New variant set.
1018         (OP_SVE_DHHU): New variant set.
1019         (OP_SVE_VMV_HSD_BHS): New variant set.
1020         (OP_SVE_VVU_HSD_BHS): New variant set.
1021         (OP_SVE_VVVU_SD_BH): New variant set.
1022         (OP_SVE_VVVU_BHSD): New variant set.
1023         (OP_SVE_VVV_QHD_DBS): New variant set.
1024         (OP_SVE_VVV_HSD_BHS): New variant set.
1025         (OP_SVE_VVV_HSD_BHS2): New variant set.
1026         (OP_SVE_VVV_BHS_HSD): New variant set.
1027         (OP_SVE_VV_BHS_HSD): New variant set.
1028         (OP_SVE_VVV_SD): New variant set.
1029         (OP_SVE_VVU_BHS_HSD): New variant set.
1030         (OP_SVE_VZVV_SD): New variant set.
1031         (OP_SVE_VZVV_BH): New variant set.
1032         (OP_SVE_VZV_SD): New variant set.
1033         (aarch64_opcode_table): Add sve2 instructions.
1034
1035 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1036
1037         * aarch64-asm-2.c: Regenerated.
1038         * aarch64-dis-2.c: Regenerated.
1039         * aarch64-opc-2.c: Regenerated.
1040         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1041         for SVE_SHLIMM_UNPRED_22.
1042         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1043         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1044         operand.
1045
1046 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1047
1048         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1049         sve_size_tsz_bhs iclass encode.
1050         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1051         sve_size_tsz_bhs iclass decode.
1052
1053 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1054
1055         * aarch64-asm-2.c: Regenerated.
1056         * aarch64-dis-2.c: Regenerated.
1057         * aarch64-opc-2.c: Regenerated.
1058         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1059         for SVE_Zm4_11_INDEX.
1060         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1061         (fields): Handle SVE_i2h field.
1062         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1063         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1064
1065 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1066
1067         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1068         sve_shift_tsz_bhsd iclass encode.
1069         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1070         sve_shift_tsz_bhsd iclass decode.
1071
1072 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1073
1074         * aarch64-asm-2.c: Regenerated.
1075         * aarch64-dis-2.c: Regenerated.
1076         * aarch64-opc-2.c: Regenerated.
1077         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1078         (aarch64_encode_variant_using_iclass): Handle
1079         sve_shift_tsz_hsd iclass encode.
1080         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1081         sve_shift_tsz_hsd iclass decode.
1082         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1083         for SVE_SHRIMM_UNPRED_22.
1084         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1085         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1086         operand.
1087
1088 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1089
1090         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1091         sve_size_013 iclass encode.
1092         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1093         sve_size_013 iclass decode.
1094
1095 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1096
1097         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1098         sve_size_bh iclass encode.
1099         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1100         sve_size_bh iclass decode.
1101
1102 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1103
1104         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1105         sve_size_sd2 iclass encode.
1106         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1107         sve_size_sd2 iclass decode.
1108         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1109         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1110
1111 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1112
1113         * aarch64-asm-2.c: Regenerated.
1114         * aarch64-dis-2.c: Regenerated.
1115         * aarch64-opc-2.c: Regenerated.
1116         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1117         for SVE_ADDR_ZX.
1118         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1119         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1120
1121 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1122
1123         * aarch64-asm-2.c: Regenerated.
1124         * aarch64-dis-2.c: Regenerated.
1125         * aarch64-opc-2.c: Regenerated.
1126         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1127         for SVE_Zm3_11_INDEX.
1128         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1129         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1130         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1131         fields.
1132         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1133
1134 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1135
1136         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1137         sve_size_hsd2 iclass encode.
1138         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1139         sve_size_hsd2 iclass decode.
1140         * aarch64-opc.c (fields): Handle SVE_size field.
1141         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1142
1143 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1144
1145         * aarch64-asm-2.c: Regenerated.
1146         * aarch64-dis-2.c: Regenerated.
1147         * aarch64-opc-2.c: Regenerated.
1148         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1149         for SVE_IMM_ROT3.
1150         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1151         (fields): Handle SVE_rot3 field.
1152         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1153         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1154
1155 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1156
1157         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1158         instructions.
1159
1160 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1161
1162         * aarch64-tbl.h
1163         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1164         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1165         aarch64_feature_sve2bitperm): New feature sets.
1166         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1167         for feature set addresses.
1168         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1169         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1170
1171 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1172             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1173
1174         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1175         argument and set ASE_EVA_R6 appropriately.
1176         (set_default_mips_dis_options): Pass ISA to above.
1177         (parse_mips_dis_option): Likewise.
1178         * mips-opc.c (EVAR6): New macro.
1179         (mips_builtin_opcodes): Add llwpe, scwpe.
1180
1181 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1182
1183         * aarch64-asm-2.c: Regenerated.
1184         * aarch64-dis-2.c: Regenerated.
1185         * aarch64-opc-2.c: Regenerated.
1186         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1187         AARCH64_OPND_TME_UIMM16.
1188         (aarch64_print_operand): Likewise.
1189         * aarch64-tbl.h (QL_IMM_NIL): New.
1190         (TME): New.
1191         (_TME_INSN): New.
1192         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1193
1194 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1195
1196         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1197
1198 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1199             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1200
1201         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1202
1203 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1204
1205         * s12z-opc.h: Add extern "C" bracketing to help
1206         users who wish to use this interface in c++ code.
1207
1208 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1209
1210         * s12z-opc.c (bm_decode): Handle bit map operations with the
1211         "reserved0" mode.
1212
1213 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1214
1215         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1216         specifier.  Add entries for VLDR and VSTR of system registers.
1217         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1218         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1219         of %J and %K format specifier.
1220
1221 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1222
1223         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1224         Add new entries for VSCCLRM instruction.
1225         (print_insn_coprocessor): Handle new %C format control code.
1226
1227 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1228
1229         * arm-dis.c (enum isa): New enum.
1230         (struct sopcode32): New structure.
1231         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1232         set isa field of all current entries to ANY.
1233         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1234         Only match an entry if its isa field allows the current mode.
1235
1236 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1237
1238         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1239         CLRM.
1240         (print_insn_thumb32): Add logic to print %n CLRM register list.
1241
1242 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1243
1244         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1245         and %Q patterns.
1246
1247 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1248
1249         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1250         (print_insn_thumb32): Edit the switch case for %Z.
1251
1252 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1253
1254         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1255
1256 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1257
1258         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1259
1260 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1261
1262         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1263
1264 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1265
1266         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1267         Arm register with r13 and r15 unpredictable.
1268         (thumb32_opcodes): New instructions for bfx and bflx.
1269
1270 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1271
1272         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1273
1274 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1275
1276         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1277
1278 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1279
1280         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1281
1282 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1283
1284         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1285
1286 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1287
1288         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1289         "optr". ("operator" is a reserved word in c++).
1290
1291 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1292
1293         * aarch64-opc.c (aarch64_print_operand): Add case for
1294         AARCH64_OPND_Rt_SP.
1295         (verify_constraints): Likewise.
1296         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1297         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1298         to accept Rt|SP as first operand.
1299         (AARCH64_OPERANDS): Add new Rt_SP.
1300         * aarch64-asm-2.c: Regenerated.
1301         * aarch64-dis-2.c: Regenerated.
1302         * aarch64-opc-2.c: Regenerated.
1303
1304 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1305
1306         * aarch64-asm-2.c: Regenerated.
1307         * aarch64-dis-2.c: Likewise.
1308         * aarch64-opc-2.c: Likewise.
1309         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1310
1311 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1312
1313         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1314
1315 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1316
1317         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1318         * i386-init.h: Regenerated.
1319
1320 2019-04-07  Alan Modra  <amodra@gmail.com>
1321
1322         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1323         op_separator to control printing of spaces, comma and parens
1324         rather than need_comma, need_paren and spaces vars.
1325
1326 2019-04-07  Alan Modra  <amodra@gmail.com>
1327
1328         PR 24421
1329         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1330         (print_insn_neon, print_insn_arm): Likewise.
1331
1332 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1333
1334         * i386-dis-evex.h (evex_table): Updated to support BF16
1335         instructions.
1336         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1337         and EVEX_W_0F3872_P_3.
1338         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1339         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1340         * i386-opc.h (enum): Add CpuAVX512_BF16.
1341         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1342         * i386-opc.tbl: Add AVX512 BF16 instructions.
1343         * i386-init.h: Regenerated.
1344         * i386-tbl.h: Likewise.
1345
1346 2019-04-05  Alan Modra  <amodra@gmail.com>
1347
1348         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1349         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1350         to favour printing of "-" branch hint when using the "y" bit.
1351         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1352
1353 2019-04-05  Alan Modra  <amodra@gmail.com>
1354
1355         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1356         opcode until first operand is output.
1357
1358 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1359
1360         PR gas/24349
1361         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1362         (valid_bo_post_v2): Add support for 'at' branch hints.
1363         (insert_bo): Only error on branch on ctr.
1364         (get_bo_hint_mask): New function.
1365         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1366         for inserting 'at' branch hints.
1367         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1368         for extracting 'at' branch hints.
1369         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1370         (BOE): Delete operand.
1371         (BOM, BOP): New operands.
1372         (RM): Update value.
1373         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1374         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1375         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1376         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1377         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1378         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1379         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1380         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1381         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1382         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1383         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1384         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1385         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1386         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1387         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1388         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1389         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1390         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1391         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1392         bttarl+>: New extended mnemonics.
1393
1394 2019-03-28  Alan Modra  <amodra@gmail.com>
1395
1396         PR 24390
1397         * ppc-opc.c (BTF): Define.
1398         (powerpc_opcodes): Use for mtfsb*.
1399         * ppc-dis.c (print_insn_powerpc): Print fields with both
1400         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1401
1402 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1403
1404         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1405         (mapping_symbol_for_insn): Implement new algorithm.
1406         (print_insn): Remove duplicate code.
1407
1408 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1409
1410         * aarch64-dis.c (print_insn_aarch64):
1411         Implement override.
1412
1413 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1414
1415         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1416         order.
1417
1418 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1419
1420         * aarch64-dis.c (last_stop_offset): New.
1421         (print_insn_aarch64): Use stop_offset.
1422
1423 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1424
1425         PR gas/24359
1426         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1427         CPU_ANY_AVX2_FLAGS.
1428         * i386-init.h: Regenerated.
1429
1430 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         PR gas/24348
1433         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1434         vmovdqu16, vmovdqu32 and vmovdqu64.
1435         * i386-tbl.h: Regenerated.
1436
1437 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1438
1439         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1440         from vstrszb, vstrszh, and vstrszf.
1441
1442 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1443
1444         * s390-opc.txt: Add instruction descriptions.
1445
1446 2019-02-08  Jim Wilson  <jimw@sifive.com>
1447
1448         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1449         <bne>: Likewise.
1450
1451 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1452
1453         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1454
1455 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1456
1457         PR binutils/23212
1458         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1459         * aarch64-opc.c (verify_elem_sd): New.
1460         (fields): Add FLD_sz entr.
1461         * aarch64-tbl.h (_SIMD_INSN): New.
1462         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1463         fmulx scalar and vector by element isns.
1464
1465 2019-02-07  Nick Clifton  <nickc@redhat.com>
1466
1467         * po/sv.po: Updated Swedish translation.
1468
1469 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1470
1471         * s390-mkopc.c (main): Accept arch13 as cpu string.
1472         * s390-opc.c: Add new instruction formats and instruction opcode
1473         masks.
1474         * s390-opc.txt: Add new arch13 instructions.
1475
1476 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1477
1478         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1479         (aarch64_opcode): Change encoding for stg, stzg
1480         st2g and st2zg.
1481         * aarch64-asm-2.c: Regenerated.
1482         * aarch64-dis-2.c: Regenerated.
1483         * aarch64-opc-2.c: Regenerated.
1484
1485 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1486
1487         * aarch64-asm-2.c: Regenerated.
1488         * aarch64-dis-2.c: Likewise.
1489         * aarch64-opc-2.c: Likewise.
1490         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1491
1492 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1493             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1494
1495         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1496         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1497         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1498         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1499         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1500         case for ldstgv_indexed.
1501         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1502         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1503         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1504         * aarch64-asm-2.c: Regenerated.
1505         * aarch64-dis-2.c: Regenerated.
1506         * aarch64-opc-2.c: Regenerated.
1507
1508 2019-01-23  Nick Clifton  <nickc@redhat.com>
1509
1510         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1511
1512 2019-01-21  Nick Clifton  <nickc@redhat.com>
1513
1514         * po/de.po: Updated German translation.
1515         * po/uk.po: Updated Ukranian translation.
1516
1517 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1518         * mips-dis.c (mips_arch_choices): Fix typo in
1519         gs464, gs464e and gs264e descriptors.
1520
1521 2019-01-19  Nick Clifton  <nickc@redhat.com>
1522
1523         * configure: Regenerate.
1524         * po/opcodes.pot: Regenerate.
1525
1526 2018-06-24  Nick Clifton  <nickc@redhat.com>
1527
1528         2.32 branch created.
1529
1530 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1531
1532         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1533         if it is null.
1534         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1535         zero.
1536
1537 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1538
1539         * configure: Regenerate.
1540
1541 2019-01-07  Alan Modra  <amodra@gmail.com>
1542
1543         * configure: Regenerate.
1544         * po/POTFILES.in: Regenerate.
1545
1546 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1547
1548         * s12z-opc.c: New file.
1549         * s12z-opc.h: New file.
1550         * s12z-dis.c: Removed all code not directly related to display
1551         of instructions.  Used the interface provided by the new files
1552         instead.
1553         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1554         * Makefile.in: Regenerate.
1555         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1556         * configure: Regenerate.
1557
1558 2019-01-01  Alan Modra  <amodra@gmail.com>
1559
1560         Update year range in copyright notice of all files.
1561
1562 For older changes see ChangeLog-2018
1563 \f
1564 Copyright (C) 2019 Free Software Foundation, Inc.
1565
1566 Copying and distribution of this file, with or without modification,
1567 are permitted in any medium without royalty provided the copyright
1568 notice and this notice are preserved.
1569
1570 Local Variables:
1571 mode: change-log
1572 left-margin: 8
1573 fill-column: 74
1574 version-control: never
1575 End: