1 2019-05-11 Alan Modra <amodra@gmail.com>
3 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
4 when -Mraw is in effect.
6 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
8 * aarch64-dis-2.c: Regenerate.
9 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
10 (OP_SVE_BBB): New variant set.
11 (OP_SVE_DDDD): New variant set.
12 (OP_SVE_HHH): New variant set.
13 (OP_SVE_HHHU): New variant set.
14 (OP_SVE_SSS): New variant set.
15 (OP_SVE_SSSU): New variant set.
16 (OP_SVE_SHH): New variant set.
17 (OP_SVE_SBBU): New variant set.
18 (OP_SVE_DSS): New variant set.
19 (OP_SVE_DHHU): New variant set.
20 (OP_SVE_VMV_HSD_BHS): New variant set.
21 (OP_SVE_VVU_HSD_BHS): New variant set.
22 (OP_SVE_VVVU_SD_BH): New variant set.
23 (OP_SVE_VVVU_BHSD): New variant set.
24 (OP_SVE_VVV_QHD_DBS): New variant set.
25 (OP_SVE_VVV_HSD_BHS): New variant set.
26 (OP_SVE_VVV_HSD_BHS2): New variant set.
27 (OP_SVE_VVV_BHS_HSD): New variant set.
28 (OP_SVE_VV_BHS_HSD): New variant set.
29 (OP_SVE_VVV_SD): New variant set.
30 (OP_SVE_VVU_BHS_HSD): New variant set.
31 (OP_SVE_VZVV_SD): New variant set.
32 (OP_SVE_VZVV_BH): New variant set.
33 (OP_SVE_VZV_SD): New variant set.
34 (aarch64_opcode_table): Add sve2 instructions.
36 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
38 * aarch64-asm-2.c: Regenerated.
39 * aarch64-dis-2.c: Regenerated.
40 * aarch64-opc-2.c: Regenerated.
41 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
42 for SVE_SHLIMM_UNPRED_22.
43 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
44 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
47 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
49 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
50 sve_size_tsz_bhs iclass encode.
51 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
52 sve_size_tsz_bhs iclass decode.
54 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
56 * aarch64-asm-2.c: Regenerated.
57 * aarch64-dis-2.c: Regenerated.
58 * aarch64-opc-2.c: Regenerated.
59 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
61 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
62 (fields): Handle SVE_i2h field.
63 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
64 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
66 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
68 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
69 sve_shift_tsz_bhsd iclass encode.
70 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
71 sve_shift_tsz_bhsd iclass decode.
73 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
75 * aarch64-asm-2.c: Regenerated.
76 * aarch64-dis-2.c: Regenerated.
77 * aarch64-opc-2.c: Regenerated.
78 * aarch64-asm.c (aarch64_ins_sve_shrimm):
79 (aarch64_encode_variant_using_iclass): Handle
80 sve_shift_tsz_hsd iclass encode.
81 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
82 sve_shift_tsz_hsd iclass decode.
83 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
84 for SVE_SHRIMM_UNPRED_22.
85 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
86 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
89 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
91 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
92 sve_size_013 iclass encode.
93 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
94 sve_size_013 iclass decode.
96 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
98 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
99 sve_size_bh iclass encode.
100 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
101 sve_size_bh iclass decode.
103 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
105 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
106 sve_size_sd2 iclass encode.
107 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
108 sve_size_sd2 iclass decode.
109 * aarch64-opc.c (fields): Handle SVE_sz2 field.
110 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
112 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
114 * aarch64-asm-2.c: Regenerated.
115 * aarch64-dis-2.c: Regenerated.
116 * aarch64-opc-2.c: Regenerated.
117 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
119 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
120 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
122 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
124 * aarch64-asm-2.c: Regenerated.
125 * aarch64-dis-2.c: Regenerated.
126 * aarch64-opc-2.c: Regenerated.
127 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
128 for SVE_Zm3_11_INDEX.
129 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
130 (fields): Handle SVE_i3l and SVE_i3h2 fields.
131 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
133 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
135 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
137 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
138 sve_size_hsd2 iclass encode.
139 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
140 sve_size_hsd2 iclass decode.
141 * aarch64-opc.c (fields): Handle SVE_size field.
142 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
144 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
146 * aarch64-asm-2.c: Regenerated.
147 * aarch64-dis-2.c: Regenerated.
148 * aarch64-opc-2.c: Regenerated.
149 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
151 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
152 (fields): Handle SVE_rot3 field.
153 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
154 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
156 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
158 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
161 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
164 (aarch64_feature_sve2, aarch64_feature_sve2aes,
165 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
166 aarch64_feature_sve2bitperm): New feature sets.
167 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
168 for feature set addresses.
169 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
170 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
172 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
173 Faraz Shahbazker <fshahbazker@wavecomp.com>
175 * mips-dis.c (mips_calculate_combination_ases): Add ISA
176 argument and set ASE_EVA_R6 appropriately.
177 (set_default_mips_dis_options): Pass ISA to above.
178 (parse_mips_dis_option): Likewise.
179 * mips-opc.c (EVAR6): New macro.
180 (mips_builtin_opcodes): Add llwpe, scwpe.
182 2019-05-01 Sudakshina Das <sudi.das@arm.com>
184 * aarch64-asm-2.c: Regenerated.
185 * aarch64-dis-2.c: Regenerated.
186 * aarch64-opc-2.c: Regenerated.
187 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
188 AARCH64_OPND_TME_UIMM16.
189 (aarch64_print_operand): Likewise.
190 * aarch64-tbl.h (QL_IMM_NIL): New.
193 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
195 2019-04-29 John Darrington <john@darrington.wattle.id.au>
197 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
199 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
200 Faraz Shahbazker <fshahbazker@wavecomp.com>
202 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
204 2019-04-24 John Darrington <john@darrington.wattle.id.au>
206 * s12z-opc.h: Add extern "C" bracketing to help
207 users who wish to use this interface in c++ code.
209 2019-04-24 John Darrington <john@darrington.wattle.id.au>
211 * s12z-opc.c (bm_decode): Handle bit map operations with the
214 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
216 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
217 specifier. Add entries for VLDR and VSTR of system registers.
218 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
219 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
220 of %J and %K format specifier.
222 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
224 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
225 Add new entries for VSCCLRM instruction.
226 (print_insn_coprocessor): Handle new %C format control code.
228 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
230 * arm-dis.c (enum isa): New enum.
231 (struct sopcode32): New structure.
232 (coprocessor_opcodes): change type of entries to struct sopcode32 and
233 set isa field of all current entries to ANY.
234 (print_insn_coprocessor): Change type of insn to struct sopcode32.
235 Only match an entry if its isa field allows the current mode.
237 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
239 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
241 (print_insn_thumb32): Add logic to print %n CLRM register list.
243 2019-04-15 Sudakshina Das <sudi.das@arm.com>
245 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
248 2019-04-15 Sudakshina Das <sudi.das@arm.com>
250 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
251 (print_insn_thumb32): Edit the switch case for %Z.
253 2019-04-15 Sudakshina Das <sudi.das@arm.com>
255 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
257 2019-04-15 Sudakshina Das <sudi.das@arm.com>
259 * arm-dis.c (thumb32_opcodes): New instruction bfl.
261 2019-04-15 Sudakshina Das <sudi.das@arm.com>
263 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
265 2019-04-15 Sudakshina Das <sudi.das@arm.com>
267 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
268 Arm register with r13 and r15 unpredictable.
269 (thumb32_opcodes): New instructions for bfx and bflx.
271 2019-04-15 Sudakshina Das <sudi.das@arm.com>
273 * arm-dis.c (thumb32_opcodes): New instructions for bf.
275 2019-04-15 Sudakshina Das <sudi.das@arm.com>
277 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
279 2019-04-15 Sudakshina Das <sudi.das@arm.com>
281 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
283 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
285 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
287 2019-04-12 John Darrington <john@darrington.wattle.id.au>
289 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
290 "optr". ("operator" is a reserved word in c++).
292 2019-04-11 Sudakshina Das <sudi.das@arm.com>
294 * aarch64-opc.c (aarch64_print_operand): Add case for
296 (verify_constraints): Likewise.
297 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
298 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
299 to accept Rt|SP as first operand.
300 (AARCH64_OPERANDS): Add new Rt_SP.
301 * aarch64-asm-2.c: Regenerated.
302 * aarch64-dis-2.c: Regenerated.
303 * aarch64-opc-2.c: Regenerated.
305 2019-04-11 Sudakshina Das <sudi.das@arm.com>
307 * aarch64-asm-2.c: Regenerated.
308 * aarch64-dis-2.c: Likewise.
309 * aarch64-opc-2.c: Likewise.
310 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
312 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
314 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
316 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
318 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
319 * i386-init.h: Regenerated.
321 2019-04-07 Alan Modra <amodra@gmail.com>
323 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
324 op_separator to control printing of spaces, comma and parens
325 rather than need_comma, need_paren and spaces vars.
327 2019-04-07 Alan Modra <amodra@gmail.com>
330 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
331 (print_insn_neon, print_insn_arm): Likewise.
333 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
335 * i386-dis-evex.h (evex_table): Updated to support BF16
337 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
338 and EVEX_W_0F3872_P_3.
339 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
340 (cpu_flags): Add bitfield for CpuAVX512_BF16.
341 * i386-opc.h (enum): Add CpuAVX512_BF16.
342 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
343 * i386-opc.tbl: Add AVX512 BF16 instructions.
344 * i386-init.h: Regenerated.
345 * i386-tbl.h: Likewise.
347 2019-04-05 Alan Modra <amodra@gmail.com>
349 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
350 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
351 to favour printing of "-" branch hint when using the "y" bit.
352 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
354 2019-04-05 Alan Modra <amodra@gmail.com>
356 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
357 opcode until first operand is output.
359 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
362 * ppc-opc.c (valid_bo_pre_v2): Add comments.
363 (valid_bo_post_v2): Add support for 'at' branch hints.
364 (insert_bo): Only error on branch on ctr.
365 (get_bo_hint_mask): New function.
366 (insert_boe): Add new 'branch_taken' formal argument. Add support
367 for inserting 'at' branch hints.
368 (extract_boe): Add new 'branch_taken' formal argument. Add support
369 for extracting 'at' branch hints.
370 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
371 (BOE): Delete operand.
372 (BOM, BOP): New operands.
374 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
375 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
376 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
377 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
378 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
379 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
380 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
381 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
382 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
383 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
384 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
385 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
386 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
387 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
388 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
389 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
390 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
391 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
392 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
393 bttarl+>: New extended mnemonics.
395 2019-03-28 Alan Modra <amodra@gmail.com>
398 * ppc-opc.c (BTF): Define.
399 (powerpc_opcodes): Use for mtfsb*.
400 * ppc-dis.c (print_insn_powerpc): Print fields with both
401 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
403 2019-03-25 Tamar Christina <tamar.christina@arm.com>
405 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
406 (mapping_symbol_for_insn): Implement new algorithm.
407 (print_insn): Remove duplicate code.
409 2019-03-25 Tamar Christina <tamar.christina@arm.com>
411 * aarch64-dis.c (print_insn_aarch64):
414 2019-03-25 Tamar Christina <tamar.christina@arm.com>
416 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
419 2019-03-25 Tamar Christina <tamar.christina@arm.com>
421 * aarch64-dis.c (last_stop_offset): New.
422 (print_insn_aarch64): Use stop_offset.
424 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
427 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
429 * i386-init.h: Regenerated.
431 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
434 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
435 vmovdqu16, vmovdqu32 and vmovdqu64.
436 * i386-tbl.h: Regenerated.
438 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
440 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
441 from vstrszb, vstrszh, and vstrszf.
443 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
445 * s390-opc.txt: Add instruction descriptions.
447 2019-02-08 Jim Wilson <jimw@sifive.com>
449 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
452 2019-02-07 Tamar Christina <tamar.christina@arm.com>
454 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
456 2019-02-07 Tamar Christina <tamar.christina@arm.com>
459 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
460 * aarch64-opc.c (verify_elem_sd): New.
461 (fields): Add FLD_sz entr.
462 * aarch64-tbl.h (_SIMD_INSN): New.
463 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
464 fmulx scalar and vector by element isns.
466 2019-02-07 Nick Clifton <nickc@redhat.com>
468 * po/sv.po: Updated Swedish translation.
470 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
472 * s390-mkopc.c (main): Accept arch13 as cpu string.
473 * s390-opc.c: Add new instruction formats and instruction opcode
475 * s390-opc.txt: Add new arch13 instructions.
477 2019-01-25 Sudakshina Das <sudi.das@arm.com>
479 * aarch64-tbl.h (QL_LDST_AT): Update macro.
480 (aarch64_opcode): Change encoding for stg, stzg
482 * aarch64-asm-2.c: Regenerated.
483 * aarch64-dis-2.c: Regenerated.
484 * aarch64-opc-2.c: Regenerated.
486 2019-01-25 Sudakshina Das <sudi.das@arm.com>
488 * aarch64-asm-2.c: Regenerated.
489 * aarch64-dis-2.c: Likewise.
490 * aarch64-opc-2.c: Likewise.
491 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
493 2019-01-25 Sudakshina Das <sudi.das@arm.com>
494 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
496 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
497 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
498 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
499 * aarch64-dis.h (ext_addr_simple_2): Likewise.
500 * aarch64-opc.c (operand_general_constraint_met_p): Remove
501 case for ldstgv_indexed.
502 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
503 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
504 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
505 * aarch64-asm-2.c: Regenerated.
506 * aarch64-dis-2.c: Regenerated.
507 * aarch64-opc-2.c: Regenerated.
509 2019-01-23 Nick Clifton <nickc@redhat.com>
511 * po/pt_BR.po: Updated Brazilian Portuguese translation.
513 2019-01-21 Nick Clifton <nickc@redhat.com>
515 * po/de.po: Updated German translation.
516 * po/uk.po: Updated Ukranian translation.
518 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
519 * mips-dis.c (mips_arch_choices): Fix typo in
520 gs464, gs464e and gs264e descriptors.
522 2019-01-19 Nick Clifton <nickc@redhat.com>
524 * configure: Regenerate.
525 * po/opcodes.pot: Regenerate.
527 2018-06-24 Nick Clifton <nickc@redhat.com>
531 2019-01-09 John Darrington <john@darrington.wattle.id.au>
533 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
535 -dis.c (opr_emit_disassembly): Do not omit an index if it is
538 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
540 * configure: Regenerate.
542 2019-01-07 Alan Modra <amodra@gmail.com>
544 * configure: Regenerate.
545 * po/POTFILES.in: Regenerate.
547 2019-01-03 John Darrington <john@darrington.wattle.id.au>
549 * s12z-opc.c: New file.
550 * s12z-opc.h: New file.
551 * s12z-dis.c: Removed all code not directly related to display
552 of instructions. Used the interface provided by the new files
554 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
555 * Makefile.in: Regenerate.
556 * configure.ac (bfd_s12z_arch): Correct the dependencies.
557 * configure: Regenerate.
559 2019-01-01 Alan Modra <amodra@gmail.com>
561 Update year range in copyright notice of all files.
563 For older changes see ChangeLog-2018
565 Copyright (C) 2019 Free Software Foundation, Inc.
567 Copying and distribution of this file, with or without modification,
568 are permitted in any medium without royalty provided the copyright
569 notice and this notice are preserved.
575 version-control: never