opcodes/ChangeLog

   1 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
   4         SVE FMOV alias of FCPY.
   5
   6 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
   7
   8         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
   9         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
  10
  11 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  12
  13         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
  14         registers in an instruction prefixed by MOVPRFX.
  15
  16 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
  17
  18         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
  19         sve_size_13 icode to account for variant behaviour of
  20         pmull{t,b}.
  21         * aarch64-dis-2.c: Regenerate.
  22         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
  23         sve_size_13 icode to account for variant behaviour of
  24         pmull{t,b}.
  25         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
  26         (OP_SVE_VVV_Q_D): Add new qualifier.
  27         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
  28         (struct aarch64_opcode): Split pmull{t,b} into those requiring
  29         AES and those not.
  30
  31 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  32
  33         * opcodes/i386-gen.c (operand_type_init): Remove
  34         OPERAND_TYPE_VEC_IMM4 entry.
  35         (operand_types): Remove Vec_Imm4.
  36         * opcodes/i386-opc.h (Vec_Imm4): Delete.
  37         (union i386_operand_type): Remove vec_imm4.
  38         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
  39         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  40
  41 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
  44         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
  45         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
  46         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
  47         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
  48         monitorx, mwaitx): Drop ImmExt from operand-less forms.
  49         * i386-tbl.h: Re-generate.
  50
  51 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
  54         register operands.
  55         * i386-tbl.h: Re-generate.
  56
  57 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-opc.tbl (C): New.
  60         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
  61         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
  62         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
  63         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
  64         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
  65         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
  66         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
  67         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
  68         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
  69         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
  70         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
  71         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
  72         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
  73         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
  74         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
  75         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
  76         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
  77         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
  78         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
  79         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
  80         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
  81         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
  82         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
  83         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
  84         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
  85         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
  86         flavors.
  87         * i386-tbl.h: Re-generate.
  88
  89 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
  92         register operands.
  93         * i386-tbl.h: Re-generate.
  94
  95 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
  98         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
  99         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 100         * i386-tbl.h: Re-generate.
 101
 102 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 105         Disp8MemShift from register only templates.
 106         * i386-tbl.h: Re-generate.
 107
 108 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 111         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 112         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 113         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 114         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 115         EVEX_W_0F11_P_3_M_1): Delete.
 116         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 117         EVEX_W_0F11_P_3): New.
 118         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 119         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 120         MOD_EVEX_0F11_PREFIX_3 table entries.
 121         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 122         PREFIX_EVEX_0F11 table entries.
 123         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 124         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 125         EVEX_W_0F11_P_3_M_{0,1} table entries.
 126
 127 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 130         Delete.
 131
 132 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 133
 134         PR binutils/24719
 135         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 136         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 137         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 138         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 139         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 140         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 141         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 142         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 143         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 144         PREFIX_EVEX_0F38C6_REG_6 entries.
 145         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 146         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 147         EVEX_W_0F38C7_R_6_P_2 entries.
 148         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 149         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 150         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 151         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 152         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 153         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 154         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 155
 156 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 159         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 160         VEX_LEN_0F2D_P_3): Delete.
 161         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 162         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 163         (prefix_table): ... here.
 164
 165 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-dis.c (Iq): Delete.
 168         (Id): New.
 169         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 170         TBM insns.
 171         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 172         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 173         (OP_E_memory): Also honor needindex when deciding whether an
 174         address size prefix needs printing.
 175         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 176
 177 2019-06-26  Jim Wilson  <jimw@sifive.com>
 178
 179         PR binutils/24739
 180         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 181         Set info->display_endian to info->endian_code.
 182
 183 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 186         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 187         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 188         OPERAND_TYPE_ACC64 entries.
 189         * i386-init.h: Re-generate.
 190
 191 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 194         Delete.
 195         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 196         of dqa_mode.
 197         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 198         entries here.
 199         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 200         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 201
 202 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 205         variables.
 206
 207 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 210         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 211         movnti.
 212         * i386-opc.tbl (movnti): Add IgnoreSize.
 213         * i386-tbl.h: Re-generate.
 214
 215 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 218         * i386-tbl.h: Re-generate.
 219
 220 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         * i386-dis-evex.h: Break into ...
 223         * i386-dis-evex-len.h: New file.
 224         * i386-dis-evex-mod.h: Likewise.
 225         * i386-dis-evex-prefix.h: Likewise.
 226         * i386-dis-evex-reg.h: Likewise.
 227         * i386-dis-evex-w.h: Likewise.
 228         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 229         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 230         i386-dis-evex-mod.h.
 231
 232 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         PR binutils/24700
 235         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 236         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 237         EVEX_W_0F385B_P_2.
 238         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 239         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 240         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 241         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 242         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 243         EVEX_LEN_0F385B_P_2_W_1.
 244         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 245         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 246         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 247         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 248         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 249         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 250         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 251         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 252         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 253         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 254
 255 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 256
 257         PR binutils/24691
 258         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 259         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 260         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 261         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 262         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 263         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 264         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 265         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 266         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 267         EVEX_LEN_0F3A43_P_2_W_1.
 268         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 269         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 270         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 271         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 272         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 273         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 274         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 275         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 276         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 277         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 278         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 279         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 280
 281 2019-06-14  Nick Clifton  <nickc@redhat.com>
 282
 283         * po/fr.po; Updated French translation.
 284
 285 2019-06-13  Stafford Horne  <shorne@gmail.com>
 286
 287         * or1k-asm.c: Regenerated.
 288         * or1k-desc.c: Regenerated.
 289         * or1k-desc.h: Regenerated.
 290         * or1k-dis.c: Regenerated.
 291         * or1k-ibld.c: Regenerated.
 292         * or1k-opc.c: Regenerated.
 293         * or1k-opc.h: Regenerated.
 294         * or1k-opinst.c: Regenerated.
 295
 296 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 297
 298         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 299
 300 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         PR binutils/24633
 303         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 304         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 305         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 306         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 307         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 308         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 309         EVEX_LEN_0F3A1B_P_2_W_1.
 310         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 311         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 312         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 313         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 314         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 315         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 316         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 317         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 318
 319 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 320
 321         PR binutils/24626
 322         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 323         EVEX.vvvv when disassembling VEX and EVEX instructions.
 324         (OP_VEX): Set vex.register_specifier to 0 after readding
 325         vex.register_specifier.
 326         (OP_Vex_2src_1): Likewise.
 327         (OP_Vex_2src_2): Likewise.
 328         (OP_LWP_E): Likewise.
 329         (OP_EX_Vex): Don't check vex.register_specifier.
 330         (OP_XMM_Vex): Likewise.
 331
 332 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 333             Lili Cui  <lili.cui@intel.com>
 334
 335         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 336         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 337         instructions.
 338         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 339         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 340         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 341         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 342         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 343         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 344         * i386-init.h: Regenerated.
 345         * i386-tbl.h: Likewise.
 346
 347 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 348             Lili Cui  <lili.cui@intel.com>
 349
 350         * doc/c-i386.texi: Document enqcmd.
 351         * testsuite/gas/i386/enqcmd-intel.d: New file.
 352         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 353         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 354         * testsuite/gas/i386/enqcmd.d: Likewise.
 355         * testsuite/gas/i386/enqcmd.s: Likewise.
 356         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 357         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 358         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 359         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 360         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 361         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 362         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 363         and x86-64-enqcmd.
 364
 365 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 366
 367         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 368
 369 2019-06-03  Alan Modra  <amodra@gmail.com>
 370
 371         * ppc-dis.c (prefix_opcd_indices): Correct size.
 372
 373 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         PR gas/24625
 376         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 377         Disp8ShiftVL.
 378         * i386-tbl.h: Regenerated.
 379
 380 2019-05-24  Alan Modra  <amodra@gmail.com>
 381
 382         * po/POTFILES.in: Regenerate.
 383
 384 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 385             Alan Modra  <amodra@gmail.com>
 386
 387         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 388         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 389         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 390         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 391         XTOP>): Define and add entries.
 392         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 393         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 394         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 395         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 396
 397 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 398             Alan Modra  <amodra@gmail.com>
 399
 400         * ppc-dis.c (ppc_opts): Add "future" entry.
 401         (PREFIX_OPCD_SEGS): Define.
 402         (prefix_opcd_indices): New array.
 403         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 404         (lookup_prefix): New function.
 405         (print_insn_powerpc): Handle 64-bit prefix instructions.
 406         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 407         (PMRR, POWERXX): Define.
 408         (prefix_opcodes): New instruction table.
 409         (prefix_num_opcodes): New constant.
 410
 411 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 412
 413         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 414         * configure: Regenerated.
 415         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 416         and cpu/bpf.opc.
 417         (HFILES): Add bpf-desc.h and bpf-opc.h.
 418         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 419         bpf-ibld.c and bpf-opc.c.
 420         (BPF_DEPS): Define.
 421         * Makefile.in: Regenerated.
 422         * disassemble.c (ARCH_bpf): Define.
 423         (disassembler): Add case for bfd_arch_bpf.
 424         (disassemble_init_for_target): Likewise.
 425         (enum epbf_isa_attr): Define.
 426         * disassemble.h: extern print_insn_bpf.
 427         * bpf-asm.c: Generated.
 428         * bpf-opc.h: Likewise.
 429         * bpf-opc.c: Likewise.
 430         * bpf-ibld.c: Likewise.
 431         * bpf-dis.c: Likewise.
 432         * bpf-desc.h: Likewise.
 433         * bpf-desc.c: Likewise.
 434
 435 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 436
 437         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 438         and VMSR with the new operands.
 439
 440 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 441
 442         * arm-dis.c (enum mve_instructions): New enum
 443         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 444         and cneg.
 445         (mve_opcodes): New instructions as above.
 446         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 447         csneg and csel.
 448         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 449
 450 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 451
 452         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 453         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 454         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 455         uqshl, urshrl and urshr.
 456         (is_mve_okay_in_it): Add new instructions to TRUE list.
 457         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 458         (print_insn_mve): Updated to accept new %j,
 459         %<bitfield>m and %<bitfield>n patterns.
 460
 461 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 462
 463         * mips-opc.c (mips_builtin_opcodes): Change source register
 464         constraint for DAUI.
 465
 466 2019-05-20  Nick Clifton  <nickc@redhat.com>
 467
 468         * po/fr.po: Updated French translation.
 469
 470 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 471             Michael Collison <michael.collison@arm.com>
 472
 473         * arm-dis.c (thumb32_opcodes): Add new instructions.
 474         (enum mve_instructions): Likewise.
 475         (enum mve_undefined): Add new reasons.
 476         (is_mve_encoding_conflict): Handle new instructions.
 477         (is_mve_undefined): Likewise.
 478         (is_mve_unpredictable): Likewise.
 479         (print_mve_undefined): Likewise.
 480         (print_mve_size): Likewise.
 481
 482 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 483             Michael Collison <michael.collison@arm.com>
 484
 485         * arm-dis.c (thumb32_opcodes): Add new instructions.
 486         (enum mve_instructions): Likewise.
 487         (is_mve_encoding_conflict): Handle new instructions.
 488         (is_mve_undefined): Likewise.
 489         (is_mve_unpredictable): Likewise.
 490         (print_mve_size): Likewise.
 491
 492 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 493             Michael Collison <michael.collison@arm.com>
 494
 495         * arm-dis.c (thumb32_opcodes): Add new instructions.
 496         (enum mve_instructions): Likewise.
 497         (is_mve_encoding_conflict): Likewise.
 498         (is_mve_unpredictable): Likewise.
 499         (print_mve_size): Likewise.
 500
 501 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 502             Michael Collison <michael.collison@arm.com>
 503
 504         * arm-dis.c (thumb32_opcodes): Add new instructions.
 505         (enum mve_instructions): Likewise.
 506         (is_mve_encoding_conflict): Handle new instructions.
 507         (is_mve_undefined): Likewise.
 508         (is_mve_unpredictable): Likewise.
 509         (print_mve_size): Likewise.
 510
 511 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 512             Michael Collison <michael.collison@arm.com>
 513
 514         * arm-dis.c (thumb32_opcodes): Add new instructions.
 515         (enum mve_instructions): Likewise.
 516         (is_mve_encoding_conflict): Handle new instructions.
 517         (is_mve_undefined): Likewise.
 518         (is_mve_unpredictable): Likewise.
 519         (print_mve_size): Likewise.
 520         (print_insn_mve): Likewise.
 521
 522 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 523             Michael Collison <michael.collison@arm.com>
 524
 525         * arm-dis.c (thumb32_opcodes): Add new instructions.
 526         (print_insn_thumb32): Handle new instructions.
 527
 528 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 529             Michael Collison <michael.collison@arm.com>
 530
 531         * arm-dis.c (enum mve_instructions): Add new instructions.
 532         (enum mve_undefined): Add new reasons.
 533         (is_mve_encoding_conflict): Handle new instructions.
 534         (is_mve_undefined): Likewise.
 535         (is_mve_unpredictable): Likewise.
 536         (print_mve_undefined): Likewise.
 537         (print_mve_size): Likewise.
 538         (print_mve_shift_n): Likewise.
 539         (print_insn_mve): Likewise.
 540
 541 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 542             Michael Collison <michael.collison@arm.com>
 543
 544         * arm-dis.c (enum mve_instructions): Add new instructions.
 545         (is_mve_encoding_conflict): Handle new instructions.
 546         (is_mve_unpredictable): Likewise.
 547         (print_mve_rotate): Likewise.
 548         (print_mve_size): Likewise.
 549         (print_insn_mve): Likewise.
 550
 551 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 552             Michael Collison <michael.collison@arm.com>
 553
 554         * arm-dis.c (enum mve_instructions): Add new instructions.
 555         (is_mve_encoding_conflict): Handle new instructions.
 556         (is_mve_unpredictable): Likewise.
 557         (print_mve_size): Likewise.
 558         (print_insn_mve): Likewise.
 559
 560 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 561             Michael Collison <michael.collison@arm.com>
 562
 563         * arm-dis.c (enum mve_instructions): Add new instructions.
 564         (enum mve_undefined): Add new reasons.
 565         (is_mve_encoding_conflict): Handle new instructions.
 566         (is_mve_undefined): Likewise.
 567         (is_mve_unpredictable): Likewise.
 568         (print_mve_undefined): Likewise.
 569         (print_mve_size): Likewise.
 570         (print_insn_mve): Likewise.
 571
 572 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 573             Michael Collison <michael.collison@arm.com>
 574
 575         * arm-dis.c (enum mve_instructions): Add new instructions.
 576         (is_mve_encoding_conflict): Handle new instructions.
 577         (is_mve_undefined): Likewise.
 578         (is_mve_unpredictable): Likewise.
 579         (print_mve_size): Likewise.
 580         (print_insn_mve): Likewise.
 581
 582 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 583             Michael Collison <michael.collison@arm.com>
 584
 585         * arm-dis.c (enum mve_instructions): Add new instructions.
 586         (enum mve_unpredictable): Add new reasons.
 587         (enum mve_undefined): Likewise.
 588         (is_mve_okay_in_it): Handle new isntructions.
 589         (is_mve_encoding_conflict): Likewise.
 590         (is_mve_undefined): Likewise.
 591         (is_mve_unpredictable): Likewise.
 592         (print_mve_vmov_index): Likewise.
 593         (print_simd_imm8): Likewise.
 594         (print_mve_undefined): Likewise.
 595         (print_mve_unpredictable): Likewise.
 596         (print_mve_size): Likewise.
 597         (print_insn_mve): Likewise.
 598
 599 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 600             Michael Collison <michael.collison@arm.com>
 601
 602         * arm-dis.c (enum mve_instructions): Add new instructions.
 603         (enum mve_unpredictable): Add new reasons.
 604         (enum mve_undefined): Likewise.
 605         (is_mve_encoding_conflict): Handle new instructions.
 606         (is_mve_undefined): Likewise.
 607         (is_mve_unpredictable): Likewise.
 608         (print_mve_undefined): Likewise.
 609         (print_mve_unpredictable): Likewise.
 610         (print_mve_rounding_mode): Likewise.
 611         (print_mve_vcvt_size): Likewise.
 612         (print_mve_size): Likewise.
 613         (print_insn_mve): Likewise.
 614
 615 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 616             Michael Collison <michael.collison@arm.com>
 617
 618         * arm-dis.c (enum mve_instructions): Add new instructions.
 619         (enum mve_unpredictable): Add new reasons.
 620         (enum mve_undefined): Likewise.
 621         (is_mve_undefined): Handle new instructions.
 622         (is_mve_unpredictable): Likewise.
 623         (print_mve_undefined): Likewise.
 624         (print_mve_unpredictable): Likewise.
 625         (print_mve_size): Likewise.
 626         (print_insn_mve): Likewise.
 627
 628 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 629             Michael Collison <michael.collison@arm.com>
 630
 631         * arm-dis.c (enum mve_instructions): Add new instructions.
 632         (enum mve_undefined): Add new reasons.
 633         (insns): Add new instructions.
 634         (is_mve_encoding_conflict):
 635         (print_mve_vld_str_addr): New print function.
 636         (is_mve_undefined): Handle new instructions.
 637         (is_mve_unpredictable): Likewise.
 638         (print_mve_undefined): Likewise.
 639         (print_mve_size): Likewise.
 640         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 641         (print_insn_mve):  Handle new operands.
 642
 643 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 644             Michael Collison <michael.collison@arm.com>
 645
 646         * arm-dis.c (enum mve_instructions): Add new instructions.
 647         (enum mve_unpredictable): Add new reasons.
 648         (is_mve_encoding_conflict): Handle new instructions.
 649         (is_mve_unpredictable): Likewise.
 650         (mve_opcodes): Add new instructions.
 651         (print_mve_unpredictable): Handle new reasons.
 652         (print_mve_register_blocks): New print function.
 653         (print_mve_size): Handle new instructions.
 654         (print_insn_mve): Likewise.
 655
 656 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 657             Michael Collison <michael.collison@arm.com>
 658
 659         * arm-dis.c (enum mve_instructions): Add new instructions.
 660         (enum mve_unpredictable): Add new reasons.
 661         (enum mve_undefined): Likewise.
 662         (is_mve_encoding_conflict): Handle new instructions.
 663         (is_mve_undefined): Likewise.
 664         (is_mve_unpredictable): Likewise.
 665         (coprocessor_opcodes): Move NEON VDUP from here...
 666         (neon_opcodes): ... to here.
 667         (mve_opcodes): Add new instructions.
 668         (print_mve_undefined):  Handle new reasons.
 669         (print_mve_unpredictable): Likewise.
 670         (print_mve_size): Handle new instructions.
 671         (print_insn_neon): Handle vdup.
 672         (print_insn_mve): Handle new operands.
 673
 674 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 675             Michael Collison <michael.collison@arm.com>
 676
 677         * arm-dis.c (enum mve_instructions): Add new instructions.
 678         (enum mve_unpredictable): Add new values.
 679         (mve_opcodes): Add new instructions.
 680         (vec_condnames): New array with vector conditions.
 681         (mve_predicatenames): New array with predicate suffixes.
 682         (mve_vec_sizename): New array with vector sizes.
 683         (enum vpt_pred_state): New enum with vector predication states.
 684         (struct vpt_block): New struct type for vpt blocks.
 685         (vpt_block_state): Global struct to keep track of state.
 686         (mve_extract_pred_mask): New helper function.
 687         (num_instructions_vpt_block): Likewise.
 688         (mark_outside_vpt_block): Likewise.
 689         (mark_inside_vpt_block): Likewise.
 690         (invert_next_predicate_state): Likewise.
 691         (update_next_predicate_state): Likewise.
 692         (update_vpt_block_state): Likewise.
 693         (is_vpt_instruction): Likewise.
 694         (is_mve_encoding_conflict): Add entries for new instructions.
 695         (is_mve_unpredictable): Likewise.
 696         (print_mve_unpredictable): Handle new cases.
 697         (print_instruction_predicate): Likewise.
 698         (print_mve_size): New function.
 699         (print_vec_condition): New function.
 700         (print_insn_mve): Handle vpt blocks and new print operands.
 701
 702 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 703
 704         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 705         8, 14 and 15 for Armv8.1-M Mainline.
 706
 707 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 708             Michael Collison <michael.collison@arm.com>
 709
 710         * arm-dis.c (enum mve_instructions): New enum.
 711         (enum mve_unpredictable): Likewise.
 712         (enum mve_undefined): Likewise.
 713         (struct mopcode32): New struct.
 714         (is_mve_okay_in_it): New function.
 715         (is_mve_architecture): Likewise.
 716         (arm_decode_field): Likewise.
 717         (arm_decode_field_multiple): Likewise.
 718         (is_mve_encoding_conflict): Likewise.
 719         (is_mve_undefined): Likewise.
 720         (is_mve_unpredictable): Likewise.
 721         (print_mve_undefined): Likewise.
 722         (print_mve_unpredictable): Likewise.
 723         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 724         (print_insn_mve): New function.
 725         (print_insn_thumb32): Handle MVE architecture.
 726         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 727
 728 2019-05-10  Nick Clifton  <nickc@redhat.com>
 729
 730         PR 24538
 731         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 732         end of the table prematurely.
 733
 734 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 735
 736         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 737         macros for R6.
 738
 739 2019-05-11  Alan Modra  <amodra@gmail.com>
 740
 741         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 742         when -Mraw is in effect.
 743
 744 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 745
 746         * aarch64-dis-2.c: Regenerate.
 747         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 748         (OP_SVE_BBB): New variant set.
 749         (OP_SVE_DDDD): New variant set.
 750         (OP_SVE_HHH): New variant set.
 751         (OP_SVE_HHHU): New variant set.
 752         (OP_SVE_SSS): New variant set.
 753         (OP_SVE_SSSU): New variant set.
 754         (OP_SVE_SHH): New variant set.
 755         (OP_SVE_SBBU): New variant set.
 756         (OP_SVE_DSS): New variant set.
 757         (OP_SVE_DHHU): New variant set.
 758         (OP_SVE_VMV_HSD_BHS): New variant set.
 759         (OP_SVE_VVU_HSD_BHS): New variant set.
 760         (OP_SVE_VVVU_SD_BH): New variant set.
 761         (OP_SVE_VVVU_BHSD): New variant set.
 762         (OP_SVE_VVV_QHD_DBS): New variant set.
 763         (OP_SVE_VVV_HSD_BHS): New variant set.
 764         (OP_SVE_VVV_HSD_BHS2): New variant set.
 765         (OP_SVE_VVV_BHS_HSD): New variant set.
 766         (OP_SVE_VV_BHS_HSD): New variant set.
 767         (OP_SVE_VVV_SD): New variant set.
 768         (OP_SVE_VVU_BHS_HSD): New variant set.
 769         (OP_SVE_VZVV_SD): New variant set.
 770         (OP_SVE_VZVV_BH): New variant set.
 771         (OP_SVE_VZV_SD): New variant set.
 772         (aarch64_opcode_table): Add sve2 instructions.
 773
 774 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 775
 776         * aarch64-asm-2.c: Regenerated.
 777         * aarch64-dis-2.c: Regenerated.
 778         * aarch64-opc-2.c: Regenerated.
 779         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 780         for SVE_SHLIMM_UNPRED_22.
 781         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 782         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 783         operand.
 784
 785 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 786
 787         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 788         sve_size_tsz_bhs iclass encode.
 789         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 790         sve_size_tsz_bhs iclass decode.
 791
 792 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 793
 794         * aarch64-asm-2.c: Regenerated.
 795         * aarch64-dis-2.c: Regenerated.
 796         * aarch64-opc-2.c: Regenerated.
 797         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 798         for SVE_Zm4_11_INDEX.
 799         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 800         (fields): Handle SVE_i2h field.
 801         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 802         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 803
 804 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 805
 806         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 807         sve_shift_tsz_bhsd iclass encode.
 808         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 809         sve_shift_tsz_bhsd iclass decode.
 810
 811 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 812
 813         * aarch64-asm-2.c: Regenerated.
 814         * aarch64-dis-2.c: Regenerated.
 815         * aarch64-opc-2.c: Regenerated.
 816         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 817         (aarch64_encode_variant_using_iclass): Handle
 818         sve_shift_tsz_hsd iclass encode.
 819         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 820         sve_shift_tsz_hsd iclass decode.
 821         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 822         for SVE_SHRIMM_UNPRED_22.
 823         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 824         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 825         operand.
 826
 827 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 828
 829         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 830         sve_size_013 iclass encode.
 831         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 832         sve_size_013 iclass decode.
 833
 834 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 835
 836         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 837         sve_size_bh iclass encode.
 838         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 839         sve_size_bh iclass decode.
 840
 841 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 842
 843         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 844         sve_size_sd2 iclass encode.
 845         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 846         sve_size_sd2 iclass decode.
 847         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 848         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 849
 850 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 851
 852         * aarch64-asm-2.c: Regenerated.
 853         * aarch64-dis-2.c: Regenerated.
 854         * aarch64-opc-2.c: Regenerated.
 855         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 856         for SVE_ADDR_ZX.
 857         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 858         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 859
 860 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 861
 862         * aarch64-asm-2.c: Regenerated.
 863         * aarch64-dis-2.c: Regenerated.
 864         * aarch64-opc-2.c: Regenerated.
 865         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 866         for SVE_Zm3_11_INDEX.
 867         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 868         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 869         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 870         fields.
 871         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 872
 873 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 874
 875         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 876         sve_size_hsd2 iclass encode.
 877         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 878         sve_size_hsd2 iclass decode.
 879         * aarch64-opc.c (fields): Handle SVE_size field.
 880         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 881
 882 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 883
 884         * aarch64-asm-2.c: Regenerated.
 885         * aarch64-dis-2.c: Regenerated.
 886         * aarch64-opc-2.c: Regenerated.
 887         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 888         for SVE_IMM_ROT3.
 889         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 890         (fields): Handle SVE_rot3 field.
 891         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 892         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 893
 894 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 895
 896         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 897         instructions.
 898
 899 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 900
 901         * aarch64-tbl.h
 902         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 903         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 904         aarch64_feature_sve2bitperm): New feature sets.
 905         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 906         for feature set addresses.
 907         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 908         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 909
 910 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 911             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 912
 913         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 914         argument and set ASE_EVA_R6 appropriately.
 915         (set_default_mips_dis_options): Pass ISA to above.
 916         (parse_mips_dis_option): Likewise.
 917         * mips-opc.c (EVAR6): New macro.
 918         (mips_builtin_opcodes): Add llwpe, scwpe.
 919
 920 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 921
 922         * aarch64-asm-2.c: Regenerated.
 923         * aarch64-dis-2.c: Regenerated.
 924         * aarch64-opc-2.c: Regenerated.
 925         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 926         AARCH64_OPND_TME_UIMM16.
 927         (aarch64_print_operand): Likewise.
 928         * aarch64-tbl.h (QL_IMM_NIL): New.
 929         (TME): New.
 930         (_TME_INSN): New.
 931         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 932
 933 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 934
 935         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 936
 937 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 938             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 939
 940         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 941
 942 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 943
 944         * s12z-opc.h: Add extern "C" bracketing to help
 945         users who wish to use this interface in c++ code.
 946
 947 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 948
 949         * s12z-opc.c (bm_decode): Handle bit map operations with the
 950         "reserved0" mode.
 951
 952 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 953
 954         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 955         specifier.  Add entries for VLDR and VSTR of system registers.
 956         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 957         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 958         of %J and %K format specifier.
 959
 960 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 961
 962         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 963         Add new entries for VSCCLRM instruction.
 964         (print_insn_coprocessor): Handle new %C format control code.
 965
 966 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 967
 968         * arm-dis.c (enum isa): New enum.
 969         (struct sopcode32): New structure.
 970         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 971         set isa field of all current entries to ANY.
 972         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 973         Only match an entry if its isa field allows the current mode.
 974
 975 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 976
 977         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 978         CLRM.
 979         (print_insn_thumb32): Add logic to print %n CLRM register list.
 980
 981 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 982
 983         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 984         and %Q patterns.
 985
 986 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 987
 988         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 989         (print_insn_thumb32): Edit the switch case for %Z.
 990
 991 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 992
 993         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 994
 995 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 996
 997         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 998
 999 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1000
1001         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1002
1003 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1004
1005         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1006         Arm register with r13 and r15 unpredictable.
1007         (thumb32_opcodes): New instructions for bfx and bflx.
1008
1009 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1010
1011         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1012
1013 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1014
1015         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1016
1017 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1018
1019         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1020
1021 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1022
1023         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1024
1025 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1026
1027         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1028         "optr". ("operator" is a reserved word in c++).
1029
1030 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1031
1032         * aarch64-opc.c (aarch64_print_operand): Add case for
1033         AARCH64_OPND_Rt_SP.
1034         (verify_constraints): Likewise.
1035         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1036         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1037         to accept Rt|SP as first operand.
1038         (AARCH64_OPERANDS): Add new Rt_SP.
1039         * aarch64-asm-2.c: Regenerated.
1040         * aarch64-dis-2.c: Regenerated.
1041         * aarch64-opc-2.c: Regenerated.
1042
1043 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1044
1045         * aarch64-asm-2.c: Regenerated.
1046         * aarch64-dis-2.c: Likewise.
1047         * aarch64-opc-2.c: Likewise.
1048         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1049
1050 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1051
1052         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1053
1054 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1055
1056         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1057         * i386-init.h: Regenerated.
1058
1059 2019-04-07  Alan Modra  <amodra@gmail.com>
1060
1061         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1062         op_separator to control printing of spaces, comma and parens
1063         rather than need_comma, need_paren and spaces vars.
1064
1065 2019-04-07  Alan Modra  <amodra@gmail.com>
1066
1067         PR 24421
1068         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1069         (print_insn_neon, print_insn_arm): Likewise.
1070
1071 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1072
1073         * i386-dis-evex.h (evex_table): Updated to support BF16
1074         instructions.
1075         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1076         and EVEX_W_0F3872_P_3.
1077         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1078         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1079         * i386-opc.h (enum): Add CpuAVX512_BF16.
1080         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1081         * i386-opc.tbl: Add AVX512 BF16 instructions.
1082         * i386-init.h: Regenerated.
1083         * i386-tbl.h: Likewise.
1084
1085 2019-04-05  Alan Modra  <amodra@gmail.com>
1086
1087         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1088         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1089         to favour printing of "-" branch hint when using the "y" bit.
1090         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1091
1092 2019-04-05  Alan Modra  <amodra@gmail.com>
1093
1094         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1095         opcode until first operand is output.
1096
1097 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1098
1099         PR gas/24349
1100         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1101         (valid_bo_post_v2): Add support for 'at' branch hints.
1102         (insert_bo): Only error on branch on ctr.
1103         (get_bo_hint_mask): New function.
1104         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1105         for inserting 'at' branch hints.
1106         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1107         for extracting 'at' branch hints.
1108         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1109         (BOE): Delete operand.
1110         (BOM, BOP): New operands.
1111         (RM): Update value.
1112         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1113         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1114         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1115         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1116         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1117         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1118         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1119         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1120         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1121         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1122         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1123         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1124         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1125         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1126         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1127         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1128         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1129         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1130         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1131         bttarl+>: New extended mnemonics.
1132
1133 2019-03-28  Alan Modra  <amodra@gmail.com>
1134
1135         PR 24390
1136         * ppc-opc.c (BTF): Define.
1137         (powerpc_opcodes): Use for mtfsb*.
1138         * ppc-dis.c (print_insn_powerpc): Print fields with both
1139         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1140
1141 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1142
1143         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1144         (mapping_symbol_for_insn): Implement new algorithm.
1145         (print_insn): Remove duplicate code.
1146
1147 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1148
1149         * aarch64-dis.c (print_insn_aarch64):
1150         Implement override.
1151
1152 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1153
1154         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1155         order.
1156
1157 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1158
1159         * aarch64-dis.c (last_stop_offset): New.
1160         (print_insn_aarch64): Use stop_offset.
1161
1162 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1163
1164         PR gas/24359
1165         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1166         CPU_ANY_AVX2_FLAGS.
1167         * i386-init.h: Regenerated.
1168
1169 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1170
1171         PR gas/24348
1172         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1173         vmovdqu16, vmovdqu32 and vmovdqu64.
1174         * i386-tbl.h: Regenerated.
1175
1176 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1177
1178         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1179         from vstrszb, vstrszh, and vstrszf.
1180
1181 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1182
1183         * s390-opc.txt: Add instruction descriptions.
1184
1185 2019-02-08  Jim Wilson  <jimw@sifive.com>
1186
1187         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1188         <bne>: Likewise.
1189
1190 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1191
1192         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1193
1194 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1195
1196         PR binutils/23212
1197         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1198         * aarch64-opc.c (verify_elem_sd): New.
1199         (fields): Add FLD_sz entr.
1200         * aarch64-tbl.h (_SIMD_INSN): New.
1201         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1202         fmulx scalar and vector by element isns.
1203
1204 2019-02-07  Nick Clifton  <nickc@redhat.com>
1205
1206         * po/sv.po: Updated Swedish translation.
1207
1208 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1209
1210         * s390-mkopc.c (main): Accept arch13 as cpu string.
1211         * s390-opc.c: Add new instruction formats and instruction opcode
1212         masks.
1213         * s390-opc.txt: Add new arch13 instructions.
1214
1215 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1216
1217         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1218         (aarch64_opcode): Change encoding for stg, stzg
1219         st2g and st2zg.
1220         * aarch64-asm-2.c: Regenerated.
1221         * aarch64-dis-2.c: Regenerated.
1222         * aarch64-opc-2.c: Regenerated.
1223
1224 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1225
1226         * aarch64-asm-2.c: Regenerated.
1227         * aarch64-dis-2.c: Likewise.
1228         * aarch64-opc-2.c: Likewise.
1229         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1230
1231 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1232             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1233
1234         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1235         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1236         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1237         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1238         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1239         case for ldstgv_indexed.
1240         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1241         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1242         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1243         * aarch64-asm-2.c: Regenerated.
1244         * aarch64-dis-2.c: Regenerated.
1245         * aarch64-opc-2.c: Regenerated.
1246
1247 2019-01-23  Nick Clifton  <nickc@redhat.com>
1248
1249         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1250
1251 2019-01-21  Nick Clifton  <nickc@redhat.com>
1252
1253         * po/de.po: Updated German translation.
1254         * po/uk.po: Updated Ukranian translation.
1255
1256 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1257         * mips-dis.c (mips_arch_choices): Fix typo in
1258         gs464, gs464e and gs264e descriptors.
1259
1260 2019-01-19  Nick Clifton  <nickc@redhat.com>
1261
1262         * configure: Regenerate.
1263         * po/opcodes.pot: Regenerate.
1264
1265 2018-06-24  Nick Clifton  <nickc@redhat.com>
1266
1267         2.32 branch created.
1268
1269 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1270
1271         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1272         if it is null.
1273         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1274         zero.
1275
1276 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1277
1278         * configure: Regenerate.
1279
1280 2019-01-07  Alan Modra  <amodra@gmail.com>
1281
1282         * configure: Regenerate.
1283         * po/POTFILES.in: Regenerate.
1284
1285 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1286
1287         * s12z-opc.c: New file.
1288         * s12z-opc.h: New file.
1289         * s12z-dis.c: Removed all code not directly related to display
1290         of instructions.  Used the interface provided by the new files
1291         instead.
1292         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1293         * Makefile.in: Regenerate.
1294         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1295         * configure: Regenerate.
1296
1297 2019-01-01  Alan Modra  <amodra@gmail.com>
1298
1299         Update year range in copyright notice of all files.
1300
1301 For older changes see ChangeLog-2018
1302 \f
1303 Copyright (C) 2019 Free Software Foundation, Inc.
1304
1305 Copying and distribution of this file, with or without modification,
1306 are permitted in any medium without royalty provided the copyright
1307 notice and this notice are preserved.
1308
1309 Local Variables:
1310 mode: change-log
1311 left-margin: 8
1312 fill-column: 74
1313 version-control: never
1314 End: