1 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
3 * disassemble.c: Enable disassembler_needs_relocs for PRU.
5 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
6 Renlin Li <renlin.li@arm.com>
8 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
9 (get_sym_code_type): Here.
11 2017-12-03 Alan Modra <amodra@gmail.com>
13 * ppc-opc.c (extract_li20): Rewrite.
15 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
17 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
18 (operand_value_powerpc): Update return and argument type.
19 <value, top>: Update type.
20 (skip_optional_operands): Update argument type.
21 (lookup_powerpc): Likewise.
22 (lookup_vle): Likewise.
23 <table_opcd, table_mask, insn2>: Update type.
24 (lookup_spe2): Update argument type.
25 <table_opcd, table_mask, insn2>: Update type.
26 (print_insn_powerpc) <insn, value>: Update type.
27 Use PPC_INT_FMT for printing instructions and operands.
28 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
29 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
30 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
31 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
32 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
33 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
34 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
35 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
36 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
37 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
38 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
39 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
40 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
41 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
42 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
43 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
44 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
45 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
46 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
47 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
48 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
49 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
50 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
51 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
52 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
53 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
54 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
55 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
56 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
57 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
58 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
59 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
60 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
61 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
62 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
63 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
64 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
66 2017-11-29 Jan Beulich <jbeulich@suse.com>
68 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
70 (output_cpu_flags): Update active_cpu_flags.
71 (process_i386_opcode_modifier): Update active_isstring.
72 (output_operand_type): Rename "macro" parameter to "stage",
74 (process_i386_operand_type): Likewise. Track presence of
75 BaseIndex and emit DispN accordingly.
76 (output_i386_opcode, process_i386_registers,
77 process_i386_initializers): Adjust calls to
78 process_i386_operand_type() for its changed parameter type.
79 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
80 all insns operands having BaseIndex set.
81 * i386-tbl.h: Re-generate.
83 2017-11-29 Jan Beulich <jbeulich@suse.com>
85 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
87 (operand_types): Remove Vec_Disp8 entry.
88 * i386-opc.h (Vec_Disp8): Delete.
89 (union i386_operand_type): Remove vec_disp8.
90 (i386-opc.tbl): Remove Vec_Disp8.
91 * i386-init.h, i386-tbl.h: Re-generate.
93 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
95 * po/Make-in (datadir): Define as @datadir@.
96 (localedir): Define as @localedir@.
97 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
99 2017-11-27 Nick Clifton <nickc@redhat.com>
101 * po/zh_CN.po: Updated simplified Chinese translation.
103 2017-11-24 Jan Beulich <jbeulich@suse.com>
105 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
108 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
110 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
111 * i386-tbl.h: Regenerate.
113 2017-11-23 Jan Beulich <jbeulich@suse.com>
115 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
116 the 16-bit addressing case.
118 2017-11-23 Jan Beulich <jbeulich@suse.com>
120 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
121 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
122 * i386-opc.tbl (ud1, ud2b): Add operands.
124 * i386-tbl.h: Re-generate.
126 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
128 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
129 * i386-tbl.h: Regenerate.
131 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
133 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
134 * i386-tbl.h: Regenerate.
136 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
138 *arc-opc (insert_rhv2): Check h-regs range.
140 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
142 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
143 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
145 2017-11-16 Tamar Christina <tamar.christina@arm.com>
147 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
148 and AARCH64_FEATURE_F16.
150 2017-11-16 Tamar Christina <tamar.christina@arm.com>
152 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
153 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
154 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
155 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
156 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
157 (ldapur, ldapursw, stlur): New.
158 * aarch64-dis-2.c: Regenerate.
160 2017-11-16 Jan Beulich <jbeulich@suse.com>
162 (get_valid_dis386): Never flag bad opcode when
163 vex.register_specifier is beyond 7. Always store all four
164 bits of it. Move 16-/32-bit override in EVEX handling after
165 all to be overridden bits have been set.
166 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
167 Use rex to determine GPR register set.
168 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
169 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
171 2017-11-15 Jan Beulich <jbeulich@suse.com>
173 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
174 determine GPR register set.
176 2017-11-15 Jan Beulich <jbeulich@suse.com>
178 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
179 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
180 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
182 (OP_REG_VexI4): Drop low 4 bits check.
184 2017-11-15 Jan Beulich <jbeulich@suse.com>
186 * i386-reg.tbl (axl): Remove Acc and Byte.
187 * i386-tbl.h: Re-generate.
189 2017-11-14 Jan Beulich <jbeulich@suse.com>
191 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
192 (vex_len_table): Use VPCOM.
194 2017-11-14 Jan Beulich <jbeulich@suse.com>
196 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
197 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
198 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
200 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
201 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
202 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
203 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
205 * i386-tbl.h: Re-generate.
207 2017-11-14 Jan Beulich <jbeulich@suse.com>
209 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
210 smov, ssca, stos, ssto, xlat): Drop Disp*.
211 * i386-tbl.h: Re-generate.
213 2017-11-13 Jan Beulich <jbeulich@suse.com>
215 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
216 xsaveopt64): Add No_qSuf.
217 * i386-tbl.h: Re-generate.
219 2017-11-09 Tamar Christina <tamar.christina@arm.com>
221 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
222 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
223 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
224 sder32_el2, vncr_el2.
225 (aarch64_sys_reg_supported_p): Likewise.
226 (aarch64_pstatefields): Add dit register.
227 (aarch64_pstatefield_supported_p): Likewise.
228 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
229 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
230 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
231 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
232 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
233 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
234 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
236 2017-11-09 Tamar Christina <tamar.christina@arm.com>
238 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
239 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
240 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
241 (QL_STLW, QL_STLX): New.
243 2017-11-09 Tamar Christina <tamar.christina@arm.com>
245 * aarch64-asm.h (ins_addr_offset): New.
246 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
247 (aarch64_ins_addr_offset): New.
248 * aarch64-asm-2.c: Regenerate.
249 * aarch64-dis.h (ext_addr_offset): New.
250 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
251 (aarch64_ext_addr_offset): New.
252 * aarch64-dis-2.c: Regenerate.
253 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
254 FLD_imm4_2 and FLD_SM3_imm2.
255 * aarch64-opc.c (fields): Add FLD_imm6_2,
256 FLD_imm4_2 and FLD_SM3_imm2.
257 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
258 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
259 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
260 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
262 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
264 2017-11-09 Tamar Christina <tamar.christina@arm.com>
267 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
268 (aarch64_feature_sm4, aarch64_feature_sha3): New.
269 (aarch64_feature_fp_16_v8_2): New.
270 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
271 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
272 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
274 2017-11-08 Tamar Christina <tamar.christina@arm.com>
276 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
277 (aarch64_feature_sha2, aarch64_feature_aes): New.
279 (AES_INSN, SHA2_INSN): New.
280 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
281 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
282 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
285 2017-11-08 Jiong Wang <jiong.wang@arm.com>
286 Tamar Christina <tamar.christina@arm.com>
288 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
289 FP16 instructions, including vfmal.f16 and vfmsl.f16.
291 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
293 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
295 2017-11-07 Alan Modra <amodra@gmail.com>
297 * opintl.h: Formatting, comment fixes.
298 (gettext, ngettext): Redefine when ENABLE_NLS.
299 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
300 (_): Define using gettext.
301 (textdomain, bindtextdomain): Use safer "do nothing".
303 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
305 * arc-dis.c (print_hex): New variable.
306 (parse_option): Check for hex option.
307 (print_insn_arc): Use hexadecimal representation for short
308 immediate values when requested.
309 (print_arc_disassembler_options): Add hex option to the list.
311 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
313 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
314 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
315 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
316 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
317 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
318 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
319 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
320 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
321 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
322 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
323 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
324 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
325 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
326 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
327 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
328 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
329 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
330 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
331 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
333 (prealloc, prefetch*): Place them before ld instruction.
334 * arc-opc.c (skip_this_opcode): Add ARITH class.
336 2017-10-25 Alan Modra <amodra@gmail.com>
339 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
340 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
341 (imm4flag, size_changed): Likewise.
342 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
343 (words, allWords, processing_argument_number): Likewise.
344 (cst4flag, size_changed): Likewise.
345 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
346 (crx_cst4_maps): Rename from cst4_maps.
347 (crx_no_op_insn): Rename from no_op_insn.
349 2017-10-24 Andrew Waterman <andrew@sifive.com>
351 * riscv-opc.c (match_c_addi16sp) : New function.
352 (match_c_addi4spn): New function.
353 (match_c_lui): Don't allow 0-immediate encodings.
354 (riscv_opcodes) <addi>: Use the above functions.
356 <c.addi4spn>: Likewise.
357 <c.addi16sp>: Likewise.
359 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
361 * i386-init.h: Regenerate
362 * i386-tbl.h: Likewise
364 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
366 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
367 (enum): Add EVEX_W_0F3854_P_2.
368 * i386-dis-evex.h (evex_table): Updated.
369 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
370 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
371 (cpu_flags): Add CpuAVX512_BITALG.
372 * i386-opc.h (enum): Add CpuAVX512_BITALG.
373 (i386_cpu_flags): Add cpuavx512_bitalg..
374 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
375 * i386-init.h: Regenerate.
376 * i386-tbl.h: Likewise.
378 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
380 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
381 * i386-dis-evex.h (evex_table): Updated.
382 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
383 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
384 (cpu_flags): Add CpuAVX512_VNNI.
385 * i386-opc.h (enum): Add CpuAVX512_VNNI.
386 (i386_cpu_flags): Add cpuavx512_vnni.
387 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
388 * i386-init.h: Regenerate.
389 * i386-tbl.h: Likewise.
391 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
393 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
394 (enum): Remove VEX_LEN_0F3A44_P_2.
395 (vex_len_table): Ditto.
396 (enum): Remove VEX_W_0F3A44_P_2.
397 (vew_w_table): Ditto.
398 (prefix_table): Adjust instructions (see prefixes above).
399 * i386-dis-evex.h (evex_table):
400 Add new instructions (see prefixes above).
401 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
402 (bitfield_cpu_flags): Ditto.
403 * i386-opc.h (enum): Ditto.
404 (i386_cpu_flags): Ditto.
405 (CpuUnused): Comment out to avoid zero-width field problem.
406 * i386-opc.tbl (vpclmulqdq): New instruction.
407 * i386-init.h: Regenerate.
410 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
412 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
413 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
414 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
415 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
416 (vex_len_table): Ditto.
417 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
418 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
419 (vew_w_table): Ditto.
420 (prefix_table): Adjust instructions (see prefixes above).
421 * i386-dis-evex.h (evex_table):
422 Add new instructions (see prefixes above).
423 * i386-gen.c (cpu_flag_init): Add VAES.
424 (bitfield_cpu_flags): Ditto.
425 * i386-opc.h (enum): Ditto.
426 (i386_cpu_flags): Ditto.
427 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
428 * i386-init.h: Regenerate.
431 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
433 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
434 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
435 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
436 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
437 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
438 (prefix_table): Updated (see prefixes above).
439 (three_byte_table): Likewise.
440 (vex_w_table): Likewise.
441 * i386-dis-evex.h: Likewise.
442 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
443 (cpu_flags): Add CpuGFNI.
444 * i386-opc.h (enum): Add CpuGFNI.
445 (i386_cpu_flags): Add cpugfni.
446 * i386-opc.tbl: Add Intel GFNI instructions.
447 * i386-init.h: Regenerate.
448 * i386-tbl.h: Likewise.
450 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
452 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
453 Define EXbScalar and EXwScalar for OP_EX.
454 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
455 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
456 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
457 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
458 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
459 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
460 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
461 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
462 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
463 (OP_E_memory): Likewise.
464 * i386-dis-evex.h: Updated.
465 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
466 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
467 (cpu_flags): Add CpuAVX512_VBMI2.
468 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
469 (i386_cpu_flags): Add cpuavx512_vbmi2.
470 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
471 * i386-init.h: Regenerate.
472 * i386-tbl.h: Likewise.
474 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
476 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
478 2017-10-12 James Bowman <james.bowman@ftdichip.com>
480 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
481 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
482 K15. Add jmpix pattern.
484 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
486 * s390-opc.txt (prno, tpei, irbm): New instructions added.
488 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
490 * s390-opc.c (INSTR_SI_RD): New macro.
491 (INSTR_S_RD): Adjust example instruction.
492 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
495 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
497 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
498 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
499 VLE multimple load/store instructions. Old e_ldm* variants are
501 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
503 2017-09-27 Nick Clifton <nickc@redhat.com>
506 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
507 names for the fmv.x.s and fmv.s.x instructions respectively.
509 2017-09-26 do <do@nerilex.org>
512 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
513 be used on CPUs that have emacs support.
515 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
517 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
519 2017-09-09 Kamil Rytarowski <n54@gmx.com>
521 * nds32-asm.c: Rename __BIT() to N32_BIT().
522 * nds32-asm.h: Likewise.
523 * nds32-dis.c: Likewise.
525 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
527 * i386-dis.c (last_active_prefix): Removed.
528 (ckprefix): Don't set last_active_prefix.
529 (NOTRACK_Fixup): Don't check last_active_prefix.
531 2017-08-31 Nick Clifton <nickc@redhat.com>
533 * po/fr.po: Updated French translation.
535 2017-08-31 James Bowman <james.bowman@ftdichip.com>
537 * ft32-dis.c (print_insn_ft32): Correct display of non-address
540 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
541 Edmar Wienskoski <edmar.wienskoski@nxp.com>
543 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
544 PPC_OPCODE_EFS2 flag to "e200z4" entry.
545 New entries efs2 and spe2.
546 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
547 (SPE2_OPCD_SEGS): New macro.
548 (spe2_opcd_indices): New.
549 (disassemble_init_powerpc): Handle SPE2 opcodes.
550 (lookup_spe2): New function.
551 (print_insn_powerpc): call lookup_spe2.
552 * ppc-opc.c (insert_evuimm1_ex0): New function.
553 (extract_evuimm1_ex0): Likewise.
554 (insert_evuimm_lt8): Likewise.
555 (extract_evuimm_lt8): Likewise.
556 (insert_off_spe2): Likewise.
557 (extract_off_spe2): Likewise.
558 (insert_Ddd): Likewise.
559 (extract_Ddd): Likewise.
561 (EVUIMM_LT8): Likewise.
562 (EVUIMM_LT16): Adjust.
564 (EVUIMM_1): Likewise.
565 (EVUIMM_1_EX0): Likewise.
568 (VX_OFF_SPE2): Likewise.
571 (VX_MASK_DDD): New mask.
573 (VX_RA_CONST): New macro.
574 (VX_RA_CONST_MASK): Likewise.
575 (VX_RB_CONST): Likewise.
576 (VX_RB_CONST_MASK): Likewise.
577 (VX_OFF_SPE2_MASK): Likewise.
578 (VX_SPE_CRFD): Likewise.
579 (VX_SPE_CRFD_MASK VX): Likewise.
580 (VX_SPE2_CLR): Likewise.
581 (VX_SPE2_CLR_MASK): Likewise.
582 (VX_SPE2_SPLATB): Likewise.
583 (VX_SPE2_SPLATB_MASK): Likewise.
584 (VX_SPE2_OCTET): Likewise.
585 (VX_SPE2_OCTET_MASK): Likewise.
586 (VX_SPE2_DDHH): Likewise.
587 (VX_SPE2_DDHH_MASK): Likewise.
588 (VX_SPE2_HH): Likewise.
589 (VX_SPE2_HH_MASK): Likewise.
590 (VX_SPE2_EVMAR): Likewise.
591 (VX_SPE2_EVMAR_MASK): Likewise.
594 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
595 (powerpc_macros): Map old SPE instructions have new names
596 with the same opcodes. Add SPE2 instructions which just are
598 (spe2_opcodes): Add SPE2 opcodes.
600 2017-08-23 Alan Modra <amodra@gmail.com>
602 * ppc-opc.c: Formatting and comment fixes. Move insert and
603 extract functions earlier, deleting forward declarations.
604 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
607 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
609 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
611 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
612 Edmar Wienskoski <edmar.wienskoski@nxp.com>
614 * ppc-opc.c (insert_evuimm2_ex0): New function.
615 (extract_evuimm2_ex0): Likewise.
616 (insert_evuimm4_ex0): Likewise.
617 (extract_evuimm4_ex0): Likewise.
618 (insert_evuimm8_ex0): Likewise.
619 (extract_evuimm8_ex0): Likewise.
620 (insert_evuimm_lt16): Likewise.
621 (extract_evuimm_lt16): Likewise.
622 (insert_rD_rS_even): Likewise.
623 (extract_rD_rS_even): Likewise.
624 (insert_off_lsp): Likewise.
625 (extract_off_lsp): Likewise.
626 (RD_EVEN): New operand.
629 (EVUIMM_LT16): New operand.
631 (EVUIMM_2_EX0): New operand.
633 (EVUIMM_4_EX0): New operand.
635 (EVUIMM_8_EX0): New operand.
637 (VX_OFF): New operand.
639 (VX_LSP_MASK): Likewise.
640 (VX_LSP_OFF_MASK): Likewise.
641 (PPC_OPCODE_LSP): Likewise.
642 (vle_opcodes): Add LSP opcodes.
643 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
645 2017-08-09 Jiong Wang <jiong.wang@arm.com>
647 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
648 register operands in CRC instructions.
649 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
652 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
654 * disassemble.c (disassembler): Mark big and mach with
657 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
659 * disassemble.c (disassembler): Remove arch/mach/endian
662 2017-07-25 Nick Clifton <nickc@redhat.com>
665 * arc-opc.c (insert_rhv2): Use lower case first letter in error
667 (insert_r0): Likewise.
668 (insert_r1): Likewise.
669 (insert_r2): Likewise.
670 (insert_r3): Likewise.
671 (insert_sp): Likewise.
672 (insert_gp): Likewise.
673 (insert_pcl): Likewise.
674 (insert_blink): Likewise.
675 (insert_ilink1): Likewise.
676 (insert_ilink2): Likewise.
677 (insert_ras): Likewise.
678 (insert_rbs): Likewise.
679 (insert_rcs): Likewise.
680 (insert_simm3s): Likewise.
681 (insert_rrange): Likewise.
682 (insert_r13el): Likewise.
683 (insert_fpel): Likewise.
684 (insert_blinkel): Likewise.
685 (insert_pclel): Likewise.
686 (insert_nps_bitop_size_2b): Likewise.
687 (insert_nps_imm_offset): Likewise.
688 (insert_nps_imm_entry): Likewise.
689 (insert_nps_size_16bit): Likewise.
690 (insert_nps_##NAME##_pos): Likewise.
691 (insert_nps_##NAME): Likewise.
692 (insert_nps_bitop_ins_ext): Likewise.
693 (insert_nps_##NAME): Likewise.
694 (insert_nps_min_hofs): Likewise.
695 (insert_nps_##NAME): Likewise.
696 (insert_nps_rbdouble_64): Likewise.
697 (insert_nps_misc_imm_offset): Likewise.
698 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
701 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
702 Jiong Wang <jiong.wang@arm.com>
704 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
706 * aarch64-dis-2.c: Regenerated.
708 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
710 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
713 2017-07-20 Nick Clifton <nickc@redhat.com>
715 * po/de.po: Updated German translation.
717 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
719 * arc-regs.h (sec_stat): New aux register.
720 (aux_kernel_sp): Likewise.
721 (aux_sec_u_sp): Likewise.
722 (aux_sec_k_sp): Likewise.
723 (sec_vecbase_build): Likewise.
724 (nsc_table_top): Likewise.
725 (nsc_table_base): Likewise.
726 (ersec_stat): Likewise.
727 (aux_sec_except): Likewise.
729 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
731 * arc-opc.c (extract_uimm12_20): New function.
732 (UIMM12_20): New operand.
734 * arc-tbl.h (sjli): Add new instruction.
736 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
737 John Eric Martin <John.Martin@emmicro-us.com>
739 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
740 (UIMM3_23): Adjust accordingly.
741 * arc-regs.h: Add/correct jli_base register.
742 * arc-tbl.h (jli_s): Likewise.
744 2017-07-18 Nick Clifton <nickc@redhat.com>
747 * aarch64-opc.c: Fix spelling typos.
748 * i386-dis.c: Likewise.
750 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
752 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
753 max_addr_offset and octets variables to size_t.
755 2017-07-12 Alan Modra <amodra@gmail.com>
757 * po/da.po: Update from translationproject.org/latest/opcodes/.
758 * po/de.po: Likewise.
759 * po/es.po: Likewise.
760 * po/fi.po: Likewise.
761 * po/fr.po: Likewise.
762 * po/id.po: Likewise.
763 * po/it.po: Likewise.
764 * po/nl.po: Likewise.
765 * po/pt_BR.po: Likewise.
766 * po/ro.po: Likewise.
767 * po/sv.po: Likewise.
768 * po/tr.po: Likewise.
769 * po/uk.po: Likewise.
770 * po/vi.po: Likewise.
771 * po/zh_CN.po: Likewise.
773 2017-07-11 Yao Qi <yao.qi@linaro.org>
774 Alan Modra <amodra@gmail.com>
776 * cgen.sh: Mark generated files read-only.
777 * epiphany-asm.c: Regenerate.
778 * epiphany-desc.c: Regenerate.
779 * epiphany-desc.h: Regenerate.
780 * epiphany-dis.c: Regenerate.
781 * epiphany-ibld.c: Regenerate.
782 * epiphany-opc.c: Regenerate.
783 * epiphany-opc.h: Regenerate.
784 * fr30-asm.c: Regenerate.
785 * fr30-desc.c: Regenerate.
786 * fr30-desc.h: Regenerate.
787 * fr30-dis.c: Regenerate.
788 * fr30-ibld.c: Regenerate.
789 * fr30-opc.c: Regenerate.
790 * fr30-opc.h: Regenerate.
791 * frv-asm.c: Regenerate.
792 * frv-desc.c: Regenerate.
793 * frv-desc.h: Regenerate.
794 * frv-dis.c: Regenerate.
795 * frv-ibld.c: Regenerate.
796 * frv-opc.c: Regenerate.
797 * frv-opc.h: Regenerate.
798 * ip2k-asm.c: Regenerate.
799 * ip2k-desc.c: Regenerate.
800 * ip2k-desc.h: Regenerate.
801 * ip2k-dis.c: Regenerate.
802 * ip2k-ibld.c: Regenerate.
803 * ip2k-opc.c: Regenerate.
804 * ip2k-opc.h: Regenerate.
805 * iq2000-asm.c: Regenerate.
806 * iq2000-desc.c: Regenerate.
807 * iq2000-desc.h: Regenerate.
808 * iq2000-dis.c: Regenerate.
809 * iq2000-ibld.c: Regenerate.
810 * iq2000-opc.c: Regenerate.
811 * iq2000-opc.h: Regenerate.
812 * lm32-asm.c: Regenerate.
813 * lm32-desc.c: Regenerate.
814 * lm32-desc.h: Regenerate.
815 * lm32-dis.c: Regenerate.
816 * lm32-ibld.c: Regenerate.
817 * lm32-opc.c: Regenerate.
818 * lm32-opc.h: Regenerate.
819 * lm32-opinst.c: Regenerate.
820 * m32c-asm.c: Regenerate.
821 * m32c-desc.c: Regenerate.
822 * m32c-desc.h: Regenerate.
823 * m32c-dis.c: Regenerate.
824 * m32c-ibld.c: Regenerate.
825 * m32c-opc.c: Regenerate.
826 * m32c-opc.h: Regenerate.
827 * m32r-asm.c: Regenerate.
828 * m32r-desc.c: Regenerate.
829 * m32r-desc.h: Regenerate.
830 * m32r-dis.c: Regenerate.
831 * m32r-ibld.c: Regenerate.
832 * m32r-opc.c: Regenerate.
833 * m32r-opc.h: Regenerate.
834 * m32r-opinst.c: Regenerate.
835 * mep-asm.c: Regenerate.
836 * mep-desc.c: Regenerate.
837 * mep-desc.h: Regenerate.
838 * mep-dis.c: Regenerate.
839 * mep-ibld.c: Regenerate.
840 * mep-opc.c: Regenerate.
841 * mep-opc.h: Regenerate.
842 * mt-asm.c: Regenerate.
843 * mt-desc.c: Regenerate.
844 * mt-desc.h: Regenerate.
845 * mt-dis.c: Regenerate.
846 * mt-ibld.c: Regenerate.
847 * mt-opc.c: Regenerate.
848 * mt-opc.h: Regenerate.
849 * or1k-asm.c: Regenerate.
850 * or1k-desc.c: Regenerate.
851 * or1k-desc.h: Regenerate.
852 * or1k-dis.c: Regenerate.
853 * or1k-ibld.c: Regenerate.
854 * or1k-opc.c: Regenerate.
855 * or1k-opc.h: Regenerate.
856 * or1k-opinst.c: Regenerate.
857 * xc16x-asm.c: Regenerate.
858 * xc16x-desc.c: Regenerate.
859 * xc16x-desc.h: Regenerate.
860 * xc16x-dis.c: Regenerate.
861 * xc16x-ibld.c: Regenerate.
862 * xc16x-opc.c: Regenerate.
863 * xc16x-opc.h: Regenerate.
864 * xstormy16-asm.c: Regenerate.
865 * xstormy16-desc.c: Regenerate.
866 * xstormy16-desc.h: Regenerate.
867 * xstormy16-dis.c: Regenerate.
868 * xstormy16-ibld.c: Regenerate.
869 * xstormy16-opc.c: Regenerate.
870 * xstormy16-opc.h: Regenerate.
872 2017-07-07 Alan Modra <amodra@gmail.com>
874 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
875 * m32c-dis.c: Regenerate.
876 * mep-dis.c: Regenerate.
878 2017-07-05 Borislav Petkov <bp@suse.de>
880 * i386-dis.c: Enable ModRM.reg /6 aliases.
882 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
884 * opcodes/arm-dis.c: Support MVFR2 in disassembly
887 2017-07-04 Tristan Gingold <gingold@adacore.com>
889 * configure: Regenerate.
891 2017-07-03 Tristan Gingold <gingold@adacore.com>
893 * po/opcodes.pot: Regenerate.
895 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
897 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
898 entries to the MSA ASE instruction block.
900 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
901 Maciej W. Rozycki <macro@imgtec.com>
903 * micromips-opc.c (XPA, XPAVZ): New macros.
904 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
907 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
908 Maciej W. Rozycki <macro@imgtec.com>
910 * micromips-opc.c (I36): New macro.
911 (micromips_opcodes): Add "eretnc".
913 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
914 Andrew Bennett <andrew.bennett@imgtec.com>
916 * mips-dis.c (mips_calculate_combination_ases): Handle the
918 (parse_mips_ase_option): New function.
919 (parse_mips_dis_option): Factor out ASE option handling to the
920 new function. Call `mips_calculate_combination_ases'.
921 * mips-opc.c (XPAVZ): New macro.
922 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
923 "mfhgc0", "mthc0" and "mthgc0".
925 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
927 * mips-dis.c (mips_calculate_combination_ases): New function.
928 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
929 calculation to the new function.
930 (set_default_mips_dis_options): Call the new function.
932 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
934 * arc-dis.c (parse_disassembler_options): Use
935 FOR_EACH_DISASSEMBLER_OPTION.
937 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
939 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
940 disassembler option strings.
941 (parse_cpu_option): Likewise.
943 2017-06-28 Tamar Christina <tamar.christina@arm.com>
945 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
946 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
947 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
948 (aarch64_feature_dotprod, DOT_INSN): New.
950 * aarch64-dis-2.c: Regenerated.
952 2017-06-28 Jiong Wang <jiong.wang@arm.com>
954 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
956 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
957 Matthew Fortune <matthew.fortune@imgtec.com>
958 Andrew Bennett <andrew.bennett@imgtec.com>
960 * mips-formats.h (INT_BIAS): New macro.
961 (INT_ADJ): Redefine in INT_BIAS terms.
962 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
963 (mips_print_save_restore): New function.
964 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
965 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
967 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
968 (print_mips16_insn_arg): Call `mips_print_save_restore' for
969 OP_SAVE_RESTORE_LIST handling, factored out from here.
970 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
971 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
972 (mips_builtin_opcodes): Add "restore" and "save" entries.
973 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
975 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
977 2017-06-23 Andrew Waterman <andrew@sifive.com>
979 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
980 alias; do not mark SLTI instruction as an alias.
982 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
984 * i386-dis.c (RM_0FAE_REG_5): Removed.
985 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
986 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
987 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
988 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
989 PREFIX_MOD_3_0F01_REG_5_RM_0.
990 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
991 PREFIX_MOD_3_0FAE_REG_5.
992 (mod_table): Update MOD_0FAE_REG_5.
993 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
994 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
995 * i386-tbl.h: Regenerated.
997 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
999 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1000 * i386-opc.tbl: Likewise.
1001 * i386-tbl.h: Regenerated.
1003 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1005 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1007 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1010 2017-06-19 Nick Clifton <nickc@redhat.com>
1013 * score-dis.c (score_opcodes): Add sentinel.
1015 2017-06-16 Alan Modra <amodra@gmail.com>
1017 * rx-decode.c: Regenerate.
1019 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1022 * i386-dis.c (OP_E_register): Check valid bnd register.
1025 2017-06-15 Nick Clifton <nickc@redhat.com>
1028 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1031 2017-06-15 Nick Clifton <nickc@redhat.com>
1034 * rl78-decode.opc (OP_BUF_LEN): Define.
1035 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1036 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1038 * rl78-decode.c: Regenerate.
1040 2017-06-15 Nick Clifton <nickc@redhat.com>
1043 * bfin-dis.c (gregs): Clip index to prevent overflow.
1045 (regs_lo): Likewise.
1046 (regs_hi): Likewise.
1048 2017-06-14 Nick Clifton <nickc@redhat.com>
1051 * score7-dis.c (score_opcodes): Add sentinel.
1053 2017-06-14 Yao Qi <yao.qi@linaro.org>
1055 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1056 * arm-dis.c: Likewise.
1057 * ia64-dis.c: Likewise.
1058 * mips-dis.c: Likewise.
1059 * spu-dis.c: Likewise.
1060 * disassemble.h (print_insn_aarch64): New declaration, moved from
1062 (print_insn_big_arm, print_insn_big_mips): Likewise.
1063 (print_insn_i386, print_insn_ia64): Likewise.
1064 (print_insn_little_arm, print_insn_little_mips): Likewise.
1066 2017-06-14 Nick Clifton <nickc@redhat.com>
1069 * rx-decode.opc: Include libiberty.h
1070 (GET_SCALE): New macro - validates access to SCALE array.
1071 (GET_PSCALE): New macro - validates access to PSCALE array.
1072 (DIs, SIs, S2Is, rx_disp): Use new macros.
1073 * rx-decode.c: Regenerate.
1075 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1077 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1079 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1081 * arc-dis.c (enforced_isa_mask): Declare.
1082 (cpu_types): Likewise.
1083 (parse_cpu_option): New function.
1084 (parse_disassembler_options): Use it.
1085 (print_insn_arc): Use enforced_isa_mask.
1086 (print_arc_disassembler_options): Document new options.
1088 2017-05-24 Yao Qi <yao.qi@linaro.org>
1090 * alpha-dis.c: Include disassemble.h, don't include
1092 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1093 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1094 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1095 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1096 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1097 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1098 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1099 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1100 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1101 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1102 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1103 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1104 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1105 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1106 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1107 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1108 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1109 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1110 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1111 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1112 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1113 * z80-dis.c, z8k-dis.c: Likewise.
1114 * disassemble.h: New file.
1116 2017-05-24 Yao Qi <yao.qi@linaro.org>
1118 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1119 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1121 2017-05-24 Yao Qi <yao.qi@linaro.org>
1123 * disassemble.c (disassembler): Add arguments a, big and mach.
1126 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1128 * i386-dis.c (NOTRACK_Fixup): New.
1129 (NOTRACK): Likewise.
1130 (NOTRACK_PREFIX): Likewise.
1131 (last_active_prefix): Likewise.
1132 (reg_table): Use NOTRACK on indirect call and jmp.
1133 (ckprefix): Set last_active_prefix.
1134 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1135 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1136 * i386-opc.h (NoTrackPrefixOk): New.
1137 (i386_opcode_modifier): Add notrackprefixok.
1138 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1140 * i386-tbl.h: Regenerated.
1142 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1144 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1146 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1147 bfd_mach_sparc_v9m8.
1148 (print_insn_sparc): Handle new operand types.
1149 * sparc-opc.c (MASK_M8): Define.
1151 (v6notlet): Likewise.
1162 (v9andleon): Likewise.
1165 (HWS2_VM8): Likewise.
1166 (sparc_opcode_archs): Add entry for "m8".
1167 (sparc_opcodes): Add OSA2017 and M8 instructions
1168 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1170 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1171 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1172 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1173 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1174 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1175 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1176 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1177 ASI_CORE_SELECT_COMMIT_NHT.
1179 2017-05-18 Alan Modra <amodra@gmail.com>
1181 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1182 * aarch64-dis.c: Likewise.
1183 * aarch64-gen.c: Likewise.
1184 * aarch64-opc.c: Likewise.
1186 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1187 Matthew Fortune <matthew.fortune@imgtec.com>
1189 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1190 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1191 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1192 (print_insn_arg) <OP_REG28>: Add handler.
1193 (validate_insn_args) <OP_REG28>: Handle.
1194 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1195 32-bit encoding and 9-bit immediates.
1196 (print_insn_mips16): Handle MIPS16 instructions that require
1197 32-bit encoding and MFC0/MTC0 operand decoding.
1198 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1199 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1200 (RD_C0, WR_C0, E2, E2MT): New macros.
1201 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1202 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1203 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1204 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1205 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1206 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1207 instructions, "swl", "swr", "sync" and its "sync_acquire",
1208 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1209 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1210 regular/extended entries for original MIPS16 ISA revision
1211 instructions whose extended forms are subdecoded in the MIPS16e2
1212 ISA revision: "li", "sll" and "srl".
1214 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1216 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1217 reference in CP0 move operand decoding.
1219 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1221 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1222 type to hexadecimal.
1223 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1225 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1227 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1228 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1229 "sync_rmb" and "sync_wmb" as aliases.
1230 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1231 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1233 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1235 * arc-dis.c (parse_option): Update quarkse_em option..
1236 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1238 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1240 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1242 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1244 2017-05-01 Michael Clark <michaeljclark@mac.com>
1246 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1249 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1251 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1252 and branches and not synthetic data instructions.
1254 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1256 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1258 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1260 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1261 * arc-opc.c (insert_r13el): New function.
1263 * arc-tbl.h: Add new enter/leave variants.
1265 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1267 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1269 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1271 * mips-dis.c (print_mips_disassembler_options): Add
1274 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1276 * mips16-opc.c (AL): New macro.
1277 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1278 of "ld" and "lw" as aliases.
1280 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1282 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1285 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1286 Alan Modra <amodra@gmail.com>
1288 * ppc-opc.c (ELEV): Define.
1289 (vle_opcodes): Add se_rfgi and e_sc.
1290 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1293 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1295 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1297 2017-04-21 Nick Clifton <nickc@redhat.com>
1300 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1303 2017-04-13 Alan Modra <amodra@gmail.com>
1305 * epiphany-desc.c: Regenerate.
1306 * fr30-desc.c: Regenerate.
1307 * frv-desc.c: Regenerate.
1308 * ip2k-desc.c: Regenerate.
1309 * iq2000-desc.c: Regenerate.
1310 * lm32-desc.c: Regenerate.
1311 * m32c-desc.c: Regenerate.
1312 * m32r-desc.c: Regenerate.
1313 * mep-desc.c: Regenerate.
1314 * mt-desc.c: Regenerate.
1315 * or1k-desc.c: Regenerate.
1316 * xc16x-desc.c: Regenerate.
1317 * xstormy16-desc.c: Regenerate.
1319 2017-04-11 Alan Modra <amodra@gmail.com>
1321 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1322 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1323 PPC_OPCODE_TMR for e6500.
1324 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1325 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1326 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1327 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1328 (PPCHTM): Define as PPC_OPCODE_POWER8.
1329 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1331 2017-04-10 Alan Modra <amodra@gmail.com>
1333 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1334 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1335 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1336 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1338 2017-04-09 Pip Cet <pipcet@gmail.com>
1340 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1341 appropriate floating-point precision directly.
1343 2017-04-07 Alan Modra <amodra@gmail.com>
1345 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1346 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1347 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1348 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1349 vector instructions with E6500 not PPCVEC2.
1351 2017-04-06 Pip Cet <pipcet@gmail.com>
1353 * Makefile.am: Add wasm32-dis.c.
1354 * configure.ac: Add wasm32-dis.c to wasm32 target.
1355 * disassemble.c: Add wasm32 disassembler code.
1356 * wasm32-dis.c: New file.
1357 * Makefile.in: Regenerate.
1358 * configure: Regenerate.
1359 * po/POTFILES.in: Regenerate.
1360 * po/opcodes.pot: Regenerate.
1362 2017-04-05 Pedro Alves <palves@redhat.com>
1364 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1365 * arm-dis.c (parse_arm_disassembler_options): Constify.
1366 * ppc-dis.c (powerpc_init_dialect): Constify local.
1367 * vax-dis.c (parse_disassembler_options): Constify.
1369 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1371 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1374 2017-03-30 Pip Cet <pipcet@gmail.com>
1376 * configure.ac: Add (empty) bfd_wasm32_arch target.
1377 * configure: Regenerate
1378 * po/opcodes.pot: Regenerate.
1380 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1382 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1384 * opcodes/sparc-opc.c (asi_table): New ASIs.
1386 2017-03-29 Alan Modra <amodra@gmail.com>
1388 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1390 (lookup_powerpc): Don't special case -1 dialect. Handle
1392 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1393 lookup_powerpc call, pass it on second.
1395 2017-03-27 Alan Modra <amodra@gmail.com>
1398 * ppc-dis.c (struct ppc_mopt): Comment.
1399 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1401 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1403 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1404 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1405 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1406 (insert_nps_misc_imm_offset): New function.
1407 (extract_nps_misc imm_offset): New function.
1408 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1409 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1411 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1413 * s390-mkopc.c (main): Remove vx2 check.
1414 * s390-opc.txt: Remove vx2 instruction flags.
1416 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1418 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1419 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1420 (insert_nps_imm_offset): New function.
1421 (extract_nps_imm_offset): New function.
1422 (insert_nps_imm_entry): New function.
1423 (extract_nps_imm_entry): New function.
1425 2017-03-17 Alan Modra <amodra@gmail.com>
1428 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1429 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1430 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1432 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1434 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1438 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1440 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1442 2017-03-13 Andrew Waterman <andrew@sifive.com>
1444 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1449 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1451 * i386-gen.c (opcode_modifiers): Replace S with Load.
1452 * i386-opc.h (S): Removed.
1454 (i386_opcode_modifier): Replace s with load.
1455 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1456 and {evex}. Replace S with Load.
1457 * i386-tbl.h: Regenerated.
1459 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1461 * i386-opc.tbl: Use CpuCET on rdsspq.
1462 * i386-tbl.h: Regenerated.
1464 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1466 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1467 <vsx>: Do not use PPC_OPCODE_VSX3;
1469 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1471 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1473 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1475 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1476 (MOD_0F1E_PREFIX_1): Likewise.
1477 (MOD_0F38F5_PREFIX_2): Likewise.
1478 (MOD_0F38F6_PREFIX_0): Likewise.
1479 (RM_0F1E_MOD_3_REG_7): Likewise.
1480 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1481 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1482 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1483 (PREFIX_0F1E): Likewise.
1484 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1485 (PREFIX_0F38F5): Likewise.
1486 (dis386_twobyte): Use PREFIX_0F1E.
1487 (reg_table): Add REG_0F1E_MOD_3.
1488 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1489 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1490 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1491 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1492 (three_byte_table): Use PREFIX_0F38F5.
1493 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1494 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1495 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1496 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1497 PREFIX_MOD_3_0F01_REG_5_RM_2.
1498 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1499 (cpu_flags): Add CpuCET.
1500 * i386-opc.h (CpuCET): New enum.
1501 (CpuUnused): Commented out.
1502 (i386_cpu_flags): Add cpucet.
1503 * i386-opc.tbl: Add Intel CET instructions.
1504 * i386-init.h: Regenerated.
1505 * i386-tbl.h: Likewise.
1507 2017-03-06 Alan Modra <amodra@gmail.com>
1510 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1511 (extract_raq, extract_ras, extract_rbx): New functions.
1512 (powerpc_operands): Use opposite corresponding insert function.
1514 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1515 register restriction.
1517 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1519 * disassemble.c Include "safe-ctype.h".
1520 (disassemble_init_for_target): Handle s390 init.
1521 (remove_whitespace_and_extra_commas): New function.
1522 (disassembler_options_cmp): Likewise.
1523 * arm-dis.c: Include "libiberty.h".
1525 (regnames): Use long disassembler style names.
1526 Add force-thumb and no-force-thumb options.
1527 (NUM_ARM_REGNAMES): Rename from this...
1528 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1529 (get_arm_regname_num_options): Delete.
1530 (set_arm_regname_option): Likewise.
1531 (get_arm_regnames): Likewise.
1532 (parse_disassembler_options): Likewise.
1533 (parse_arm_disassembler_option): Rename from this...
1534 (parse_arm_disassembler_options): ...to this. Make static.
1535 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1536 (print_insn): Use parse_arm_disassembler_options.
1537 (disassembler_options_arm): New function.
1538 (print_arm_disassembler_options): Handle updated regnames.
1539 * ppc-dis.c: Include "libiberty.h".
1540 (ppc_opts): Add "32" and "64" entries.
1541 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1542 (powerpc_init_dialect): Add break to switch statement.
1543 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1544 (disassembler_options_powerpc): New function.
1545 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1546 Remove printing of "32" and "64".
1547 * s390-dis.c: Include "libiberty.h".
1548 (init_flag): Remove unneeded variable.
1549 (struct s390_options_t): New structure type.
1550 (options): New structure.
1551 (init_disasm): Rename from this...
1552 (disassemble_init_s390): ...to this. Add initializations for
1553 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1554 (print_insn_s390): Delete call to init_disasm.
1555 (disassembler_options_s390): New function.
1556 (print_s390_disassembler_options): Print using information from
1558 * po/opcodes.pot: Regenerate.
1560 2017-02-28 Jan Beulich <jbeulich@suse.com>
1562 * i386-dis.c (PCMPESTR_Fixup): New.
1563 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1564 (prefix_table): Use PCMPESTR_Fixup.
1565 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1567 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1568 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1569 Split 64-bit and non-64-bit variants.
1570 * opcodes/i386-tbl.h: Re-generate.
1572 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1574 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1575 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1576 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1577 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1578 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1579 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1580 (OP_SVE_V_HSD): New macros.
1581 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1582 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1583 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1584 (aarch64_opcode_table): Add new SVE instructions.
1585 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1586 for rotation operands. Add new SVE operands.
1587 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1588 (ins_sve_quad_index): Likewise.
1589 (ins_imm_rotate): Split into...
1590 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1591 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1592 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1594 (aarch64_ins_sve_addr_ri_s4): New function.
1595 (aarch64_ins_sve_quad_index): Likewise.
1596 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1597 * aarch64-asm-2.c: Regenerate.
1598 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1599 (ext_sve_quad_index): Likewise.
1600 (ext_imm_rotate): Split into...
1601 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1602 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1603 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1605 (aarch64_ext_sve_addr_ri_s4): New function.
1606 (aarch64_ext_sve_quad_index): Likewise.
1607 (aarch64_ext_sve_index): Allow quad indices.
1608 (do_misc_decoding): Likewise.
1609 * aarch64-dis-2.c: Regenerate.
1610 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1611 aarch64_field_kinds.
1612 (OPD_F_OD_MASK): Widen by one bit.
1613 (OPD_F_NO_ZR): Bump accordingly.
1614 (get_operand_field_width): New function.
1615 * aarch64-opc.c (fields): Add new SVE fields.
1616 (operand_general_constraint_met_p): Handle new SVE operands.
1617 (aarch64_print_operand): Likewise.
1618 * aarch64-opc-2.c: Regenerate.
1620 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1622 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1623 (aarch64_feature_compnum): ...this.
1624 (SIMD_V8_3): Replace with...
1626 (CNUM_INSN): New macro.
1627 (aarch64_opcode_table): Use it for the complex number instructions.
1629 2017-02-24 Jan Beulich <jbeulich@suse.com>
1631 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1633 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1635 Add support for associating SPARC ASIs with an architecture level.
1636 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1637 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1638 decoding of SPARC ASIs.
1640 2017-02-23 Jan Beulich <jbeulich@suse.com>
1642 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1643 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1645 2017-02-21 Jan Beulich <jbeulich@suse.com>
1647 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1648 1 (instead of to itself). Correct typo.
1650 2017-02-14 Andrew Waterman <andrew@sifive.com>
1652 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1655 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1657 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1658 (aarch64_sys_reg_supported_p): Handle them.
1660 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1662 * arc-opc.c (UIMM6_20R): Define.
1663 (SIMM12_20): Use above.
1664 (SIMM12_20R): Define.
1665 (SIMM3_5_S): Use above.
1666 (UIMM7_A32_11R_S): Define.
1667 (UIMM7_9_S): Use above.
1668 (UIMM3_13R_S): Define.
1669 (SIMM11_A32_7_S): Use above.
1671 (UIMM10_A32_8_S): Use above.
1672 (UIMM8_8R_S): Define.
1674 (arc_relax_opcodes): Use all above defines.
1676 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1678 * arc-regs.h: Distinguish some of the registers different on
1679 ARC700 and HS38 cpus.
1681 2017-02-14 Alan Modra <amodra@gmail.com>
1684 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1685 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1687 2017-02-11 Stafford Horne <shorne@gmail.com>
1688 Alan Modra <amodra@gmail.com>
1690 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1691 Use insn_bytes_value and insn_int_value directly instead. Don't
1692 free allocated memory until function exit.
1694 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1696 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1698 2017-02-03 Nick Clifton <nickc@redhat.com>
1701 * aarch64-opc.c (print_register_list): Ensure that the register
1702 list index will fir into the tb buffer.
1703 (print_register_offset_address): Likewise.
1704 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1706 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1709 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1710 instructions when the previous fetch packet ends with a 32-bit
1713 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1715 * pru-opc.c: Remove vague reference to a future GDB port.
1717 2017-01-20 Nick Clifton <nickc@redhat.com>
1719 * po/ga.po: Updated Irish translation.
1721 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1723 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1725 2017-01-13 Yao Qi <yao.qi@linaro.org>
1727 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1728 if FETCH_DATA returns 0.
1729 (m68k_scan_mask): Likewise.
1730 (print_insn_m68k): Update code to handle -1 return value.
1732 2017-01-13 Yao Qi <yao.qi@linaro.org>
1734 * m68k-dis.c (enum print_insn_arg_error): New.
1735 (NEXTBYTE): Replace -3 with
1736 PRINT_INSN_ARG_MEMORY_ERROR.
1737 (NEXTULONG): Likewise.
1738 (NEXTSINGLE): Likewise.
1739 (NEXTDOUBLE): Likewise.
1740 (NEXTDOUBLE): Likewise.
1741 (NEXTPACKED): Likewise.
1742 (FETCH_ARG): Likewise.
1743 (FETCH_DATA): Update comments.
1744 (print_insn_arg): Update comments. Replace magic numbers with
1746 (match_insn_m68k): Likewise.
1748 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1750 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1751 * i386-dis-evex.h (evex_table): Updated.
1752 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1753 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1754 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1755 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1756 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1757 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1758 * i386-init.h: Regenerate.
1759 * i386-tbl.h: Ditto.
1761 2017-01-12 Yao Qi <yao.qi@linaro.org>
1763 * msp430-dis.c (msp430_singleoperand): Return -1 if
1764 msp430dis_opcode_signed returns false.
1765 (msp430_doubleoperand): Likewise.
1766 (msp430_branchinstr): Return -1 if
1767 msp430dis_opcode_unsigned returns false.
1768 (msp430x_calla_instr): Likewise.
1769 (print_insn_msp430): Likewise.
1771 2017-01-05 Nick Clifton <nickc@redhat.com>
1774 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1775 could not be matched.
1776 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1779 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1781 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1782 (aarch64_opcode_table): Use RCPC_INSN.
1784 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1786 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1788 * riscv-opcodes/all-opcodes: Likewise.
1790 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1792 * riscv-dis.c (print_insn_args): Add fall through comment.
1794 2017-01-03 Nick Clifton <nickc@redhat.com>
1796 * po/sr.po: New Serbian translation.
1797 * configure.ac (ALL_LINGUAS): Add sr.
1798 * configure: Regenerate.
1800 2017-01-02 Alan Modra <amodra@gmail.com>
1802 * epiphany-desc.h: Regenerate.
1803 * epiphany-opc.h: Regenerate.
1804 * fr30-desc.h: Regenerate.
1805 * fr30-opc.h: Regenerate.
1806 * frv-desc.h: Regenerate.
1807 * frv-opc.h: Regenerate.
1808 * ip2k-desc.h: Regenerate.
1809 * ip2k-opc.h: Regenerate.
1810 * iq2000-desc.h: Regenerate.
1811 * iq2000-opc.h: Regenerate.
1812 * lm32-desc.h: Regenerate.
1813 * lm32-opc.h: Regenerate.
1814 * m32c-desc.h: Regenerate.
1815 * m32c-opc.h: Regenerate.
1816 * m32r-desc.h: Regenerate.
1817 * m32r-opc.h: Regenerate.
1818 * mep-desc.h: Regenerate.
1819 * mep-opc.h: Regenerate.
1820 * mt-desc.h: Regenerate.
1821 * mt-opc.h: Regenerate.
1822 * or1k-desc.h: Regenerate.
1823 * or1k-opc.h: Regenerate.
1824 * xc16x-desc.h: Regenerate.
1825 * xc16x-opc.h: Regenerate.
1826 * xstormy16-desc.h: Regenerate.
1827 * xstormy16-opc.h: Regenerate.
1829 2017-01-02 Alan Modra <amodra@gmail.com>
1831 Update year range in copyright notice of all files.
1833 For older changes see ChangeLog-2016
1835 Copyright (C) 2017 Free Software Foundation, Inc.
1837 Copying and distribution of this file, with or without modification,
1838 are permitted in any medium without royalty provided the copyright
1839 notice and this notice are preserved.
1845 version-control: never