opcodes/ChangeLog

   1 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
   2
   3         * s390-dis.c (print_insn_s390): Pick instruction with most
   4         specific mask.
   5         * s390-opc.c: Add unused bits to the insn mask.
   6         * s390-opc.txt: Reorder some instructions to prefer more recent
   7         versions.
   8
   9 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
  10
  11         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
  12         correction to unaligned PCs while printing comment.
  13
  14 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  15
  16         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
  17         (thumb32_opcodes): Likewise.
  18         (banked_regname): New function.
  19         (print_insn_arm): Add Virtualization Extensions support.
  20         (print_insn_thumb32): Likewise.
  21
  22 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  23
  24         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  25         ARM state.
  26
  27 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  28
  29         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  30         (thumb32_opcodes): Likewise.
  31
  32 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  33
  34         * arm-dis.c (arm_opcodes): Add support for pldw.
  35         (thumb32_opcodes): Likewise.
  36
  37 2010-09-22  Robin Getz  <robin.getz@analog.com>
  38
  39         * bfin-dis.c (fmtconst): Cast address to 32bits.
  40
  41 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  42
  43         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  44
  45 2010-09-22  Robin Getz  <robin.getz@analog.com>
  46
  47         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  48         Reject P6/P7 to TESTSET.
  49         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  50         SP onto the stack.
  51         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  52         P/D fields match all the time.
  53         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  54         are 0 for accumulator compares.
  55         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  56         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  57         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  58         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  59         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  60         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  61         insns.
  62         (decode_dagMODim_0): Verify br field for IREG ops.
  63         (decode_LDST_0): Reject preg load into same preg.
  64         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  65         (print_insn_bfin): Likewise.
  66
  67 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  68
  69         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  70
  71 2010-09-22  Robin Getz  <robin.getz@analog.com>
  72
  73         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
  74
  75 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  76
  77         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
  78
  79 2010-09-22  Robin Getz  <robin.getz@analog.com>
  80
  81         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
  82         register values greater than 8.
  83         (IS_RESERVEDREG, allreg, mostreg): New helpers.
  84         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
  85         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
  86         (decode_CC2dreg_0): Check valid CC register number.
  87
  88 2010-09-22  Robin Getz  <robin.getz@analog.com>
  89
  90         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
  91
  92 2010-09-22  Robin Getz  <robin.getz@analog.com>
  93
  94         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
  95         (reg_names): Likewise.
  96         (decode_statbits): Likewise; while reformatting to make manageable.
  97
  98 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  99
 100         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 101         (decode_pseudoOChar_0): New function.
 102         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 103
 104 2010-09-22  Robin Getz  <robin.getz@analog.com>
 105
 106         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 107         LSHIFT instead of SHIFT.
 108
 109 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 110
 111         * bfin-dis.c (constant_formats): Constify the whole structure.
 112         (fmtconst): Add const to return value.
 113         (reg_names): Mark const.
 114         (decode_multfunc): Mark s0/s1 as const.
 115         (decode_macfunc): Mark a/sop as const.
 116
 117 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 118
 119         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 120
 121 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 122
 123         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 124         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 125
 126 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 127
 128         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 129         dlx_insn_type array.
 130
 131 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 132
 133         PR binutils/11960
 134         * i386-dis.c (sIv): New.
 135         (dis386): Replace Iq with sIv on "pushT".
 136         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 137         (x86_64_table): Replace {T|}/{P|} with P.
 138         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 139         (OP_sI): Update v_mode.  Remove w_mode.
 140
 141 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 142
 143         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 144         on E500 and E500MC.
 145
 146 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 149         prefetchw.
 150
 151 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 152
 153         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 154         to processor flags for PENTIUMPRO processors and later.
 155         * i386-opc.h (enum): Add CpuNop.
 156         (i386_cpu_flags): Add cpunop bit.
 157         * i386-opc.tbl: Change nop cpu_flags.
 158         * i386-init.h: Regenerated.
 159         * i386-tbl.h: Likewise.
 160
 161 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 162
 163         * i386-opc.h (enum): Fix typos in comments.
 164
 165 2010-08-06  Alan Modra  <amodra@gmail.com>
 166
 167         * disassemble.c: Formatting.
 168         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 169
 170 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 171
 172         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 173         * i386-tbl.h: Regenerated.
 174
 175 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 178
 179         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 180         * i386-tbl.h: Regenerated.
 181
 182 2010-07-29  DJ Delorie  <dj@redhat.com>
 183
 184         * rx-decode.opc (SRR): New.
 185         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 186         r0,r0) and NOP3 (max r0,r0) special cases.
 187         * rx-decode.c: Regenerate.
 188
 189 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 190
 191         * i386-dis.c: Add 0F to VEX opcode enums.
 192
 193 2010-07-27  DJ Delorie  <dj@redhat.com>
 194
 195         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 196         (rx_decode_opcode): Likewise.
 197         * rx-decode.c: Regenerate.
 198
 199 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 200             Ina Pandit  <ina.pandit@kpitcummins.com>
 201
 202         * v850-dis.c (v850_sreg_names): Updated structure for system
 203         registers.
 204         (float_cc_names): new structure for condition codes.
 205         (print_value): Update the function that prints value.
 206         (get_operand_value): New function to get the operand value.
 207         (disassemble): Updated to handle the disassembly of instructions.
 208         (print_insn_v850): Updated function to print instruction for different
 209         families.
 210         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 211         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 212         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 213         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 214         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 215         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 216         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 217         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 218         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 219         (v850_operands): Update with the relocation name. Also update
 220         the instructions with specific set of processors.
 221
 222 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 223
 224         * arm-dis.c (print_insn_arm): Add cases for printing more
 225         symbolic operands.
 226         (print_insn_thumb32): Likewise.
 227
 228 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 229
 230         * mips-dis.c (print_insn_mips): Correct branch instruction type
 231         determination.
 232
 233 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 234
 235         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 236         type and delay slot determination.
 237         (print_insn_mips16): Extend branch instruction type and delay
 238         slot determination to cover all instructions.
 239         * mips16-opc.c (BR): Remove macro.
 240         (UBR, CBR): New macros.
 241         (mips16_opcodes): Update branch annotation for "b", "beqz",
 242         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 243         and "jrc".
 244
 245 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 246
 247         AVX Programming Reference (June, 2010)
 248         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 249         * i386-opc.tbl: Likewise.
 250         * i386-tbl.h: Regenerated.
 251
 252 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 253
 254         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 255
 256 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 257
 258         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 259         ppc_cpu_t before inverting.
 260         (ppc_parse_cpu): Likewise.
 261         (print_insn_powerpc): Likewise.
 262
 263 2010-07-03  Alan Modra  <amodra@gmail.com>
 264
 265         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 266         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 267         (PPC64, MFDEC2): Update.
 268         (NON32, NO371): Define.
 269         (powerpc_opcode): Update to not use old opcode flags, and avoid
 270         -m601 duplicates.
 271
 272 2010-07-03  DJ Delorie  <dj@delorie.com>
 273
 274         * m32c-ibld.c: Regenerate.
 275
 276 2010-07-03  Alan Modra  <amodra@gmail.com>
 277
 278         * ppc-opc.c (PWR2COM): Define.
 279         (PPCPWR2): Add PPC_OPCODE_COMMON.
 280         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 281         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 282         "rac" from -mcom.
 283
 284 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         AVX Programming Reference (June, 2010)
 287         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 288         (PREFIX_0FAE_REG_1): Likewise.
 289         (PREFIX_0FAE_REG_2): Likewise.
 290         (PREFIX_0FAE_REG_3): Likewise.
 291         (PREFIX_VEX_3813): Likewise.
 292         (PREFIX_VEX_3A1D): Likewise.
 293         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 294         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 295         PREFIX_VEX_3A1D.
 296         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 297         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 298         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 299
 300         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 301         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 302         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 303
 304         * i386-opc.h (CpuXsaveopt): New.
 305         (CpuFSGSBase): Likewise.
 306         (CpuRdRnd): Likewise.
 307         (CpuF16C): Likewise.
 308         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 309         cpuf16c.
 310
 311         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 312         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 313         * i386-init.h: Regenerated.
 314         * i386-tbl.h: Likewise.
 315
 316 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 317
 318         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 319         and mtocrf on EFS.
 320
 321 2010-06-29  Alan Modra  <amodra@gmail.com>
 322
 323         * maxq-dis.c: Delete file.
 324         * Makefile.am: Remove references to maxq.
 325         * configure.in: Likewise.
 326         * disassemble.c: Likewise.
 327         * Makefile.in: Regenerate.
 328         * configure: Regenerate.
 329         * po/POTFILES.in: Regenerate.
 330
 331 2010-06-29  Alan Modra  <amodra@gmail.com>
 332
 333         * mep-dis.c: Regenerate.
 334
 335 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 336
 337         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 338
 339 2010-06-27  Alan Modra  <amodra@gmail.com>
 340
 341         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 342         (decodeInstr): Likewise.
 343         * dlx-dis.c (print_insn_dlx): Likewise.
 344         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 345         * maxq-dis.c (check_move, print_insn): Likewise.
 346         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 347         * msp430-dis.c (msp430_branchinstr): Likewise.
 348         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 349         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 350         * sparc-dis.c (print_insn_sparc): Likewise.
 351         * fr30-asm.c: Regenerate.
 352         * frv-asm.c: Regenerate.
 353         * ip2k-asm.c: Regenerate.
 354         * iq2000-asm.c: Regenerate.
 355         * lm32-asm.c: Regenerate.
 356         * m32c-asm.c: Regenerate.
 357         * m32r-asm.c: Regenerate.
 358         * mep-asm.c: Regenerate.
 359         * mt-asm.c: Regenerate.
 360         * openrisc-asm.c: Regenerate.
 361         * xc16x-asm.c: Regenerate.
 362         * xstormy16-asm.c: Regenerate.
 363
 364 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 365
 366         PR gas/11673
 367         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 368
 369 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 370
 371         PR binutils/11676
 372         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 373
 374 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 375
 376         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 377         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 378         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 379         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 380         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 381         Treat lwsync as msync on e500.
 382
 383 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 384
 385         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 386
 387 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 388
 389         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 390         constants is the same on 32-bit and 64-bit hosts.
 391
 392 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 393
 394         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 395         .short directives so that they can be reassembled.
 396
 397 2010-05-26  Catherine Moore <clm@codesourcery.com>
 398             David Ung  <davidu@mips.com>
 399
 400         * mips-opc.c: Change membership to I1 for instructions ssnop and
 401         ehb.
 402
 403 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 404
 405         * i386-dis.c (sib): New.
 406         (get_sib): Likewise.
 407         (print_insn): Call get_sib.
 408         OP_E_memory): Use sib.
 409
 410 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 411
 412         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 413         * mips-opc.c (I16): Remove.
 414         (mips_builtin_op): Reclassify jalx.
 415
 416 2010-05-19  Alan Modra  <amodra@gmail.com>
 417
 418         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 419         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 420
 421 2010-05-13  Alan Modra  <amodra@gmail.com>
 422
 423         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 424
 425 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 426
 427         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 428         format.
 429         (print_insn_thumb16): Add support for new %W format.
 430
 431 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 432
 433         * Makefile.in: Regenerate with automake 1.11.1.
 434         * aclocal.m4: Ditto.
 435
 436 2010-05-05  Nick Clifton  <nickc@redhat.com>
 437
 438         * po/es.po: Updated Spanish translation.
 439
 440 2010-04-22  Nick Clifton  <nickc@redhat.com>
 441
 442         * po/opcodes.pot: Updated by the Translation project.
 443         * po/vi.po: Updated Vietnamese translation.
 444
 445 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 448         bits in opcode.
 449
 450 2010-04-09  Nick Clifton  <nickc@redhat.com>
 451
 452         * i386-dis.c (print_insn): Remove unused variable op.
 453         (OP_sI): Remove unused variable mask.
 454
 455 2010-04-07  Alan Modra  <amodra@gmail.com>
 456
 457         * configure: Regenerate.
 458
 459 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 460
 461         * ppc-opc.c (RBOPT): New define.
 462         ("dccci"): Enable for PPCA2.  Make operands optional.
 463         ("iccci"): Likewise.  Do not deprecate for PPC476.
 464
 465 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 466
 467         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 468
 469 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 470
 471         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 472         * Makefile.in: Regenerate.
 473         * configure.in (bfd_tic6x_arch): New.
 474         * configure: Regenerate.
 475         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 476         (disassembler): Handle TI C6X.
 477         * tic6x-dis.c: New.
 478
 479 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 480
 481         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 482
 483 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 484
 485         * dis-buf.c (buffer_read_memory): Give error for reading just
 486         before the start of memory.
 487
 488 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 489             Quentin Neill <quentin.neill@amd.com>
 490
 491         * i386-dis.c (OP_LWP_I): Removed.
 492         (reg_table): Do not use OP_LWP_I, use Iq.
 493         (OP_LWPCB_E): Remove use of names16.
 494         (OP_LWP_E): Same.
 495         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 496         should not set the Vex.length bit.
 497         * i386-tbl.h: Regenerated.
 498
 499 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 500
 501         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 502
 503 2010-02-24  Nick Clifton  <nickc@redhat.com>
 504
 505         PR binutils/6773
 506         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 507         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 508         (thumb32_opcodes): Likewise.
 509
 510 2010-02-15  Nick Clifton  <nickc@redhat.com>
 511
 512         * po/vi.po: Updated Vietnamese translation.
 513
 514 2010-02-12  Doug Evans  <dje@sebabeach.org>
 515
 516         * lm32-opinst.c: Regenerate.
 517
 518 2010-02-11  Doug Evans  <dje@sebabeach.org>
 519
 520         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 521         (print_address): Delete CGEN_PRINT_ADDRESS.
 522         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 523         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 524         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 525         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 526
 527         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 528         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 529         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 530         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 531         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 532         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 533         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 534         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 535         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 536         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 537         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 538         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 539
 540 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * i386-dis.c: Update copyright.
 543         * i386-gen.c: Likewise.
 544         * i386-opc.h: Likewise.
 545         * i386-opc.tbl: Likewise.
 546
 547 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 548             Sebastian Pop  <sebastian.pop@amd.com>
 549
 550         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 551         function to handle 5th imm8 operand.
 552         (PREFIX_VEX_3A48): Added.
 553         (PREFIX_VEX_3A49): Added.
 554         (VEX_W_3A48_P_2): Added.
 555         (VEX_W_3A49_P_2): Added.
 556         (prefix table): Added entries for PREFIX_VEX_3A48
 557         and PREFIX_VEX_3A49.
 558         (vex table): Added entries for VEX_W_3A48_P_2 and
 559         and VEX_W_3A49_P_2.
 560         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 561         for Vec_Imm4 operands.
 562         * i386-opc.h (enum): Added Vec_Imm4.
 563         (i386_operand_type): Added vec_imm4.
 564         * i386-opc.tbl: Add entries for vpermilp[ds].
 565         * i386-init.h: Regenerated.
 566         * i386-tbl.h: Regenerated.
 567
 568 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 569
 570         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 571         and "pwr7".  Move "a2" into alphabetical order.
 572
 573 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 574
 575         * ppc-dis.c (ppc_opts): Add titan entry.
 576         * ppc-opc.c (TITAN, MULHW): Define.
 577         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 578
 579 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 580
 581         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 582         to CPU_BDVER1_FLAGS
 583         * i386-init.h: Regenerated.
 584
 585 2010-02-03  Anthony Green  <green@moxielogic.com>
 586
 587         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 588         0x0f, and make 0x00 an illegal instruction.
 589
 590 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 591
 592         * opcodes/arm-dis.c (struct arm_private_data): New.
 593         (print_insn_coprocessor, print_insn_arm): Update to use struct
 594         arm_private_data.
 595         (is_mapping_symbol, get_map_sym_type): New functions.
 596         (get_sym_code_type): Check the symbol's section.  Do not check
 597         mapping symbols.
 598         (print_insn): Default to disassembling ARM mode code.  Check
 599         for mapping symbols separately from other symbols.  Use
 600         struct arm_private_data.
 601
 602 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         * i386-dis.c (EXVexWdqScalar): New.
 605         (vex_scalar_w_dq_mode): Likewise.
 606         (prefix_table): Update entries for PREFIX_VEX_3899,
 607         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 608         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 609         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 610         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 611         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 612         (OP_EX): Likewise.
 613
 614 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         * i386-dis.c (XMScalar): New.
 617         (EXdScalar): Likewise.
 618         (EXqScalar): Likewise.
 619         (EXqScalarS): Likewise.
 620         (VexScalar): Likewise.
 621         (EXdVexScalarS): Likewise.
 622         (EXqVexScalarS): Likewise.
 623         (XMVexScalar): Likewise.
 624         (scalar_mode): Likewise.
 625         (d_scalar_mode): Likewise.
 626         (d_scalar_swap_mode): Likewise.
 627         (q_scalar_mode): Likewise.
 628         (q_scalar_swap_mode): Likewise.
 629         (vex_scalar_mode): Likewise.
 630         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 631         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 632         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 633         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 634         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 635         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 636         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 637         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 638         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 639         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 640         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 641         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 642         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 643         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 644         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 645         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 646         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 647         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 648         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 649         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 650         q_scalar_mode, q_scalar_swap_mode.
 651         (OP_XMM): Handle scalar_mode.
 652         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 653         and q_scalar_swap_mode.
 654         (OP_VEX): Handle vex_scalar_mode.
 655
 656 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 657
 658         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 659
 660 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 661
 662         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 663
 664 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 667
 668 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * i386-dis.c (Bad_Opcode): New.
 671         (bad_opcode): Likewise.
 672         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 673         (dis386_twobyte): Likewise.
 674         (reg_table): Likewise.
 675         (prefix_table): Likewise.
 676         (x86_64_table): Likewise.
 677         (vex_len_table): Likewise.
 678         (vex_w_table): Likewise.
 679         (mod_table): Likewise.
 680         (rm_table): Likewise.
 681         (float_reg): Likewise.
 682         (reg_table): Remove trailing "(bad)" entries.
 683         (prefix_table): Likewise.
 684         (x86_64_table): Likewise.
 685         (vex_len_table): Likewise.
 686         (vex_w_table): Likewise.
 687         (mod_table): Likewise.
 688         (rm_table): Likewise.
 689         (get_valid_dis386): Handle bytemode 0.
 690
 691 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 692
 693         * i386-opc.h (VEXScalar): New.
 694
 695         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 696         instructions.
 697         * i386-tbl.h: Regenerated.
 698
 699 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 702
 703         * i386-opc.tbl: Add xsave64 and xrstor64.
 704         * i386-tbl.h: Regenerated.
 705
 706 2010-01-20  Nick Clifton  <nickc@redhat.com>
 707
 708         PR 11170
 709         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 710         based post-indexed addressing.
 711
 712 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 713
 714         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 715         * i386-tbl.h: Regenerated.
 716
 717 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 720         comments.
 721
 722 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 723
 724         * i386-dis.c (names_mm): New.
 725         (intel_names_mm): Likewise.
 726         (att_names_mm): Likewise.
 727         (names_xmm): Likewise.
 728         (intel_names_xmm): Likewise.
 729         (att_names_xmm): Likewise.
 730         (names_ymm): Likewise.
 731         (intel_names_ymm): Likewise.
 732         (att_names_ymm): Likewise.
 733         (print_insn): Set names_mm, names_xmm and names_ymm.
 734         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 735         (OP_XMM): Likewise.
 736         (OP_EM): Likewise.
 737         (OP_EMC): Likewise.
 738         (OP_MXC): Likewise.
 739         (OP_EX): Likewise.
 740         (XMM_Fixup): Likewise.
 741         (OP_VEX): Likewise.
 742         (OP_EX_VexReg): Likewise.
 743         (OP_Vex_2src): Likewise.
 744         (OP_Vex_2src_1): Likewise.
 745         (OP_Vex_2src_2): Likewise.
 746         (OP_REG_VexI4): Likewise.
 747
 748 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 749
 750         * i386-dis.c (print_insn): Update comments.
 751
 752 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 753
 754         * i386-dis.c (rex_original): Removed.
 755         (ckprefix): Remove rex_original.
 756         (print_insn): Update comments.
 757
 758 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 759
 760         * Makefile.in: Regenerate.
 761         * configure: Regenerate.
 762
 763 2010-01-07  Doug Evans  <dje@sebabeach.org>
 764
 765         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 766         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 767         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 768         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 769         * xstormy16-ibld.c: Regenerate.
 770
 771 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 772
 773         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 774         * i386-init.h: Regenerated.
 775
 776 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 777
 778         * arm-dis.c (print_insn): Fixed search for next symbol and data
 779         dumping condition, and the initial mapping symbol state.
 780
 781 2010-01-05  Doug Evans  <dje@sebabeach.org>
 782
 783         * cgen-ibld.in: #include "cgen/basic-modes.h".
 784         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 785         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 786         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 787         * xstormy16-ibld.c: Regenerate.
 788
 789 2010-01-04  Nick Clifton  <nickc@redhat.com>
 790
 791         PR 11123
 792         * arm-dis.c (print_insn_coprocessor): Initialise value.
 793
 794 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 795
 796         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 797
 798 2010-01-02  Doug Evans  <dje@sebabeach.org>
 799
 800         * cgen-asm.in: Update copyright year.
 801         * cgen-dis.in: Update copyright year.
 802         * cgen-ibld.in: Update copyright year.
 803         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 804         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 805         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 806         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 807         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 808         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 809         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 810         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 811         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 812         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 813         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 814         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 815         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 816         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 817         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 818         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 819         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 820         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 821         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 822         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 823         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 824
 825 For older changes see ChangeLog-2009
 826 \f
 827 Local Variables:
 828 mode: change-log
 829 left-margin: 8
 830 fill-column: 74
 831 version-control: never
 832 End: