opcodes/ChangeLog

   1 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
   2
   3         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
   4
   5 2017-03-13  Andrew Waterman  <andrew@sifive.com>
   6
   7         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
   8         <srl> Likewise.
   9         <srai> Likewise.
  10         <sra> Likewise.
  11
  12 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         * i386-gen.c (opcode_modifiers): Replace S with Load.
  15         * i386-opc.h (S): Removed.
  16         (Load): New.
  17         (i386_opcode_modifier): Replace s with load.
  18         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
  19         and {evex}.  Replace S with Load.
  20         * i386-tbl.h: Regenerated.
  21
  22 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         * i386-opc.tbl: Use CpuCET on rdsspq.
  25         * i386-tbl.h: Regenerated.
  26
  27 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  28
  29         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
  30         <vsx>: Do not use PPC_OPCODE_VSX3;
  31
  32 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  33
  34         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
  35
  36 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
  37
  38         * i386-dis.c (REG_0F1E_MOD_3): New enum.
  39         (MOD_0F1E_PREFIX_1): Likewise.
  40         (MOD_0F38F5_PREFIX_2): Likewise.
  41         (MOD_0F38F6_PREFIX_0): Likewise.
  42         (RM_0F1E_MOD_3_REG_7): Likewise.
  43         (PREFIX_MOD_0_0F01_REG_5): Likewise.
  44         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  45         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  46         (PREFIX_0F1E): Likewise.
  47         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  48         (PREFIX_0F38F5): Likewise.
  49         (dis386_twobyte): Use PREFIX_0F1E.
  50         (reg_table): Add REG_0F1E_MOD_3.
  51         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  52         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  53         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  54         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  55         (three_byte_table): Use PREFIX_0F38F5.
  56         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  57         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  58         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  59         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  60         PREFIX_MOD_3_0F01_REG_5_RM_2.
  61         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  62         (cpu_flags): Add CpuCET.
  63         * i386-opc.h (CpuCET): New enum.
  64         (CpuUnused): Commented out.
  65         (i386_cpu_flags): Add cpucet.
  66         * i386-opc.tbl: Add Intel CET instructions.
  67         * i386-init.h: Regenerated.
  68         * i386-tbl.h: Likewise.
  69
  70 2017-03-06  Alan Modra  <amodra@gmail.com>
  71
  72         PR 21124
  73         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
  74         (extract_raq, extract_ras, extract_rbx): New functions.
  75         (powerpc_operands): Use opposite corresponding insert function.
  76         (Q_MASK): Define.
  77         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
  78         register restriction.
  79
  80 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  81
  82         * disassemble.c Include "safe-ctype.h".
  83         (disassemble_init_for_target): Handle s390 init.
  84         (remove_whitespace_and_extra_commas): New function.
  85         (disassembler_options_cmp): Likewise.
  86         * arm-dis.c: Include "libiberty.h".
  87         (NUM_ELEM): Delete.
  88         (regnames): Use long disassembler style names.
  89         Add force-thumb and no-force-thumb options.
  90         (NUM_ARM_REGNAMES): Rename from this...
  91         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  92         (get_arm_regname_num_options): Delete.
  93         (set_arm_regname_option): Likewise.
  94         (get_arm_regnames): Likewise.
  95         (parse_disassembler_options): Likewise.
  96         (parse_arm_disassembler_option): Rename from this...
  97         (parse_arm_disassembler_options): ...to this.  Make static.
  98         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
  99         (print_insn): Use parse_arm_disassembler_options.
 100         (disassembler_options_arm): New function.
 101         (print_arm_disassembler_options): Handle updated regnames.
 102         * ppc-dis.c: Include "libiberty.h".
 103         (ppc_opts): Add "32" and "64" entries.
 104         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 105         (powerpc_init_dialect): Add break to switch statement.
 106         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 107         (disassembler_options_powerpc): New function.
 108         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 109         Remove printing of "32" and "64".
 110         * s390-dis.c: Include "libiberty.h".
 111         (init_flag): Remove unneeded variable.
 112         (struct s390_options_t): New structure type.
 113         (options): New structure.
 114         (init_disasm): Rename from this...
 115         (disassemble_init_s390): ...to this.  Add initializations for
 116         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 117         (print_insn_s390): Delete call to init_disasm.
 118         (disassembler_options_s390): New function.
 119         (print_s390_disassembler_options): Print using information from
 120         struct 'options'.
 121         * po/opcodes.pot: Regenerate.
 122
 123 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-dis.c (PCMPESTR_Fixup): New.
 126         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 127         (prefix_table): Use PCMPESTR_Fixup.
 128         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 129         PCMPESTR_Fixup.
 130         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 131         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 132         Split 64-bit and non-64-bit variants.
 133         * opcodes/i386-tbl.h: Re-generate.
 134
 135 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 136
 137         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 138         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 139         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 140         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 141         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 142         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 143         (OP_SVE_V_HSD): New macros.
 144         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 145         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 146         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 147         (aarch64_opcode_table): Add new SVE instructions.
 148         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 149         for rotation operands.  Add new SVE operands.
 150         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 151         (ins_sve_quad_index): Likewise.
 152         (ins_imm_rotate): Split into...
 153         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 154         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 155         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 156         functions.
 157         (aarch64_ins_sve_addr_ri_s4): New function.
 158         (aarch64_ins_sve_quad_index): Likewise.
 159         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 160         * aarch64-asm-2.c: Regenerate.
 161         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 162         (ext_sve_quad_index): Likewise.
 163         (ext_imm_rotate): Split into...
 164         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 165         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 166         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 167         functions.
 168         (aarch64_ext_sve_addr_ri_s4): New function.
 169         (aarch64_ext_sve_quad_index): Likewise.
 170         (aarch64_ext_sve_index): Allow quad indices.
 171         (do_misc_decoding): Likewise.
 172         * aarch64-dis-2.c: Regenerate.
 173         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 174         aarch64_field_kinds.
 175         (OPD_F_OD_MASK): Widen by one bit.
 176         (OPD_F_NO_ZR): Bump accordingly.
 177         (get_operand_field_width): New function.
 178         * aarch64-opc.c (fields): Add new SVE fields.
 179         (operand_general_constraint_met_p): Handle new SVE operands.
 180         (aarch64_print_operand): Likewise.
 181         * aarch64-opc-2.c: Regenerate.
 182
 183 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 184
 185         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 186         (aarch64_feature_compnum): ...this.
 187         (SIMD_V8_3): Replace with...
 188         (COMPNUM): ...this.
 189         (CNUM_INSN): New macro.
 190         (aarch64_opcode_table): Use it for the complex number instructions.
 191
 192 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 195
 196 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 197
 198         Add support for associating SPARC ASIs with an architecture level.
 199         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 200         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 201         decoding of SPARC ASIs.
 202
 203 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 206         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 207
 208 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 209
 210         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 211         1 (instead of to itself). Correct typo.
 212
 213 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 214
 215         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 216         pseudoinstructions.
 217
 218 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 219
 220         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 221         (aarch64_sys_reg_supported_p): Handle them.
 222
 223 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 224
 225         * arc-opc.c (UIMM6_20R): Define.
 226         (SIMM12_20): Use above.
 227         (SIMM12_20R): Define.
 228         (SIMM3_5_S): Use above.
 229         (UIMM7_A32_11R_S): Define.
 230         (UIMM7_9_S): Use above.
 231         (UIMM3_13R_S): Define.
 232         (SIMM11_A32_7_S): Use above.
 233         (SIMM9_8R): Define.
 234         (UIMM10_A32_8_S): Use above.
 235         (UIMM8_8R_S): Define.
 236         (W6): Use above.
 237         (arc_relax_opcodes): Use all above defines.
 238
 239 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 240
 241         * arc-regs.h: Distinguish some of the registers different on
 242         ARC700 and HS38 cpus.
 243
 244 2017-02-14  Alan Modra  <amodra@gmail.com>
 245
 246         PR 21118
 247         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 248         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 249
 250 2017-02-11  Stafford Horne  <shorne@gmail.com>
 251             Alan Modra  <amodra@gmail.com>
 252
 253         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 254         Use insn_bytes_value and insn_int_value directly instead.  Don't
 255         free allocated memory until function exit.
 256
 257 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 258
 259         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 260
 261 2017-02-03  Nick Clifton  <nickc@redhat.com>
 262
 263         PR 21096
 264         * aarch64-opc.c (print_register_list): Ensure that the register
 265         list index will fir into the tb buffer.
 266         (print_register_offset_address): Likewise.
 267         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 268
 269 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 270
 271         PR 21056
 272         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 273         instructions when the previous fetch packet ends with a 32-bit
 274         instruction.
 275
 276 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 277
 278         * pru-opc.c: Remove vague reference to a future GDB port.
 279
 280 2017-01-20  Nick Clifton  <nickc@redhat.com>
 281
 282         * po/ga.po: Updated Irish translation.
 283
 284 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 285
 286         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 287
 288 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 289
 290         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 291         if FETCH_DATA returns 0.
 292         (m68k_scan_mask): Likewise.
 293         (print_insn_m68k): Update code to handle -1 return value.
 294
 295 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 296
 297         * m68k-dis.c (enum print_insn_arg_error): New.
 298         (NEXTBYTE): Replace -3 with
 299         PRINT_INSN_ARG_MEMORY_ERROR.
 300         (NEXTULONG): Likewise.
 301         (NEXTSINGLE): Likewise.
 302         (NEXTDOUBLE): Likewise.
 303         (NEXTDOUBLE): Likewise.
 304         (NEXTPACKED): Likewise.
 305         (FETCH_ARG): Likewise.
 306         (FETCH_DATA): Update comments.
 307         (print_insn_arg): Update comments. Replace magic numbers with
 308         enum.
 309         (match_insn_m68k): Likewise.
 310
 311 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 312
 313         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 314         * i386-dis-evex.h (evex_table): Updated.
 315         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 316         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 317         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 318         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 319         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 320         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 321         * i386-init.h: Regenerate.
 322         * i386-tbl.h: Ditto.
 323
 324 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 325
 326         * msp430-dis.c (msp430_singleoperand): Return -1 if
 327         msp430dis_opcode_signed returns false.
 328         (msp430_doubleoperand): Likewise.
 329         (msp430_branchinstr): Return -1 if
 330         msp430dis_opcode_unsigned returns false.
 331         (msp430x_calla_instr): Likewise.
 332         (print_insn_msp430): Likewise.
 333
 334 2017-01-05  Nick Clifton  <nickc@redhat.com>
 335
 336         PR 20946
 337         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 338         could not be matched.
 339         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 340         NULL.
 341
 342 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 343
 344         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 345         (aarch64_opcode_table): Use RCPC_INSN.
 346
 347 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 348
 349         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 350         extension.
 351         * riscv-opcodes/all-opcodes: Likewise.
 352
 353 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 354
 355         * riscv-dis.c (print_insn_args): Add fall through comment.
 356
 357 2017-01-03  Nick Clifton  <nickc@redhat.com>
 358
 359         * po/sr.po: New Serbian translation.
 360         * configure.ac (ALL_LINGUAS): Add sr.
 361         * configure: Regenerate.
 362
 363 2017-01-02  Alan Modra  <amodra@gmail.com>
 364
 365         * epiphany-desc.h: Regenerate.
 366         * epiphany-opc.h: Regenerate.
 367         * fr30-desc.h: Regenerate.
 368         * fr30-opc.h: Regenerate.
 369         * frv-desc.h: Regenerate.
 370         * frv-opc.h: Regenerate.
 371         * ip2k-desc.h: Regenerate.
 372         * ip2k-opc.h: Regenerate.
 373         * iq2000-desc.h: Regenerate.
 374         * iq2000-opc.h: Regenerate.
 375         * lm32-desc.h: Regenerate.
 376         * lm32-opc.h: Regenerate.
 377         * m32c-desc.h: Regenerate.
 378         * m32c-opc.h: Regenerate.
 379         * m32r-desc.h: Regenerate.
 380         * m32r-opc.h: Regenerate.
 381         * mep-desc.h: Regenerate.
 382         * mep-opc.h: Regenerate.
 383         * mt-desc.h: Regenerate.
 384         * mt-opc.h: Regenerate.
 385         * or1k-desc.h: Regenerate.
 386         * or1k-opc.h: Regenerate.
 387         * xc16x-desc.h: Regenerate.
 388         * xc16x-opc.h: Regenerate.
 389         * xstormy16-desc.h: Regenerate.
 390         * xstormy16-opc.h: Regenerate.
 391
 392 2017-01-02  Alan Modra  <amodra@gmail.com>
 393
 394         Update year range in copyright notice of all files.
 395
 396 For older changes see ChangeLog-2016
 397 \f
 398 Copyright (C) 2017 Free Software Foundation, Inc.
 399
 400 Copying and distribution of this file, with or without modification,
 401 are permitted in any medium without royalty provided the copyright
 402 notice and this notice are preserved.
 403
 404 Local Variables:
 405 mode: change-log
 406 left-margin: 8
 407 fill-column: 74
 408 version-control: never
 409 End: