opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
   4         * i386-tbl.h: Re-generate.
   5
   6 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
   9         * i386-tbl.h: Re-generate.
  10
  11 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  14         * i386-tbl.h: Re-generate.
  15
  16 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  19         (vpbroadcastw, rdpid): Drop NoRex64.
  20         * i386-tbl.h: Re-generate.
  21
  22 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  25         store templates, adding D.
  26         * i386-tbl.h: Re-generate.
  27
  28 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  31         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  32         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  33         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  34         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  35         Fold load and store templates where possible, adding D. Drop
  36         IgnoreSize where it was pointlessly present. Drop redundant
  37         *word.
  38         * i386-tbl.h: Re-generate.
  39
  40 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  43         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  44         (intel_operand_size): Handle v_bndmk_mode.
  45         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  46
  47 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  48
  49         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  50
  51 2018-08-31  Kito Cheng  <kito@andestech.com>
  52
  53         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  54         compressed floating point instructions.
  55
  56 2018-08-30  Kito Cheng  <kito@andestech.com>
  57
  58         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  59         riscv_opcode.xlen_requirement.
  60         * riscv-opc.c (riscv_opcodes): Update for struct change.
  61
  62 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  63
  64         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  65         psr (PWRPSR) instruction.
  66
  67 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  68
  69         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  70
  71 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  72
  73         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  74
  75 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  76
  77         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  78         loongson3a as an alias of gs464 for compatibility.
  79         * mips-opc.c (mips_opcodes): Change Comments.
  80
  81 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  82
  83         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  84         option.
  85         (print_mips_disassembler_options): Document -M loongson-ext.
  86         * mips-opc.c (LEXT2): New macro.
  87         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  88
  89 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  90
  91          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  92          descriptors.
  93          (parse_mips_ase_option): Handle -M loongson-ext option.
  94          (print_mips_disassembler_options): Document -M loongson-ext.
  95          * mips-opc.c (IL3A): Delete.
  96          * mips-opc.c (LEXT): New macro.
  97          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
  98          instructions.
  99
 100 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 101
 102         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 103         descriptors.
 104         (parse_mips_ase_option): Handle -M loongson-cam option.
 105         (print_mips_disassembler_options): Document -M loongson-cam.
 106         * mips-opc.c (LCAM): New macro.
 107         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 108         instructions.
 109
 110 2018-08-21  Alan Modra  <amodra@gmail.com>
 111
 112         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 113         (skip_optional_operands): Count optional operands, and update
 114         ppc_optional_operand_value call.
 115         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 116         (extract_vlensi): Likewise.
 117         (extract_fxm): Return default value for missing optional operand.
 118         (extract_ls, extract_raq, extract_tbr): Likewise.
 119         (insert_sxl, extract_sxl): New functions.
 120         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 121         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 122         flag and extra entry.
 123         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 124         extract_sxl.
 125
 126 2018-08-20  Alan Modra  <amodra@gmail.com>
 127
 128         * sh-opc.h (MASK): Simplify.
 129
 130 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 131
 132         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 133         BM_RESERVED0 or BM_RESERVED1
 134         (bm_rel_decode, bm_n_bytes): Ditto.
 135
 136 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 137
 138         * s12z.h: Delete.
 139
 140 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 141
 142         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 143         address with the addr32 prefix and without base nor index
 144         registers.
 145
 146 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 149         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 150         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 151         (cpu_flags): Add CpuCMOV and CpuFXSR.
 152         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 153         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 154         * i386-init.h: Regenerated.
 155         * i386-tbl.h: Likewise.
 156
 157 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 158
 159         * arc-regs.h: Update auxiliary registers.
 160
 161 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 164         (RegIP, RegIZ): Define.
 165         * i386-reg.tbl: Adjust comments.
 166         (rip): Use Qword instead of BaseIndex. Use RegIP.
 167         (eip): Use Dword instead of BaseIndex. Use RegIP.
 168         (riz): Add Qword. Use RegIZ.
 169         (eiz): Add Dword. Use RegIZ.
 170         * i386-tbl.h: Re-generate.
 171
 172 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 175         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 176         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 177         * i386-tbl.h: Re-generate.
 178
 179 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-gen.c (operand_types): Remove Mem field.
 182         * i386-opc.h (union i386_operand_type): Remove mem field.
 183         * i386-init.h, i386-tbl.h: Re-generate.
 184
 185 2018-08-01  Alan Modra  <amodra@gmail.com>
 186
 187         * po/POTFILES.in: Regenerate.
 188
 189 2018-07-31  Nick Clifton  <nickc@redhat.com>
 190
 191         * po/sv.po: Updated Swedish translation.
 192
 193 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 196         * i386-init.h, i386-tbl.h: Re-generate.
 197
 198 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 199
 200         * i386-opc.h (ZEROING_MASKING) Rename to ...
 201         (DYNAMIC_MASKING): ... this. Adjust comment.
 202         * i386-opc.tbl (MaskingMorZ): Define.
 203         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 204         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 205         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 206         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 207         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 208         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 209         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 210         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 211         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 212
 213 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.tbl: Use element rather than vector size for AVX512*
 216         scatter/gather insns.
 217         * i386-tbl.h: Re-generate.
 218
 219 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 222         (cpu_flags): Drop CpuVREX.
 223         * i386-opc.h (CpuVREX): Delete.
 224         (union i386_cpu_flags): Remove cpuvrex.
 225         * i386-init.h, i386-tbl.h: Re-generate.
 226
 227 2018-07-30  Jim Wilson  <jimw@sifive.com>
 228
 229         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 230         fields.
 231         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 232
 233 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 234
 235         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 236         * Makefile.in: Regenerated.
 237         * configure.ac: Add C-SKY.
 238         * configure: Regenerated.
 239         * csky-dis.c: New file.
 240         * csky-opc.h: New file.
 241         * disassemble.c (ARCH_csky): Define.
 242         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 243         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 244
 245 2018-07-27  Alan Modra  <amodra@gmail.com>
 246
 247         * ppc-opc.c (insert_sprbat): Correct function parameter and
 248         return type.
 249         (extract_sprbat): Likewise, variable too.
 250
 251 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 252             Alan Modra  <amodra@gmail.com>
 253
 254         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 255         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 256         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 257         support disjointed BAT.
 258         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 259         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 260         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 261
 262 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 263             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 264
 265         * i386-gen.c (adjust_broadcast_modifier): New function.
 266         (process_i386_opcode_modifier): Add an argument for operands.
 267         Adjust the Broadcast value based on operands.
 268         (output_i386_opcode): Pass operand_types to
 269         process_i386_opcode_modifier.
 270         (process_i386_opcodes): Pass NULL as operands to
 271         process_i386_opcode_modifier.
 272         * i386-opc.h (BYTE_BROADCAST): New.
 273         (WORD_BROADCAST): Likewise.
 274         (DWORD_BROADCAST): Likewise.
 275         (QWORD_BROADCAST): Likewise.
 276         (i386_opcode_modifier): Expand broadcast to 3 bits.
 277         * i386-tbl.h: Regenerated.
 278
 279 2018-07-24  Alan Modra  <amodra@gmail.com>
 280
 281         PR 23430
 282         * or1k-desc.h: Regenerate.
 283
 284 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 287         vcvtusi2ss, and vcvtusi2sd.
 288         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 289         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 290         * i386-tbl.h: Re-generate.
 291
 292 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 293
 294         * arc-opc.c (extract_w6): Fix extending the sign.
 295
 296 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 297
 298         * arc-tbl.h (vewt): Allow it for ARC EM family.
 299
 300 2018-07-23  Alan Modra  <amodra@gmail.com>
 301
 302         PR 23419
 303         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 304         opcode variants for mtspr/mfspr encodings.
 305
 306 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 307             Maciej W. Rozycki  <macro@mips.com>
 308
 309         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 310         loongson3a descriptors.
 311         (parse_mips_ase_option): Handle -M loongson-mmi option.
 312         (print_mips_disassembler_options): Document -M loongson-mmi.
 313         * mips-opc.c (LMMI): New macro.
 314         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 315         instructions.
 316
 317 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 318
 319         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 320         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 321         IgnoreSize and [XYZ]MMword where applicable.
 322         * i386-tbl.h: Re-generate.
 323
 324 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 325
 326         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 327         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 328         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 329         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 330         * i386-tbl.h: Re-generate.
 331
 332 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 335         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 336         VPCLMULQDQ templates into their respective AVX512VL counterparts
 337         where possible, using Disp8ShiftVL and CheckRegSize instead of
 338         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 339         * i386-tbl.h: Re-generate.
 340
 341 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 344         AVX512VL counterparts where possible, using Disp8ShiftVL and
 345         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 346         IgnoreSize) as appropriate.
 347         * i386-tbl.h: Re-generate.
 348
 349 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-opc.tbl: Fold AVX512BW templates into their respective
 352         AVX512VL counterparts where possible, using Disp8ShiftVL and
 353         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 354         IgnoreSize) as appropriate.
 355         * i386-tbl.h: Re-generate.
 356
 357 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-opc.tbl: Fold AVX512CD templates into their respective
 360         AVX512VL counterparts where possible, using Disp8ShiftVL and
 361         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 362         IgnoreSize) as appropriate.
 363         * i386-tbl.h: Re-generate.
 364
 365 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.h (DISP8_SHIFT_VL): New.
 368         * i386-opc.tbl (Disp8ShiftVL):  Define.
 369         (various): Fold AVX512VL templates into their respective
 370         AVX512F counterparts where possible, using Disp8ShiftVL and
 371         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 372         IgnoreSize) as appropriate.
 373         * i386-tbl.h: Re-generate.
 374
 375 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 376
 377         * Makefile.am: Change dependencies and rule for
 378         $(srcdir)/i386-init.h.
 379         * Makefile.in: Re-generate.
 380         * i386-gen.c (process_i386_opcodes): New local variable
 381         "marker". Drop opening of input file. Recognize marker and line
 382         number directives.
 383         * i386-opc.tbl (OPCODE_I386_H): Define.
 384         (i386-opc.h): Include it.
 385         (None): Undefine.
 386
 387 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         PR gas/23418
 390         * i386-opc.h (Byte): Update comments.
 391         (Word): Likewise.
 392         (Dword): Likewise.
 393         (Fword): Likewise.
 394         (Qword): Likewise.
 395         (Tbyte): Likewise.
 396         (Xmmword): Likewise.
 397         (Ymmword): Likewise.
 398         (Zmmword): Likewise.
 399         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 400         vcvttps2uqq.
 401         * i386-tbl.h: Regenerated.
 402
 403 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 404
 405         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 406         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 407         * aarch64-asm-2.c: Regenerate.
 408         * aarch64-dis-2.c: Regenerate.
 409         * aarch64-opc-2.c: Regenerate.
 410
 411 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 412
 413         PR binutils/23192
 414         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 415         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 416         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 417         sqdmulh, sqrdmulh): Use Em16.
 418
 419 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 420
 421         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 422         csdb together with them.
 423         (thumb32_opcodes): Likewise.
 424
 425 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 428         requiring 32-bit registers as operands 2 and 3. Improve
 429         comments.
 430         (mwait, mwaitx): Fold templates. Improve comments.
 431         OPERAND_TYPE_INOUTPORTREG.
 432         * i386-tbl.h: Re-generate.
 433
 434 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 435
 436         * i386-gen.c (operand_type_init): Remove
 437         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 438         OPERAND_TYPE_INOUTPORTREG.
 439         * i386-init.h: Re-generate.
 440
 441 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 444         (wrssq, wrussq): Add Qword.
 445         * i386-tbl.h: Re-generate.
 446
 447 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.h: Rename OTMax to OTNum.
 450         (OTNumOfUints): Adjust calculation.
 451         (OTUnused): Directly alias to OTNum.
 452
 453 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 454
 455         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 456         `reg_xys'.
 457         (lea_reg_xys): Likewise.
 458         (print_insn_loop_primitive): Rename `reg' local variable to
 459         `reg_dxy'.
 460
 461 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 462
 463         PR binutils/23242
 464         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 465
 466 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 467
 468         PR binutils/23369
 469         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 470         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 471
 472 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 473
 474         PR tdep/8282
 475         * mips-dis.c (mips_option_arg_t): New enumeration.
 476         (mips_options): New variable.
 477         (disassembler_options_mips): New function.
 478         (print_mips_disassembler_options): Reimplement in terms of
 479         `disassembler_options_mips'.
 480         * arm-dis.c (disassembler_options_arm): Adapt to using the
 481         `disasm_options_and_args_t' structure.
 482         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 483         * s390-dis.c (disassembler_options_s390): Likewise.
 484
 485 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 486
 487         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 488         expected result.
 489         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 490         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 491         * testsuite/ld-arm/tls-longplt.d: Likewise.
 492
 493 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 494
 495         PR binutils/23192
 496         * aarch64-asm-2.c: Regenerate.
 497         * aarch64-dis-2.c: Likewise.
 498         * aarch64-opc-2.c: Likewise.
 499         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 500         * aarch64-opc.c (operand_general_constraint_met_p,
 501         aarch64_print_operand): Likewise.
 502         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 503         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 504         fmlal2, fmlsl2.
 505         (AARCH64_OPERANDS): Add Em2.
 506
 507 2018-06-26  Nick Clifton  <nickc@redhat.com>
 508
 509         * po/uk.po: Updated Ukranian translation.
 510         * po/de.po: Updated German translation.
 511         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 512
 513 2018-06-26  Nick Clifton  <nickc@redhat.com>
 514
 515         * nfp-dis.c: Fix spelling mistake.
 516
 517 2018-06-24  Nick Clifton  <nickc@redhat.com>
 518
 519         * configure: Regenerate.
 520         * po/opcodes.pot: Regenerate.
 521
 522 2018-06-24  Nick Clifton  <nickc@redhat.com>
 523
 524         2.31 branch created.
 525
 526 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 527
 528         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 529         * aarch64-asm-2.c: Regenerate.
 530         * aarch64-dis-2.c: Likewise.
 531
 532 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 533
 534         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 535         `-M ginv' option description.
 536
 537 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 538
 539         PR gas/23305
 540         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 541         la and lla.
 542
 543 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 544
 545         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 546         * configure.ac: Remove AC_PREREQ.
 547         * Makefile.in: Re-generate.
 548         * aclocal.m4: Re-generate.
 549         * configure: Re-generate.
 550
 551 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 552
 553         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 554         mips64r6 descriptors.
 555         (parse_mips_ase_option): Handle -Mginv option.
 556         (print_mips_disassembler_options): Document -Mginv.
 557         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 558         (GINV): New macro.
 559         (mips_opcodes): Define ginvi and ginvt.
 560
 561 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 562             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 563
 564         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 565         * mips-opc.c (CRC, CRC64): New macros.
 566         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 567         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 568         crc32cd for CRC64.
 569
 570 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 571
 572         PR 20319
 573         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 574         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 575
 576 2018-06-06  Alan Modra  <amodra@gmail.com>
 577
 578         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 579         setjmp.  Move init for some other vars later too.
 580
 581 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 582
 583         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 584         (dis_private): Add new fields for property section tracking.
 585         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 586         (xtensa_instruction_fits): New functions.
 587         (fetch_data): Bump minimal fetch size to 4.
 588         (print_insn_xtensa): Make struct dis_private static.
 589         Load and prepare property table on section change.
 590         Don't disassemble literals. Don't disassemble instructions that
 591         cross property table boundaries.
 592
 593 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * configure: Regenerated.
 596
 597 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 600         * i386-tbl.h: Re-generate.
 601
 602 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-opc.tbl (sldt, str): Add NoRex64.
 605         * i386-tbl.h: Re-generate.
 606
 607 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-opc.tbl (invpcid): Add Oword.
 610         * i386-tbl.h: Re-generate.
 611
 612 2018-06-01  Alan Modra  <amodra@gmail.com>
 613
 614         * sysdep.h (_bfd_error_handler): Don't declare.
 615         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 616         * rl78-decode.opc: Likewise.
 617         * msp430-decode.c: Regenerate.
 618         * rl78-decode.c: Regenerate.
 619
 620 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 621
 622         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 623         * i386-init.h : Regenerated.
 624
 625 2018-05-25  Alan Modra  <amodra@gmail.com>
 626
 627         * Makefile.in: Regenerate.
 628         * po/POTFILES.in: Regenerate.
 629
 630 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 631
 632         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 633         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 634         (insert_bab, extract_bab, insert_btab, extract_btab,
 635         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 636         (BAT, BBA VBA RBS XB6S): Delete macros.
 637         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 638         (BB, BD, RBX, XC6): Update for new macros.
 639         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 640         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 641         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 642         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 643
 644 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 645
 646         * Makefile.am: Add support for s12z architecture.
 647         * configure.ac: Likewise.
 648         * disassemble.c: Likewise.
 649         * disassemble.h: Likewise.
 650         * Makefile.in: Regenerate.
 651         * configure: Regenerate.
 652         * s12z-dis.c: New file.
 653         * s12z.h: New file.
 654
 655 2018-05-18  Alan Modra  <amodra@gmail.com>
 656
 657         * nfp-dis.c: Don't #include libbfd.h.
 658         (init_nfp3200_priv): Use bfd_get_section_contents.
 659         (nit_nfp6000_mecsr_sec): Likewise.
 660
 661 2018-05-17  Nick Clifton  <nickc@redhat.com>
 662
 663         * po/zh_CN.po: Updated simplified Chinese translation.
 664
 665 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 666
 667         PR binutils/23109
 668         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 669         * aarch64-dis-2.c: Regenerate.
 670
 671 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 672
 673         PR binutils/21446
 674         * aarch64-asm.c (opintl.h): Include.
 675         (aarch64_ins_sysreg): Enforce read/write constraints.
 676         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 677         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 678         (F_REG_READ, F_REG_WRITE): New.
 679         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 680         AARCH64_OPND_SYSREG.
 681         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 682         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 683         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 684         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 685         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 686         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 687         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 688         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 689         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 690         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 691         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 692         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 693         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 694         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 695         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 696         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 697         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 698
 699 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 700
 701         PR binutils/21446
 702         * aarch64-dis.c (no_notes: New.
 703         (parse_aarch64_dis_option): Support notes.
 704         (aarch64_decode_insn, print_operands): Likewise.
 705         (print_aarch64_disassembler_options): Document notes.
 706         * aarch64-opc.c (aarch64_print_operand): Support notes.
 707
 708 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 709
 710         PR binutils/21446
 711         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 712         and take error struct.
 713         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 714         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 715         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 716         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 717         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 718         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 719         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 720         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 721         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 722         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 723         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 724         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 725         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 726         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 727         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 728         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 729         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 730         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 731         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 732         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 733         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 734         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 735         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 736         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 737         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 738         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 739         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 740         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 741         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 742         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 743         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 744         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 745         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 746         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 747         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 748         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 749         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 750         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 751         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 752         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 753         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 754         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 755         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 756         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 757         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 758         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 759         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 760         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 761         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 762         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 763         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 764         (determine_disassembling_preference, aarch64_decode_insn,
 765         print_insn_aarch64_word, print_insn_data): Take errors struct.
 766         (print_insn_aarch64): Use errors.
 767         * aarch64-asm-2.c: Regenerate.
 768         * aarch64-dis-2.c: Regenerate.
 769         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 770         boolean in aarch64_insert_operan.
 771         (print_operand_extractor): Likewise.
 772         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 773
 774 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 775
 776         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 777
 778 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 779
 780         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 781
 782 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 783
 784         * cr16-opc.c (cr16_instruction): Comment typo fix.
 785         * hppa-dis.c (print_insn_hppa): Likewise.
 786
 787 2018-05-08  Jim Wilson  <jimw@sifive.com>
 788
 789         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 790         (match_c_slli64, match_srxi_as_c_srxi): New.
 791         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 792         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 793         <c.slli, c.srli, c.srai>: Use match_s_slli.
 794         <c.slli64, c.srli64, c.srai64>: New.
 795
 796 2018-05-08  Alan Modra  <amodra@gmail.com>
 797
 798         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 799         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 800         partition opcode space for index lookup.
 801
 802 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 803
 804         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 805         <insn_length>: ...with this.  Update usage.
 806         Remove duplicate call to *info->memory_error_func.
 807
 808 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 809             H.J. Lu  <hongjiu.lu@intel.com>
 810
 811         * i386-dis.c (Gva): New.
 812         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 813         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 814         (prefix_table): New instructions (see prefix above).
 815         (mod_table): New instructions (see prefix above).
 816         (OP_G): Handle va_mode.
 817         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 818         CPU_MOVDIR64B_FLAGS.
 819         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 820         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 821         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 822         * i386-opc.tbl: Add movidir{i,64b}.
 823         * i386-init.h: Regenerated.
 824         * i386-tbl.h: Likewise.
 825
 826 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 827
 828         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 829         AddrPrefixOpReg.
 830         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 831         (AddrPrefixOpReg): This.
 832         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 833         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 834
 835 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 836
 837         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 838         (vle_num_opcodes): Likewise.
 839         (spe2_num_opcodes): Likewise.
 840         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 841         initialization loop.
 842         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 843         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 844         only once.
 845
 846 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 847
 848         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 849
 850 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 851
 852         Makefile.am: Added nfp-dis.c.
 853         configure.ac: Added bfd_nfp_arch.
 854         disassemble.h: Added print_insn_nfp prototype.
 855         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 856         nfp-dis.c: New, for NFP support.
 857         po/POTFILES.in: Added nfp-dis.c to the list.
 858         Makefile.in: Regenerate.
 859         configure: Regenerate.
 860
 861 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 864         templates into their base ones.
 865         * i386-tlb.h: Re-generate.
 866
 867 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 870         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 871         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 872         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 873         * i386-init.h: Re-generate.
 874
 875 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 876
 877         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 878         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 879         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 880         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 881         comment.
 882         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 883         and CpuRegMask.
 884         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 885         CpuRegMask: Delete.
 886         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 887         cpuregzmm, and cpuregmask.
 888         * i386-init.h: Re-generate.
 889         * i386-tbl.h: Re-generate.
 890
 891 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 894         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 895         * i386-init.h: Re-generate.
 896
 897 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-gen.c (VexImmExt): Delete.
 900         * i386-opc.h (VexImmExt, veximmext): Delete.
 901         * i386-opc.tbl: Drop all VexImmExt uses.
 902         * i386-tlb.h: Re-generate.
 903
 904 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 907         register-only forms.
 908         * i386-tlb.h: Re-generate.
 909
 910 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 911
 912         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 913
 914 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 915
 916         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 917         PREFIX_0F1C.
 918         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 919         (cpu_flags): Add CpuCLDEMOTE.
 920         * i386-init.h: Regenerate.
 921         * i386-opc.h (enum): Add CpuCLDEMOTE,
 922         (i386_cpu_flags): Add cpucldemote.
 923         * i386-opc.tbl: Add cldemote.
 924         * i386-tbl.h: Regenerate.
 925
 926 2018-04-16  Alan Modra  <amodra@gmail.com>
 927
 928         * Makefile.am: Remove sh5 and sh64 support.
 929         * configure.ac: Likewise.
 930         * disassemble.c: Likewise.
 931         * disassemble.h: Likewise.
 932         * sh-dis.c: Likewise.
 933         * sh64-dis.c: Delete.
 934         * sh64-opc.c: Delete.
 935         * sh64-opc.h: Delete.
 936         * Makefile.in: Regenerate.
 937         * configure: Regenerate.
 938         * po/POTFILES.in: Regenerate.
 939
 940 2018-04-16  Alan Modra  <amodra@gmail.com>
 941
 942         * Makefile.am: Remove w65 support.
 943         * configure.ac: Likewise.
 944         * disassemble.c: Likewise.
 945         * disassemble.h: Likewise.
 946         * w65-dis.c: Delete.
 947         * w65-opc.h: Delete.
 948         * Makefile.in: Regenerate.
 949         * configure: Regenerate.
 950         * po/POTFILES.in: Regenerate.
 951
 952 2018-04-16  Alan Modra  <amodra@gmail.com>
 953
 954         * configure.ac: Remove we32k support.
 955         * configure: Regenerate.
 956
 957 2018-04-16  Alan Modra  <amodra@gmail.com>
 958
 959         * Makefile.am: Remove m88k support.
 960         * configure.ac: Likewise.
 961         * disassemble.c: Likewise.
 962         * disassemble.h: Likewise.
 963         * m88k-dis.c: Delete.
 964         * Makefile.in: Regenerate.
 965         * configure: Regenerate.
 966         * po/POTFILES.in: Regenerate.
 967
 968 2018-04-16  Alan Modra  <amodra@gmail.com>
 969
 970         * Makefile.am: Remove i370 support.
 971         * configure.ac: Likewise.
 972         * disassemble.c: Likewise.
 973         * disassemble.h: Likewise.
 974         * i370-dis.c: Delete.
 975         * i370-opc.c: Delete.
 976         * Makefile.in: Regenerate.
 977         * configure: Regenerate.
 978         * po/POTFILES.in: Regenerate.
 979
 980 2018-04-16  Alan Modra  <amodra@gmail.com>
 981
 982         * Makefile.am: Remove h8500 support.
 983         * configure.ac: Likewise.
 984         * disassemble.c: Likewise.
 985         * disassemble.h: Likewise.
 986         * h8500-dis.c: Delete.
 987         * h8500-opc.h: Delete.
 988         * Makefile.in: Regenerate.
 989         * configure: Regenerate.
 990         * po/POTFILES.in: Regenerate.
 991
 992 2018-04-16  Alan Modra  <amodra@gmail.com>
 993
 994         * configure.ac: Remove tahoe support.
 995         * configure: Regenerate.
 996
 997 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 998
 999         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1000         umwait.
1001         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1002         64-bit mode.
1003         * i386-tbl.h: Regenerated.
1004
1005 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1006
1007         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1008         PREFIX_MOD_1_0FAE_REG_6.
1009         (va_mode): New.
1010         (OP_E_register): Use va_mode.
1011         * i386-dis-evex.h (prefix_table):
1012         New instructions (see prefixes above).
1013         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1014         (cpu_flags): Likewise.
1015         * i386-opc.h (enum): Likewise.
1016         (i386_cpu_flags): Likewise.
1017         * i386-opc.tbl: Add umonitor, umwait, tpause.
1018         * i386-init.h: Regenerate.
1019         * i386-tbl.h: Likewise.
1020
1021 2018-04-11  Alan Modra  <amodra@gmail.com>
1022
1023         * opcodes/i860-dis.c: Delete.
1024         * opcodes/i960-dis.c: Delete.
1025         * Makefile.am: Remove i860 and i960 support.
1026         * configure.ac: Likewise.
1027         * disassemble.c: Likewise.
1028         * disassemble.h: Likewise.
1029         * Makefile.in: Regenerate.
1030         * configure: Regenerate.
1031         * po/POTFILES.in: Regenerate.
1032
1033 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1034
1035         PR binutils/23025
1036         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1037         to 0.
1038         (print_insn): Clear vex instead of vex.evex.
1039
1040 2018-04-04  Nick Clifton  <nickc@redhat.com>
1041
1042         * po/es.po: Updated Spanish translation.
1043
1044 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1045
1046         * i386-gen.c (opcode_modifiers): Delete VecESize.
1047         * i386-opc.h (VecESize): Delete.
1048         (struct i386_opcode_modifier): Delete vecesize.
1049         * i386-opc.tbl: Drop VecESize.
1050         * i386-tlb.h: Re-generate.
1051
1052 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1055         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1056         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1057         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1058         * i386-tlb.h: Re-generate.
1059
1060 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1061
1062         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1063         Fold AVX512 forms
1064         * i386-tlb.h: Re-generate.
1065
1066 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1069         (vex_len_table): Drop Y for vcvt*2si.
1070         (putop): Replace plain 'Y' handling by abort().
1071
1072 2018-03-28  Nick Clifton  <nickc@redhat.com>
1073
1074         PR 22988
1075         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1076         instructions with only a base address register.
1077         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1078         handle AARHC64_OPND_SVE_ADDR_R.
1079         (aarch64_print_operand): Likewise.
1080         * aarch64-asm-2.c: Regenerate.
1081         * aarch64_dis-2.c: Regenerate.
1082         * aarch64-opc-2.c: Regenerate.
1083
1084 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1085
1086         * i386-opc.tbl: Drop VecESize from register only insn forms and
1087         memory forms not allowing broadcast.
1088         * i386-tlb.h: Re-generate.
1089
1090 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1093         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1094         sha256*): Drop Disp<N>.
1095
1096 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1097
1098         * i386-dis.c (EbndS, bnd_swap_mode): New.
1099         (prefix_table): Use EbndS.
1100         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1101         * i386-opc.tbl (bndmov): Move misplaced Load.
1102         * i386-tlb.h: Re-generate.
1103
1104 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1107         templates allowing memory operands and folded ones for register
1108         only flavors.
1109         * i386-tlb.h: Re-generate.
1110
1111 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1114         256-bit templates. Drop redundant leftover Disp<N>.
1115         * i386-tlb.h: Re-generate.
1116
1117 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1118
1119         * riscv-opc.c (riscv_insn_types): New.
1120
1121 2018-03-13  Nick Clifton  <nickc@redhat.com>
1122
1123         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1124
1125 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1126
1127         * i386-opc.tbl: Add Optimize to clr.
1128         * i386-tbl.h: Regenerated.
1129
1130 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1131
1132         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1133         * i386-opc.h (OldGcc): Removed.
1134         (i386_opcode_modifier): Remove oldgcc.
1135         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1136         instructions for old (<= 2.8.1) versions of gcc.
1137         * i386-tbl.h: Regenerated.
1138
1139 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1140
1141         * i386-opc.h (EVEXDYN): New.
1142         * i386-opc.tbl: Fold various AVX512VL templates.
1143         * i386-tlb.h: Re-generate.
1144
1145 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1148         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1149         vpexpandd, vpexpandq): Fold AFX512VF templates.
1150         * i386-tlb.h: Re-generate.
1151
1152 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1153
1154         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1155         Fold 128- and 256-bit VEX-encoded templates.
1156         * i386-tlb.h: Re-generate.
1157
1158 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1159
1160         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1161         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1162         vpexpandd, vpexpandq): Fold AVX512F templates.
1163         * i386-tlb.h: Re-generate.
1164
1165 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1168         64-bit templates. Drop Disp<N>.
1169         * i386-tlb.h: Re-generate.
1170
1171 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1172
1173         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1174         and 256-bit templates.
1175         * i386-tlb.h: Re-generate.
1176
1177 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1180         * i386-tlb.h: Re-generate.
1181
1182 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1183
1184         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1185         Drop NoAVX.
1186         * i386-tlb.h: Re-generate.
1187
1188 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1191         * i386-tlb.h: Re-generate.
1192
1193 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1194
1195         * i386-gen.c (opcode_modifiers): Delete FloatD.
1196         * i386-opc.h (FloatD): Delete.
1197         (struct i386_opcode_modifier): Delete floatd.
1198         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1199         FloatD by D.
1200         * i386-tlb.h: Re-generate.
1201
1202 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1203
1204         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1205
1206 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1209         * i386-tlb.h: Re-generate.
1210
1211 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1212
1213         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1214         forms.
1215         * i386-tlb.h: Re-generate.
1216
1217 2018-03-07  Alan Modra  <amodra@gmail.com>
1218
1219         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1220         bfd_arch_rs6000.
1221         * disassemble.h (print_insn_rs6000): Delete.
1222         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1223         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1224         (print_insn_rs6000): Delete.
1225
1226 2018-03-03  Alan Modra  <amodra@gmail.com>
1227
1228         * sysdep.h (opcodes_error_handler): Define.
1229         (_bfd_error_handler): Declare.
1230         * Makefile.am: Remove stray #.
1231         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1232         EDIT" comment.
1233         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1234         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1235         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1236         opcodes_error_handler to print errors.  Standardize error messages.
1237         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1238         and include opintl.h.
1239         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1240         * i386-gen.c: Standardize error messages.
1241         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1242         * Makefile.in: Regenerate.
1243         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1244         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1245         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1246         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1247         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1248         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1249         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1250         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1251         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1252         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1253         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1254         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1255         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1256
1257 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1258
1259         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1260         vpsub[bwdq] instructions.
1261         * i386-tbl.h: Regenerated.
1262
1263 2018-03-01  Alan Modra  <amodra@gmail.com>
1264
1265         * configure.ac (ALL_LINGUAS): Sort.
1266         * configure: Regenerate.
1267
1268 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1269
1270         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1271         macro by assignements.
1272
1273 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1274
1275         PR gas/22871
1276         * i386-gen.c (opcode_modifiers): Add Optimize.
1277         * i386-opc.h (Optimize): New enum.
1278         (i386_opcode_modifier): Add optimize.
1279         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1280         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1281         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1282         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1283         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1284         vpxord and vpxorq.
1285         * i386-tbl.h: Regenerated.
1286
1287 2018-02-26  Alan Modra  <amodra@gmail.com>
1288
1289         * crx-dis.c (getregliststring): Allocate a large enough buffer
1290         to silence false positive gcc8 warning.
1291
1292 2018-02-22  Shea Levy <shea@shealevy.com>
1293
1294         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1295
1296 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1297
1298         * i386-opc.tbl: Add {rex},
1299         * i386-tbl.h: Regenerated.
1300
1301 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1302
1303         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1304         (mips16_opcodes): Replace `M' with `m' for "restore".
1305
1306 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1307
1308         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1309
1310 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1311
1312         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1313         variable to `function_index'.
1314
1315 2018-02-13  Nick Clifton  <nickc@redhat.com>
1316
1317         PR 22823
1318         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1319         about truncation of printing.
1320
1321 2018-02-12  Henry Wong <henry@stuffedcow.net>
1322
1323         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1324
1325 2018-02-05  Nick Clifton  <nickc@redhat.com>
1326
1327         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1328
1329 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1330
1331         * i386-dis.c (enum): Add pconfig.
1332         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1333         (cpu_flags): Add CpuPCONFIG.
1334         * i386-opc.h (enum): Add CpuPCONFIG.
1335         (i386_cpu_flags): Add cpupconfig.
1336         * i386-opc.tbl: Add PCONFIG instruction.
1337         * i386-init.h: Regenerate.
1338         * i386-tbl.h: Likewise.
1339
1340 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1341
1342         * i386-dis.c (enum): Add PREFIX_0F09.
1343         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1344         (cpu_flags): Add CpuWBNOINVD.
1345         * i386-opc.h (enum): Add CpuWBNOINVD.
1346         (i386_cpu_flags): Add cpuwbnoinvd.
1347         * i386-opc.tbl: Add WBNOINVD instruction.
1348         * i386-init.h: Regenerate.
1349         * i386-tbl.h: Likewise.
1350
1351 2018-01-17  Jim Wilson  <jimw@sifive.com>
1352
1353         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1354
1355 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1356
1357         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1358         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1359         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1360         (cpu_flags): Add CpuIBT, CpuSHSTK.
1361         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1362         (i386_cpu_flags): Add cpuibt, cpushstk.
1363         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1364         * i386-init.h: Regenerate.
1365         * i386-tbl.h: Likewise.
1366
1367 2018-01-16  Nick Clifton  <nickc@redhat.com>
1368
1369         * po/pt_BR.po: Updated Brazilian Portugese translation.
1370         * po/de.po: Updated German translation.
1371
1372 2018-01-15  Jim Wilson  <jimw@sifive.com>
1373
1374         * riscv-opc.c (match_c_nop): New.
1375         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1376
1377 2018-01-15  Nick Clifton  <nickc@redhat.com>
1378
1379         * po/uk.po: Updated Ukranian translation.
1380
1381 2018-01-13  Nick Clifton  <nickc@redhat.com>
1382
1383         * po/opcodes.pot: Regenerated.
1384
1385 2018-01-13  Nick Clifton  <nickc@redhat.com>
1386
1387         * configure: Regenerate.
1388
1389 2018-01-13  Nick Clifton  <nickc@redhat.com>
1390
1391         2.30 branch created.
1392
1393 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1394
1395         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1396         * i386-tbl.h: Regenerate.
1397
1398 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1399
1400         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1401         * i386-tbl.h: Re-generate.
1402
1403 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1404
1405         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1406         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1407         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1408         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1409         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1410         Disp8MemShift of AVX512VL forms.
1411         * i386-tbl.h: Re-generate.
1412
1413 2018-01-09  Jim Wilson  <jimw@sifive.com>
1414
1415         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1416         then the hi_addr value is zero.
1417
1418 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1419
1420         * arm-dis.c (arm_opcodes): Add csdb.
1421         (thumb32_opcodes): Add csdb.
1422
1423 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1424
1425         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1426         * aarch64-asm-2.c: Regenerate.
1427         * aarch64-dis-2.c: Regenerate.
1428         * aarch64-opc-2.c: Regenerate.
1429
1430 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         PR gas/22681
1433         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1434         Remove AVX512 vmovd with 64-bit operands.
1435         * i386-tbl.h: Regenerated.
1436
1437 2018-01-05  Jim Wilson  <jimw@sifive.com>
1438
1439         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1440         jalr.
1441
1442 2018-01-03  Alan Modra  <amodra@gmail.com>
1443
1444         Update year range in copyright notice of all files.
1445
1446 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1447
1448         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1449         and OPERAND_TYPE_REGZMM entries.
1450
1451 For older changes see ChangeLog-2017
1452 \f
1453 Copyright (C) 2018 Free Software Foundation, Inc.
1454
1455 Copying and distribution of this file, with or without modification,
1456 are permitted in any medium without royalty provided the copyright
1457 notice and this notice are preserved.
1458
1459 Local Variables:
1460 mode: change-log
1461 left-margin: 8
1462 fill-column: 74
1463 version-control: never
1464 End: