opcodes/ChangeLog

   1 2016-12-29  Yao Qi  <yao.qi@linaro.org>
   2
   3         * avr-dis.c: Include "bfd_stdint.h"
   4         (avrdis_opcode): Change return type to int, add argument
   5         insn.  Set *INSN on success.
   6         (print_insn_avr): Check return value of avrdis_opcode, and
   7         return -1 on error.
   8
   9 2016-12-28  Alan Modra  <amodra@gmail.com>
  10
  11         * configure.ac: Revert 2016-12-23.
  12         * Makefile.am: Likewise.
  13         (MIPS_DEFS): Define.
  14         (mips-dis.lo): Add rule.
  15         * Makefile.in: Regenerate.
  16         * aclocal.m4: Regenerate.
  17         * config.in: Regenerate.
  18         * configure: Regenerate.
  19
  20 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  21
  22         * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
  23         `4' and `s' operand codes.
  24         (mips16_opcodes): Add "asmacro" entry.
  25
  26 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * mips-dis.c (print_mips16_insn_arg): Simplify processing of
  29         extended operands.
  30         * mips16-opc.c (decode_mips16_operand): Switch the extended
  31         form of the `<' operand type to LSB position 22.
  32
  33 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  34
  35         * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
  36         operand codes with `.' and `F' respectively.
  37         (mips16_opcodes): Likewise.
  38
  39 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  40
  41         * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
  42         matching for INSN2_SHORT_ONLY opcode table entries.
  43         * mips16-opc.c (SH): New macro.
  44         (mips16_opcodes): Set SH in `pinfo2' for non-extensible
  45         instruction entries: "nop", "addu", "and", "break", "cmp",
  46         "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
  47         "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
  48         "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
  49         "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
  50         "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
  51         "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
  52         "seh", "sew", "zeb", "zeh", "zew" and "extend".
  53
  54 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  55
  56         * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
  57         encoding support.
  58
  59 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  60
  61         * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
  62         "extend".
  63
  64 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  65
  66         * mips-dis.c (set_default_mips_dis_options): Use
  67         HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
  68         call to `bfd_mips_elf_get_abiflags'.
  69         * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
  70         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
  71         * aclocal.m4: Regenerate.
  72         * configure: Regenerate.
  73         * config.in: Regenerate.
  74         * Makefile.in: Regenerate.
  75
  76 2016-12-23  Tristan Gingold  <gingold@adacore.com>
  77
  78         * configure: Regenerate.
  79
  80 2016-12-23  Tristan Gingold  <gingold@adacore.com>
  81
  82         * po/opcodes.pot: Regenerate.
  83
  84 2016-12-21  Andrew Waterman  <andrew@sifive.com>
  85
  86         * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
  87
  88 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  89
  90         * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
  91         ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
  92         (print_insn_mips16): Check opcode entries for validity against
  93         the ISA level and ASE set selected.
  94
  95 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  96
  97         * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
  98         `insn' together, with `extend' as the high-order 16 bits.
  99         (match_kind): New enum.
 100         (print_insn_mips16): Rework for 32-bit instruction matching.
 101         Do not dump EXTEND prefixes here.
 102         * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
 103         Recode `match' and `mask' fields as 32-bit in absolute "jal" and
 104         "jalx" entries.
 105
 106 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
 107
 108         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
 109         than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
 110         INSN_MACRO entries.
 111
 112 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
 113
 114         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
 115         than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
 116         opcode).
 117
 118 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 119
 120         * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
 121         "*.aqrl".
 122
 123 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 124
 125         * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
 126         INSN_ALIAS.
 127
 128 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 129
 130         * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
 131         format.
 132
 133 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 134
 135         * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
 136         XLEN when none is provided.
 137
 138 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 139
 140         * riscv-opc.c: Formatting fixes.
 141
 142 2016-12-20  Alan Modra  <amodra@gmail.com>
 143
 144         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
 145         * Makefile.in: Regenerate.
 146         * po/POTFILES.in: Regenerate.
 147
 148 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
 149
 150         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
 151         Only examine ELF file structures here.
 152
 153 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
 154
 155         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
 156         `bfd_mips_elf_get_abiflags' here.
 157
 158 2016-12-16  Nick Clifton  <nickc@redhat.com>
 159
 160         * arm-dis.c (print_insn_thumb32): Fix compile time warning
 161         computing value_in_comment.
 162
 163 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 164
 165         * mips-dis.c (mips_convert_abiflags_ases): New function.
 166         (set_default_mips_dis_options): Also infer ASE flags from ELF
 167         file structures.
 168
 169 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 170
 171         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
 172         header flag interpretation code.
 173
 174 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 175
 176         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
 177         `pinfo2' with SP-relative "sd" entries.
 178
 179 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 180
 181         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
 182         compact jumps.
 183
 184 2016-12-13 Renlin Li <renlin.li@arm.com>
 185
 186         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
 187         qualifier.
 188         (operand_general_constraint_met_p): Remove case for CP_REG.
 189         (aarch64_print_operand): Print CRn, CRm operand using imm field.
 190         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
 191         (QL_SYSL): Likewise.
 192         (aarch64_opcode_table): Change CRn, CRm operand class and type.
 193         * aarch64-opc-2.c : Regenerate.
 194         * aarch64-asm-2.c : Likewise.
 195         * aarch64-dis-2.c : Likewise.
 196
 197 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 198
 199         * rx-dis.c: Include <setjmp.h>
 200         (struct private): New.
 201         (rx_get_byte): Check return value of read_memory_func, and
 202         call memory_error_func and OPCODES_SIGLONGJMP on error.
 203         (print_insn_rx): Call OPCODES_SIGSETJMP.
 204
 205 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 206
 207         * rl78-dis.c: Include <setjmp.h>.
 208         (struct private): New.
 209         (rl78_get_byte): Check return value of read_memory_func, and
 210         call memory_error_func and OPCODES_SIGLONGJMP on error.
 211         (print_insn_rl78_common): Call OPCODES_SIGJMP.
 212
 213 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 214
 215         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
 216
 217 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 218
 219         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
 220         than UINT.
 221
 222 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 223
 224         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
 225         to separate `extend' and its uninterpreted argument output.
 226         Separate hexadecimal halves of undecoded extended instructions
 227         output.
 228
 229 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 230
 231         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
 232         indentation space across.
 233
 234 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 235
 236         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 237         adjustment for PC-relative operations following MIPS16e compact
 238         jumps or undefined RR/J(AL)R(C) encodings.
 239
 240 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 241
 242         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 243         variable to `reglane_index'.
 244
 245 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 246
 247         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 248
 249 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 250
 251         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 252
 253 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 254
 255         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 256         members.
 257
 258 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 259
 260         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 261
 262 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 263
 264         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 265         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 266
 267 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 268
 269         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 270
 271 2016-12-01  Nick Clifton  <nickc@redhat.com>
 272
 273         PR binutils/20893
 274         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 275         opcode designator.
 276
 277 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 278
 279         * arc-opc.c (insert_ra_chk): New function.
 280         (insert_rb_chk): Likewise.
 281         (insert_rad): Update text error message.
 282         (insert_rcd): Likewise.
 283         (insert_rhv2): Likewise.
 284         (insert_r0): Likewise.
 285         (insert_r1): Likewise.
 286         (insert_r2): Likewise.
 287         (insert_r3): Likewise.
 288         (insert_sp): Likewise.
 289         (insert_gp): Likewise.
 290         (insert_pcl): Likewise.
 291         (insert_blink): Likewise.
 292         (insert_ilink1): Likewise.
 293         (insert_ilink2): Likewise.
 294         (insert_ras): Likewise.
 295         (insert_rbs): Likewise.
 296         (insert_rcs): Likewise.
 297         (insert_simm3s): Likewise.
 298         (insert_rrange): Likewise.
 299         (insert_fpel): Likewise.
 300         (insert_blinkel): Likewise.
 301         (insert_pcel): Likewise.
 302         (insert_nps_3bit_dst): Likewise.
 303         (insert_nps_3bit_dst_short): Likewise.
 304         (insert_nps_3bit_src2_short): Likewise.
 305         (insert_nps_bitop_size_2b): Likewise.
 306         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 307         (RA_CHK): Define.
 308         (RB): Adjust.
 309         (RB_CHK): Define.
 310         (RC): Adjust.
 311         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 312         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 313         Change first insn argument to check for LP_COUNT usage.
 314         (rem): Likewise.
 315         (ld, ldd): All instructions are LOAD class.  Change first insn
 316         argument to check for LP_COUNT usage.
 317         (st, std): All instructions are STORE class.
 318         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 319         Change first insn argument to check for LP_COUNT usage.
 320         (mov): All instructions are MOVE class.  Change first insn
 321         argument to check for LP_COUNT usage.
 322
 323 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 324
 325         * arc-dis.c (is_compatible_p): Remove function.
 326         (skip_this_opcode): Don't add any decoding class to decode list.
 327         Remove warning.
 328         (find_format_from_table): Go through all opcodes, and warn if we
 329         use a guessed mnemonic.
 330
 331 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 332             Amit Pawar  <amit.pawar@amd.com>
 333
 334         PR binutils/20637
 335         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 336         instructions.
 337
 338 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 339
 340         * configure: Regenerate.
 341
 342 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 343
 344         * sparc-opc.c (HWS_V8): Definition moved from
 345         gas/config/tc-sparc.c.
 346         (HWS_V9): Likewise.
 347         (HWS_VA): Likewise.
 348         (HWS_VB): Likewise.
 349         (HWS_VC): Likewise.
 350         (HWS_VD): Likewise.
 351         (HWS_VE): Likewise.
 352         (HWS_VV): Likewise.
 353         (HWS_VM): Likewise.
 354         (HWS2_VM): Likewise.
 355         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 356         existing entries.
 357
 358 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 359
 360         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 361         instructions.
 362
 363 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 364
 365         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 366         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 367         (aarch64_opcode_table): Add fcmla and fcadd.
 368         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 369         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 370         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 371         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 372         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 373         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 374         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 375         (operand_general_constraint_met_p): Rotate and index range check.
 376         (aarch64_print_operand): Handle rotate operand.
 377         * aarch64-asm-2.c: Regenerate.
 378         * aarch64-dis-2.c: Likewise.
 379         * aarch64-opc-2.c: Likewise.
 380
 381 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 382
 383         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 384         * aarch64-asm-2.c: Regenerate.
 385         * aarch64-dis-2.c: Regenerate.
 386         * aarch64-opc-2.c: Regenerate.
 387
 388 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 389
 390         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 391         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 392         * aarch64-asm-2.c: Regenerate.
 393         * aarch64-dis-2.c: Regenerate.
 394         * aarch64-opc-2.c: Regenerate.
 395
 396 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 397
 398         * aarch64-tbl.h (QL_X1NIL): New.
 399         (arch64_opcode_table): Add ldraa, ldrab.
 400         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 401         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 402         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 403         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 404         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 405         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 406         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 407         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 408         (aarch64_print_operand): Likewise.
 409         * aarch64-asm-2.c: Regenerate.
 410         * aarch64-dis-2.c: Regenerate.
 411         * aarch64-opc-2.c: Regenerate.
 412
 413 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 414
 415         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 416         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 417         * aarch64-asm-2.c: Regenerate.
 418         * aarch64-dis-2.c: Regenerate.
 419         * aarch64-opc-2.c: Regenerate.
 420
 421 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 422
 423         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 424         (AARCH64_OPERANDS): Add Rm_SP.
 425         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 426         * aarch64-asm-2.c: Regenerate.
 427         * aarch64-dis-2.c: Regenerate.
 428         * aarch64-opc-2.c: Regenerate.
 429
 430 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 431
 432         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 433         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 434         autdzb, xpaci, xpacd.
 435         * aarch64-asm-2.c: Regenerate.
 436         * aarch64-dis-2.c: Regenerate.
 437         * aarch64-opc-2.c: Regenerate.
 438
 439 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 440
 441         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 442         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 443         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 444         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 445
 446 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 447
 448         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 449         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 450         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 451         autibsp.
 452         * aarch64-asm-2.c: Regenerate.
 453         * aarch64-dis-2.c: Regenerate.
 454
 455 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 456
 457         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 458
 459 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         PR binutils/20799
 462         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 463         * i386-dis.c (EdqwS): Removed.
 464         (dqw_swap_mode): Likewise.
 465         (intel_operand_size): Don't check dqw_swap_mode.
 466         (OP_E_register): Likewise.
 467         (OP_E_memory): Likewise.
 468         (OP_G): Likewise.
 469         (OP_EX): Likewise.
 470         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 471         * i386-tbl.h: Regerated.
 472
 473 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         * i386-opc.tbl: Merge AVX512F vmovq.
 476         * i386-tbl.h: Regerated.
 477
 478 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         PR binutils/20701
 481         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 482         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 483         (three_byte_table): Remove THREE_BYTE_0F7A.
 484
 485 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         PR binutils/20775
 488         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 489         (FGRPd9_4): Replace 1 with 2.
 490         (FGRPd9_5): Replace 2 with 3.
 491         (FGRPd9_6): Replace 3 with 4.
 492         (FGRPd9_7): Replace 4 with 5.
 493         (FGRPda_5): Replace 5 with 6.
 494         (FGRPdb_4): Replace 6 with 7.
 495         (FGRPde_3): Replace 7 with 8.
 496         (FGRPdf_4): Replace 8 with 9.
 497         (fgrps): Add an entry for Bad_Opcode.
 498
 499 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 500
 501         * arc-opc.c (arc_flag_operands): Add F_DI14.
 502         (arc_flag_classes): Add C_DI14.
 503         * arc-nps400-tbl.h: Add new exc instructions.
 504
 505 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 506
 507         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 508         major opcode 0xa.
 509         * arc-nps-400-tbl.h: Add dcmac instruction.
 510         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 511         (insert_nps_rbdouble_64): Added.
 512         (extract_nps_rbdouble_64): Added.
 513         (insert_nps_proto_size): Added.
 514         (extract_nps_proto_size): Added.
 515
 516 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 517
 518         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 519         relating to long instruction processing, add new limm field.
 520         (OPCODE): Rename to...
 521         (OPCODE_32BIT_INSN): ...this.
 522         (OPCODE_AC): Delete.
 523         (skip_this_opcode): Handle different instruction lengths, update
 524         macro name.
 525         (special_flag_p): Update parameter type.
 526         (find_format_from_table): Update for more instruction lengths.
 527         (find_format_long_instructions): Delete.
 528         (find_format): Update for more instruction lengths.
 529         (arc_insn_length): Likewise.
 530         (extract_operand_value): Update for more instruction lengths.
 531         (operand_iterator_next): Remove code relating to long
 532         instructions.
 533         (arc_opcode_to_insn_type): New function.
 534         (print_insn_arc):Update for more instructions lengths.
 535         * arc-ext.c (extInstruction_t): Change argument type.
 536         * arc-ext.h (extInstruction_t): Change argument type.
 537         * arc-fxi.h: Change type unsigned to unsigned long long
 538         extensively throughout.
 539         * arc-nps400-tbl.h: Add long instructions taken from
 540         arc_long_opcodes table in arc-opc.c.
 541         * arc-opc.c: Update parameter types on insert/extract handlers.
 542         (arc_long_opcodes): Delete.
 543         (arc_num_long_opcodes): Delete.
 544         (arc_opcode_len): Update for more instruction lengths.
 545
 546 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 547
 548         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 549
 550 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 551
 552         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 553         with arc_opcode_len.
 554         (find_format_long_instructions): Likewise.
 555         * arc-opc.c (arc_opcode_len): New function.
 556
 557 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 558
 559         * arc-nps400-tbl.h: Fix some instruction masks.
 560
 561 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386-dis.c (REG_82): Removed.
 564         (X86_64_82_REG_0): Likewise.
 565         (X86_64_82_REG_1): Likewise.
 566         (X86_64_82_REG_2): Likewise.
 567         (X86_64_82_REG_3): Likewise.
 568         (X86_64_82_REG_4): Likewise.
 569         (X86_64_82_REG_5): Likewise.
 570         (X86_64_82_REG_6): Likewise.
 571         (X86_64_82_REG_7): Likewise.
 572         (X86_64_82): New.
 573         (dis386): Use X86_64_82 instead of REG_82.
 574         (reg_table): Remove REG_82.
 575         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 576         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 577         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 578         X86_64_82_REG_7.
 579
 580 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         PR binutils/20754
 583         * i386-dis.c (REG_82): New.
 584         (X86_64_82_REG_0): Likewise.
 585         (X86_64_82_REG_1): Likewise.
 586         (X86_64_82_REG_2): Likewise.
 587         (X86_64_82_REG_3): Likewise.
 588         (X86_64_82_REG_4): Likewise.
 589         (X86_64_82_REG_5): Likewise.
 590         (X86_64_82_REG_6): Likewise.
 591         (X86_64_82_REG_7): Likewise.
 592         (dis386): Use REG_82.
 593         (reg_table): Add REG_82.
 594         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 595         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 596         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 597
 598 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         * i386-dis.c (REG_82): Renamed to ...
 601         (REG_83): This.
 602         (dis386): Updated.
 603         (reg_table): Likewise.
 604
 605 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 606
 607         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 608         * i386-dis-evex.h (evex_table): Updated.
 609         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 610         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 611         (cpu_flags): Add CpuAVX512_4VNNIW.
 612         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 613         (i386_cpu_flags): Add cpuavx512_4vnniw.
 614         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 615         * i386-init.h: Regenerate.
 616         * i386-tbl.h: Ditto.
 617
 618 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 619
 620         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 621         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 622         * i386-dis-evex.h (evex_table): Updated.
 623         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 624         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 625         (cpu_flags): Add CpuAVX512_4FMAPS.
 626         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 627         * i386-opc.h (AVX512_4FMAP): New.
 628         (i386_cpu_flags): Add cpuavx512_4fmaps.
 629         (ImplicitQuadGroup): New.
 630         (i386_opcode_modifier): Add implicitquadgroup.
 631         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 632         * i386-init.h: Regenerate.
 633         * i386-tbl.h: Ditto.
 634
 635 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 636             Andrew Waterman <andrew@sifive.com>
 637
 638         Add support for RISC-V architecture.
 639         * configure.ac: Add entry for bfd_riscv_arch.
 640         * configure: Regenerate.
 641         * disassemble.c (disassembler): Add support for riscv.
 642         (disassembler_usage): Likewise.
 643         * riscv-dis.c: New file.
 644         * riscv-opc.c: New file.
 645
 646 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 647
 648         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 649         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 650         (rm_table): Update the RM_0FAE_REG_7 entry.
 651         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 652         (cpu_flags): Remove CpuPCOMMIT.
 653         * i386-opc.h (CpuPCOMMIT): Removed.
 654         (i386_cpu_flags): Remove cpupcommit.
 655         * i386-opc.tbl: Remove pcommit.
 656         * i386-init.h: Regenerated.
 657         * i386-tbl.h: Likewise.
 658
 659 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 660
 661         PR binutis/20705
 662         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 663         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 664         32-bit mode.  Don't check vex.register_specifier in 32-bit
 665         mode.
 666         (OP_VEX): Check for invalid mask registers.
 667
 668 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         PR binutis/20699
 671         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 672         sizeflag.
 673
 674 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 675
 676         PR binutis/20704
 677         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 678
 679 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 680
 681         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 682         local variable to `index_regno'.
 683
 684 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 685
 686         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 687
 688 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 689
 690         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 691         usage on ISA basis.
 692
 693 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 694
 695         PR target/20666
 696         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 697
 698 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 699
 700         PR target/20667
 701         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 702         available.
 703
 704 2016-10-07  Alan Modra  <amodra@gmail.com>
 705
 706         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 707
 708 2016-10-06  Alan Modra  <amodra@gmail.com>
 709
 710         * aarch64-opc.c: Spell fall through comments consistently.
 711         * i386-dis.c: Likewise.
 712         * aarch64-dis.c: Add missing fall through comments.
 713         * aarch64-opc.c: Likewise.
 714         * arc-dis.c: Likewise.
 715         * arm-dis.c: Likewise.
 716         * i386-dis.c: Likewise.
 717         * m68k-dis.c: Likewise.
 718         * mep-asm.c: Likewise.
 719         * ns32k-dis.c: Likewise.
 720         * sh-dis.c: Likewise.
 721         * tic4x-dis.c: Likewise.
 722         * tic6x-dis.c: Likewise.
 723         * vax-dis.c: Likewise.
 724
 725 2016-10-06  Alan Modra  <amodra@gmail.com>
 726
 727         * arc-ext.c (create_map): Add missing break.
 728         * msp430-decode.opc (encode_as): Likewise.
 729         * msp430-decode.c: Regenerate.
 730
 731 2016-10-06  Alan Modra  <amodra@gmail.com>
 732
 733         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 734         * crx-dis.c (print_insn_crx): Likewise.
 735
 736 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         PR binutils/20657
 739         * i386-dis.c (putop): Don't assign alt twice.
 740
 741 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 742
 743         PR target/20553
 744         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 745
 746 2016-09-29  Alan Modra  <amodra@gmail.com>
 747
 748         * ppc-opc.c (L): Make compulsory.
 749         (LOPT): New, optional form of L.
 750         (HTM_R): Define as LOPT.
 751         (L0, L1): Delete.
 752         (L32OPT): New, optional for 32-bit L.
 753         (L2OPT): New, 2-bit L for dcbf.
 754         (SVC_LEC): Update.
 755         (L2): Define.
 756         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 757         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 758         <dcbf>: Use L2OPT.
 759         <tlbiel, tlbie>: Use LOPT.
 760         <wclr, wclrall>: Use L2.
 761
 762 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 763
 764         * Makefile.in: Regenerate.
 765         * configure: Likewise.
 766
 767 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 768
 769         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 770         (EXTINSN2OP): Use EXTINSN2OPF.
 771         (bspeekm, bspop, modapp): New extension instructions.
 772         * arc-opc.c (F_DNZ_ND): Define.
 773         (F_DNZ_D): Likewise.
 774         (F_SIZEB1): Changed.
 775         (C_DNZ_D): Define.
 776         (C_HARD): Changed.
 777         * arc-tbl.h (dbnz): New instruction.
 778         (prealloc): Allow it for ARC EM.
 779         (xbfu): Likewise.
 780
 781 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 782
 783         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 784         after commas in addresses.
 785         (aarch64_print_operand): Likewise.
 786
 787 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 788
 789         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 790         rather than "should be" or "expected to be" in error messages.
 791
 792 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 793
 794         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 795         (print_mnemonic_name): ...here.
 796         (print_comment): New function.
 797         (print_aarch64_insn): Call it.
 798         * aarch64-opc.c (aarch64_conds): Add SVE names.
 799         (aarch64_print_operand): Print alternative condition names in
 800         a comment.
 801
 802 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 803
 804         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 805         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 806         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 807         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 808         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 809         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 810         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 811         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 812         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 813         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 814         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 815         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 816         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 817         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 818         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 819         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 820         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 821         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 822         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 823         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 824         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 825         (aarch64_feature_sve): New variable.
 826         (SVE): New macro.
 827         (_SVE_INSN): Likewise.
 828         (aarch64_opcode_table): Add SVE instructions.
 829         * aarch64-opc.h (extract_fields): Declare.
 830         * aarch64-opc-2.c: Regenerate.
 831         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 832         * aarch64-asm-2.c: Regenerate.
 833         * aarch64-dis.c (extract_fields): Make global.
 834         (do_misc_decoding): Handle the new SVE aarch64_ops.
 835         * aarch64-dis-2.c: Regenerate.
 836
 837 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 838
 839         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 840         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 841         aarch64_field_kinds.
 842         * aarch64-opc.c (fields): Add corresponding entries.
 843         * aarch64-asm.c (aarch64_get_variant): New function.
 844         (aarch64_encode_variant_using_iclass): Likewise.
 845         (aarch64_opcode_encode): Call it.
 846         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 847         (aarch64_opcode_decode): Call it.
 848
 849 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 850
 851         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 852         and FP register operands.
 853         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 854         (FLD_SVE_Vn): New aarch64_field_kinds.
 855         * aarch64-opc.c (fields): Add corresponding entries.
 856         (aarch64_print_operand): Handle the new SVE core and FP register
 857         operands.
 858         * aarch64-opc-2.c: Regenerate.
 859         * aarch64-asm-2.c: Likewise.
 860         * aarch64-dis-2.c: Likewise.
 861
 862 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 863
 864         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 865         immediate operands.
 866         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 867         * aarch64-opc.c (fields): Add corresponding entry.
 868         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 869         operands.
 870         (aarch64_print_operand): Likewise.
 871         * aarch64-opc-2.c: Regenerate.
 872         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 873         (ins_sve_float_zero_one): New inserters.
 874         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 875         (aarch64_ins_sve_float_half_two): Likewise.
 876         (aarch64_ins_sve_float_zero_one): Likewise.
 877         * aarch64-asm-2.c: Regenerate.
 878         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 879         (ext_sve_float_zero_one): New extractors.
 880         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 881         (aarch64_ext_sve_float_half_two): Likewise.
 882         (aarch64_ext_sve_float_zero_one): Likewise.
 883         * aarch64-dis-2.c: Regenerate.
 884
 885 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 886
 887         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 888         integer immediate operands.
 889         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 890         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 891         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 892         * aarch64-opc.c (fields): Add corresponding entries.
 893         (operand_general_constraint_met_p): Handle the new SVE integer
 894         immediate operands.
 895         (aarch64_print_operand): Likewise.
 896         (aarch64_sve_dupm_mov_immediate_p): New function.
 897         * aarch64-opc-2.c: Regenerate.
 898         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 899         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 900         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 901         (aarch64_ins_limm): ...here.
 902         (aarch64_ins_inv_limm): New function.
 903         (aarch64_ins_sve_aimm): Likewise.
 904         (aarch64_ins_sve_asimm): Likewise.
 905         (aarch64_ins_sve_limm_mov): Likewise.
 906         (aarch64_ins_sve_shlimm): Likewise.
 907         (aarch64_ins_sve_shrimm): Likewise.
 908         * aarch64-asm-2.c: Regenerate.
 909         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 910         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 911         * aarch64-dis.c (decode_limm): New function, split out from...
 912         (aarch64_ext_limm): ...here.
 913         (aarch64_ext_inv_limm): New function.
 914         (decode_sve_aimm): Likewise.
 915         (aarch64_ext_sve_aimm): Likewise.
 916         (aarch64_ext_sve_asimm): Likewise.
 917         (aarch64_ext_sve_limm_mov): Likewise.
 918         (aarch64_top_bit): Likewise.
 919         (aarch64_ext_sve_shlimm): Likewise.
 920         (aarch64_ext_sve_shrimm): Likewise.
 921         * aarch64-dis-2.c: Regenerate.
 922
 923 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 924
 925         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 926         operands.
 927         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 928         the AARCH64_MOD_MUL_VL entry.
 929         (value_aligned_p): Cope with non-power-of-two alignments.
 930         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 931         (print_immediate_offset_address): Likewise.
 932         (aarch64_print_operand): Likewise.
 933         * aarch64-opc-2.c: Regenerate.
 934         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 935         (ins_sve_addr_ri_s9xvl): New inserters.
 936         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 937         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 938         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 939         * aarch64-asm-2.c: Regenerate.
 940         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 941         (ext_sve_addr_ri_s9xvl): New extractors.
 942         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 943         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 944         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 945         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 946         * aarch64-dis-2.c: Regenerate.
 947
 948 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 949
 950         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 951         address operands.
 952         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 953         (FLD_SVE_xs_22): New aarch64_field_kinds.
 954         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 955         (get_operand_specific_data): New function.
 956         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 957         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 958         (operand_general_constraint_met_p): Handle the new SVE address
 959         operands.
 960         (sve_reg): New array.
 961         (get_addr_sve_reg_name): New function.
 962         (aarch64_print_operand): Handle the new SVE address operands.
 963         * aarch64-opc-2.c: Regenerate.
 964         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 965         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 966         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 967         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 968         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 969         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 970         (aarch64_ins_sve_addr_zi_u5): Likewise.
 971         (aarch64_ins_sve_addr_zz): Likewise.
 972         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 973         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 974         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 975         * aarch64-asm-2.c: Regenerate.
 976         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 977         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 978         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 979         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 980         (aarch64_ext_sve_addr_ri_u6): Likewise.
 981         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 982         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 983         (aarch64_ext_sve_addr_zi_u5): Likewise.
 984         (aarch64_ext_sve_addr_zz): Likewise.
 985         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 986         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 987         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 988         * aarch64-dis-2.c: Regenerate.
 989
 990 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 991
 992         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 993         AARCH64_OPND_SVE_PATTERN_SCALED.
 994         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 995         * aarch64-opc.c (fields): Add a corresponding entry.
 996         (set_multiplier_out_of_range_error): New function.
 997         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 998         (operand_general_constraint_met_p): Handle
 999         AARCH64_OPND_SVE_PATTERN_SCALED.
1000         (print_register_offset_address): Use PRIi64 to print the
1001         shift amount.
1002         (aarch64_print_operand): Likewise.  Handle
1003         AARCH64_OPND_SVE_PATTERN_SCALED.
1004         * aarch64-opc-2.c: Regenerate.
1005         * aarch64-asm.h (ins_sve_scale): New inserter.
1006         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
1007         * aarch64-asm-2.c: Regenerate.
1008         * aarch64-dis.h (ext_sve_scale): New inserter.
1009         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
1010         * aarch64-dis-2.c: Regenerate.
1011
1012 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1013
1014         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
1015         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
1016         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
1017         (FLD_SVE_prfop): Likewise.
1018         * aarch64-opc.c: Include libiberty.h.
1019         (aarch64_sve_pattern_array): New variable.
1020         (aarch64_sve_prfop_array): Likewise.
1021         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
1022         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
1023         AARCH64_OPND_SVE_PRFOP.
1024         * aarch64-asm-2.c: Regenerate.
1025         * aarch64-dis-2.c: Likewise.
1026         * aarch64-opc-2.c: Likewise.
1027
1028 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1029
1030         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
1031         AARCH64_OPND_QLF_P_[ZM].
1032         (aarch64_print_operand): Print /z and /m where appropriate.
1033
1034 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1035
1036         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
1037         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
1038         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
1039         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
1040         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
1041         * aarch64-opc.c (fields): Add corresponding entries here.
1042         (operand_general_constraint_met_p): Check that SVE register lists
1043         have the correct length.  Check the ranges of SVE index registers.
1044         Check for cases where p8-p15 are used in 3-bit predicate fields.
1045         (aarch64_print_operand): Handle the new SVE operands.
1046         * aarch64-opc-2.c: Regenerate.
1047         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
1048         * aarch64-asm.c (aarch64_ins_sve_index): New function.
1049         (aarch64_ins_sve_reglist): Likewise.
1050         * aarch64-asm-2.c: Regenerate.
1051         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
1052         * aarch64-dis.c (aarch64_ext_sve_index): New function.
1053         (aarch64_ext_sve_reglist): Likewise.
1054         * aarch64-dis-2.c: Regenerate.
1055
1056 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1057
1058         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1059         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1060         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1061         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1062         tied operands.
1063
1064 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1065
1066         * aarch64-opc.c (get_offset_int_reg_name): New function.
1067         (print_immediate_offset_address): Likewise.
1068         (print_register_offset_address): Take the base and offset
1069         registers as parameters.
1070         (aarch64_print_operand): Update caller accordingly.  Use
1071         print_immediate_offset_address.
1072
1073 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1074
1075         * aarch64-opc.c (BANK): New macro.
1076         (R32, R64): Take a register number as argument
1077         (int_reg): Use BANK.
1078
1079 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1080
1081         * aarch64-opc.c (print_register_list): Add a prefix parameter.
1082         (aarch64_print_operand): Update accordingly.
1083
1084 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1085
1086         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1087         for FPIMM.
1088         * aarch64-asm.h (ins_fpimm): New inserter.
1089         * aarch64-asm.c (aarch64_ins_fpimm): New function.
1090         * aarch64-asm-2.c: Regenerate.
1091         * aarch64-dis.h (ext_fpimm): New extractor.
1092         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1093         (aarch64_ext_fpimm): New function.
1094         * aarch64-dis-2.c: Regenerate.
1095
1096 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1097
1098         * aarch64-asm.c: Include libiberty.h.
1099         (insert_fields): New function.
1100         (aarch64_ins_imm): Use it.
1101         * aarch64-dis.c (extract_fields): New function.
1102         (aarch64_ext_imm): Use it.
1103
1104 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1105
1106         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1107         with an esize parameter.
1108         (operand_general_constraint_met_p): Update accordingly.
1109         Fix misindented code.
1110         * aarch64-asm.c (aarch64_ins_limm): Update call to
1111         aarch64_logical_immediate_p.
1112
1113 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1114
1115         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1116
1117 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1118
1119         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1120
1121 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
1122
1123         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1124
1125 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
1126
1127         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1128         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1129         xor3>: Delete mnemonics.
1130         <cp_abort>: Rename mnemonic from ...
1131         <cpabort>: ...to this.
1132         <setb>: Change to a X form instruction.
1133         <sync>: Change to 1 operand form.
1134         <copy>: Delete mnemonic.
1135         <copy_first>: Rename mnemonic from ...
1136         <copy>: ...to this.
1137         <paste, paste.>: Delete mnemonics.
1138         <paste_last>: Rename mnemonic from ...
1139         <paste.>: ...to this.
1140
1141 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1142
1143         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1144
1145 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1146
1147         * s390-mkopc.c (main): Support alternate arch strings.
1148
1149 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1150
1151         * s390-opc.txt: Fix kmctr instruction type.
1152
1153 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1154
1155         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1156         * i386-init.h: Regenerated.
1157
1158 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1159
1160         * opcodes/arc-dis.c (print_insn_arc): Changed.
1161
1162 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1163
1164         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1165         camellia_fl.
1166
1167 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1168
1169         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1170         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1171         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1172
1173 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1174
1175         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1176         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1177         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1178         PREFIX_MOD_3_0FAE_REG_4.
1179         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1180         PREFIX_MOD_3_0FAE_REG_4.
1181         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1182         (cpu_flags): Add CpuPTWRITE.
1183         * i386-opc.h (CpuPTWRITE): New.
1184         (i386_cpu_flags): Add cpuptwrite.
1185         * i386-opc.tbl: Add ptwrite instruction.
1186         * i386-init.h: Regenerated.
1187         * i386-tbl.h: Likewise.
1188
1189 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1190
1191         * arc-dis.h: Wrap around in extern "C".
1192
1193 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1194
1195         * aarch64-tbl.h (V8_2_INSN): New macro.
1196         (aarch64_opcode_table): Use it.
1197
1198 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1199
1200         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1201         CORE_INSN, __FP_INSN and SIMD_INSN.
1202
1203 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1204
1205         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1206         (aarch64_opcode_table): Update uses accordingly.
1207
1208 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1209         Kwok Cheung Yeung  <kcy@codesourcery.com>
1210
1211         opcodes/
1212         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1213         'e_cmplwi' to 'e_cmpli' instead.
1214         (OPVUPRT, OPVUPRT_MASK): Define.
1215         (powerpc_opcodes): Add E200Z4 insns.
1216         (vle_opcodes): Add context save/restore insns.
1217
1218 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1219
1220         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1221         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1222         "j".
1223
1224 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1225
1226         * arc-nps400-tbl.h: Change block comments to GNU format.
1227         * arc-dis.c: Add new globals addrtypenames,
1228         addrtypenames_max, and addtypeunknown.
1229         (get_addrtype): New function.
1230         (print_insn_arc): Print colons and address types when
1231         required.
1232         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1233         define insert and extract functions for all address types.
1234         (arc_operands): Add operands for colon and all address
1235         types.
1236         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1237         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1238         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1239         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1240         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1241         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1242
1243 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1244
1245         * configure: Regenerated.
1246
1247 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1248
1249         * arc-dis.c (skipclass): New structure.
1250         (decodelist): New variable.
1251         (is_compatible_p): New function.
1252         (new_element): Likewise.
1253         (skip_class_p): Likewise.
1254         (find_format_from_table): Use skip_class_p function.
1255         (find_format): Decode first the extension instructions.
1256         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1257         e_flags.
1258         (parse_option): New function.
1259         (parse_disassembler_options): Likewise.
1260         (print_arc_disassembler_options): Likewise.
1261         (print_insn_arc): Use parse_disassembler_options function.  Proper
1262         select ARCv2 cpu variant.
1263         * disassemble.c (disassembler_usage): Add ARC disassembler
1264         options.
1265
1266 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1267
1268         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1269         annotation from the "nal" entry and reorder it beyond "bltzal".
1270
1271 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1272
1273         * sparc-opc.c (ldtxa): New macro.
1274         (sparc_opcodes): Use the macro defined above to add entries for
1275         the LDTXA instructions.
1276         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1277         instruction.
1278
1279 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1280
1281         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1282         and "jmpc".
1283
1284 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1285
1286         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1287         (movzb): Adjust to cover all permitted suffixes.
1288         (movzw): New.
1289         * i386-tbl.h: Re-generate.
1290
1291 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1292
1293         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1294         (lgdt): Remove Tbyte from non-64-bit variant.
1295         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1296         xsaves64, xsavec64): Remove Disp16.
1297         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1298         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1299         64-bit variants.
1300         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1301         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1302         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1303         64-bit variants.
1304         * i386-tbl.h: Re-generate.
1305
1306 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1307
1308         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1309         * i386-tbl.h: Re-generate.
1310
1311 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1312
1313         * arm-dis.c (print_insn): Fix typo in comment.
1314
1315 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1316
1317         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1318         range of ldst_elemlist operands.
1319         (print_register_list): Use PRIi64 to print the index.
1320         (aarch64_print_operand): Likewise.
1321
1322 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1323
1324         * mcore-opc.h: Remove sentinal.
1325         * mcore-dis.c (print_insn_mcore): Adjust.
1326
1327 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1328
1329         * arc-opc.c: Correct description of availability of NPS400
1330         features.
1331
1332 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1333
1334         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1335         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1336         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1337         xor3>: New mnemonics.
1338         <setb>: Change to a VX form instruction.
1339         (insert_sh6): Add support for rldixor.
1340         (extract_sh6): Likewise.
1341
1342 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1343
1344         * arc-ext.h: Wrap in extern C.
1345
1346 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1347
1348         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1349         Use same method for determining instruction length on ARC700 and
1350         NPS-400.
1351         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1352         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1353         with the NPS400 subclass.
1354         * arc-opc.c: Likewise.
1355
1356 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1357
1358         * sparc-opc.c (rdasr): New macro.
1359         (wrasr): Likewise.
1360         (rdpr): Likewise.
1361         (wrpr): Likewise.
1362         (rdhpr): Likewise.
1363         (wrhpr): Likewise.
1364         (sparc_opcodes): Use the macros above to fix and expand the
1365         definition of read/write instructions from/to
1366         asr/privileged/hyperprivileged instructions.
1367         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1368         %hva_mask_nz.  Prefer softint_set and softint_clear over
1369         set_softint and clear_softint.
1370         (print_insn_sparc): Support %ver in Rd.
1371
1372 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1373
1374         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1375         architecture according to the hardware capabilities they require.
1376
1377 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1378
1379         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1380         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1381         bfd_mach_sparc_v9{c,d,e,v,m}.
1382         * sparc-opc.c (MASK_V9C): Define.
1383         (MASK_V9D): Likewise.
1384         (MASK_V9E): Likewise.
1385         (MASK_V9V): Likewise.
1386         (MASK_V9M): Likewise.
1387         (v6): Add MASK_V9{C,D,E,V,M}.
1388         (v6notlet): Likewise.
1389         (v7): Likewise.
1390         (v8): Likewise.
1391         (v9): Likewise.
1392         (v9andleon): Likewise.
1393         (v9a): Likewise.
1394         (v9b): Likewise.
1395         (v9c): Define.
1396         (v9d): Likewise.
1397         (v9e): Likewise.
1398         (v9v): Likewise.
1399         (v9m): Likewise.
1400         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1401
1402 2016-06-15  Nick Clifton  <nickc@redhat.com>
1403
1404         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1405         constants to match expected behaviour.
1406         (nds32_parse_opcode): Likewise.  Also for whitespace.
1407
1408 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1409
1410         * arc-opc.c (extract_rhv1): Extract value from insn.
1411
1412 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1413
1414         * arc-nps400-tbl.h: Add ldbit instruction.
1415         * arc-opc.c: Add flag classes required for ldbit.
1416
1417 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1418
1419         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1420         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1421         support the above instructions.
1422
1423 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1424
1425         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1426         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1427         csma, cbba, zncv, and hofs.
1428         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1429         support the above instructions.
1430
1431 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1432
1433         * arc-nps400-tbl.h: Add andab and orab instructions.
1434
1435 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1436
1437         * arc-nps400-tbl.h: Add addl-like instructions.
1438
1439 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1440
1441         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1442
1443 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1444
1445         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1446         instructions.
1447
1448 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1449
1450         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1451         variable.
1452         (init_disasm): Handle new command line option "insnlength".
1453         (print_s390_disassembler_options): Mention new option in help
1454         output.
1455         (print_insn_s390): Use the encoded insn length when dumping
1456         unknown instructions.
1457
1458 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1459
1460         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1461          to the address and set as symbol address for LDS/ STS immediate operands.
1462
1463 2016-06-07  Alan Modra  <amodra@gmail.com>
1464
1465         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1466         cpu for "vle" to e500.
1467         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1468         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1469         (PPCNONE): Delete, substitute throughout.
1470         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1471         except for major opcode 4 and 31.
1472         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1473
1474 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1475
1476         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1477         ARM_EXT_RAS in relevant entries.
1478
1479 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1480
1481         PR binutils/20196
1482         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1483         opcodes for E6500.
1484
1485 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1486
1487         PR binutis/18386
1488         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1489         (indir_v_mode): New.
1490         Add comments for '&'.
1491         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1492         (putop): Handle '&'.
1493         (intel_operand_size): Handle indir_v_mode.
1494         (OP_E_register): Likewise.
1495         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1496         64-bit indirect call/jmp for AMD64.
1497         * i386-tbl.h: Regenerated
1498
1499 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1500
1501         * arc-dis.c (struct arc_operand_iterator): New structure.
1502         (find_format_from_table): All the old content from find_format,
1503         with some minor adjustments, and parameter renaming.
1504         (find_format_long_instructions): New function.
1505         (find_format): Rewritten.
1506         (arc_insn_length): Add LSB parameter.
1507         (extract_operand_value): New function.
1508         (operand_iterator_next): New function.
1509         (print_insn_arc): Use new functions to find opcode, and iterator
1510         over operands.
1511         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1512         (extract_nps_3bit_dst_short): New function.
1513         (insert_nps_3bit_src2_short): New function.
1514         (extract_nps_3bit_src2_short): New function.
1515         (insert_nps_bitop1_size): New function.
1516         (extract_nps_bitop1_size): New function.
1517         (insert_nps_bitop2_size): New function.
1518         (extract_nps_bitop2_size): New function.
1519         (insert_nps_bitop_mod4_msb): New function.
1520         (extract_nps_bitop_mod4_msb): New function.
1521         (insert_nps_bitop_mod4_lsb): New function.
1522         (extract_nps_bitop_mod4_lsb): New function.
1523         (insert_nps_bitop_dst_pos3_pos4): New function.
1524         (extract_nps_bitop_dst_pos3_pos4): New function.
1525         (insert_nps_bitop_ins_ext): New function.
1526         (extract_nps_bitop_ins_ext): New function.
1527         (arc_operands): Add new operands.
1528         (arc_long_opcodes): New global array.
1529         (arc_num_long_opcodes): New global.
1530         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1531
1532 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1533
1534         * nds32-asm.h: Add extern "C".
1535         * sh-opc.h: Likewise.
1536
1537 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1538
1539         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1540         0,b,limm to the rflt instruction.
1541
1542 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1543
1544         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1545         constant.
1546
1547 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1548
1549         PR gas/20145
1550         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1551         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1552         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1553         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1554         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1555         * i386-init.h: Regenerated.
1556
1557 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1558
1559         PR gas/20145
1560         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1561         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1562         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1563         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1564         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1565         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1566         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1567         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1568         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1569         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1570         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1571         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1572         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1573         CpuRegMask for AVX512.
1574         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1575         and CpuRegMask.
1576         (set_bitfield_from_cpu_flag_init): New function.
1577         (set_bitfield): Remove const on f.  Call
1578         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1579         * i386-opc.h (CpuRegMMX): New.
1580         (CpuRegXMM): Likewise.
1581         (CpuRegYMM): Likewise.
1582         (CpuRegZMM): Likewise.
1583         (CpuRegMask): Likewise.
1584         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1585         and cpuregmask.
1586         * i386-init.h: Regenerated.
1587         * i386-tbl.h: Likewise.
1588
1589 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1590
1591         PR gas/20154
1592         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1593         (opcode_modifiers): Add AMD64 and Intel64.
1594         (main): Properly verify CpuMax.
1595         * i386-opc.h (CpuAMD64): Removed.
1596         (CpuIntel64): Likewise.
1597         (CpuMax): Set to CpuNo64.
1598         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1599         (AMD64): New.
1600         (Intel64): Likewise.
1601         (i386_opcode_modifier): Add amd64 and intel64.
1602         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1603         on call and jmp.
1604         * i386-init.h: Regenerated.
1605         * i386-tbl.h: Likewise.
1606
1607 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1608
1609         PR gas/20154
1610         * i386-gen.c (main): Fail if CpuMax is incorrect.
1611         * i386-opc.h (CpuMax): Set to CpuIntel64.
1612         * i386-tbl.h: Regenerated.
1613
1614 2016-05-27  Nick Clifton  <nickc@redhat.com>
1615
1616         PR target/20150
1617         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1618         (msp430dis_opcode_unsigned): New function.
1619         (msp430dis_opcode_signed): New function.
1620         (msp430_singleoperand): Use the new opcode reading functions.
1621         Only disassenmble bytes if they were successfully read.
1622         (msp430_doubleoperand): Likewise.
1623         (msp430_branchinstr): Likewise.
1624         (msp430x_callx_instr): Likewise.
1625         (print_insn_msp430): Check that it is safe to read bytes before
1626         attempting disassembly.  Use the new opcode reading functions.
1627
1628 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1629
1630         * ppc-opc.c (CY): New define.  Document it.
1631         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1632
1633 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1634
1635         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1636         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1637         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1638         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1639         CPU_ANY_AVX_FLAGS.
1640         * i386-init.h: Regenerated.
1641
1642 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1643
1644         PR gas/20141
1645         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1646         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1647         * i386-init.h: Regenerated.
1648
1649 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1650
1651         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1652         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1653         * i386-init.h: Regenerated.
1654
1655 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1656
1657         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1658         information.
1659         (print_insn_arc): Set insn_type information.
1660         * arc-opc.c (C_CC): Add F_CLASS_COND.
1661         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1662         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1663         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1664         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1665         (brne, brne_s, jeq_s, jne_s): Likewise.
1666
1667 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1668
1669         * arc-tbl.h (neg): New instruction variant.
1670
1671 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1672
1673         * arc-dis.c (find_format, find_format, get_auxreg)
1674         (print_insn_arc): Changed.
1675         * arc-ext.h (INSERT_XOP): Likewise.
1676
1677 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1678
1679         * tic54x-dis.c (sprint_mmr): Adjust.
1680         * tic54x-opc.c: Likewise.
1681
1682 2016-05-19  Alan Modra  <amodra@gmail.com>
1683
1684         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1685
1686 2016-05-19  Alan Modra  <amodra@gmail.com>
1687
1688         * ppc-opc.c: Formatting.
1689         (NSISIGNOPT): Define.
1690         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1691
1692 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1693
1694         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1695         replacing references to `micromips_ase' throughout.
1696         (_print_insn_mips): Don't use file-level microMIPS annotation to
1697         determine the disassembly mode with the symbol table.
1698
1699 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1700
1701         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1702
1703 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1704
1705         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1706         mips64r6.
1707         * mips-opc.c (D34): New macro.
1708         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1709
1710 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1711
1712         * i386-dis.c (prefix_table): Add RDPID instruction.
1713         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1714         (cpu_flags): Add RDPID bitfield.
1715         * i386-opc.h (enum): Add RDPID element.
1716         (i386_cpu_flags): Add RDPID field.
1717         * i386-opc.tbl: Add RDPID instruction.
1718         * i386-init.h: Regenerate.
1719         * i386-tbl.h: Regenerate.
1720
1721 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1722
1723         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1724         branch type of a symbol.
1725         (print_insn): Likewise.
1726
1727 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1728
1729         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1730         Mainline Security Extensions instructions.
1731         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1732         Extensions instructions.
1733         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1734         instructions.
1735         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1736         special registers.
1737
1738 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1739
1740         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1741
1742 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1743
1744         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1745         (arcExtMap_genOpcode): Likewise.
1746         * arc-opc.c (arg_32bit_rc): Define new variable.
1747         (arg_32bit_u6): Likewise.
1748         (arg_32bit_limm): Likewise.
1749
1750 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1751
1752         * aarch64-gen.c (VERIFIER): Define.
1753         * aarch64-opc.c (VERIFIER): Define.
1754         (verify_ldpsw): Use static linkage.
1755         * aarch64-opc.h (verify_ldpsw): Remove.
1756         * aarch64-tbl.h: Use VERIFIER for verifiers.
1757
1758 2016-04-28  Nick Clifton  <nickc@redhat.com>
1759
1760         PR target/19722
1761         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1762         * aarch64-opc.c (verify_ldpsw): New function.
1763         * aarch64-opc.h (verify_ldpsw): New prototype.
1764         * aarch64-tbl.h: Add initialiser for verifier field.
1765         (LDPSW): Set verifier to verify_ldpsw.
1766
1767 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1768
1769         PR binutils/19983
1770         PR binutils/19984
1771         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1772         smaller than address size.
1773
1774 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1775
1776         * alpha-dis.c: Regenerate.
1777         * crx-dis.c: Likewise.
1778         * disassemble.c: Likewise.
1779         * epiphany-opc.c: Likewise.
1780         * fr30-opc.c: Likewise.
1781         * frv-opc.c: Likewise.
1782         * ip2k-opc.c: Likewise.
1783         * iq2000-opc.c: Likewise.
1784         * lm32-opc.c: Likewise.
1785         * lm32-opinst.c: Likewise.
1786         * m32c-opc.c: Likewise.
1787         * m32r-opc.c: Likewise.
1788         * m32r-opinst.c: Likewise.
1789         * mep-opc.c: Likewise.
1790         * mt-opc.c: Likewise.
1791         * or1k-opc.c: Likewise.
1792         * or1k-opinst.c: Likewise.
1793         * tic80-opc.c: Likewise.
1794         * xc16x-opc.c: Likewise.
1795         * xstormy16-opc.c: Likewise.
1796
1797 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1798
1799         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1800         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1801         calcsd, and calcxd instructions.
1802         * arc-opc.c (insert_nps_bitop_size): Delete.
1803         (extract_nps_bitop_size): Delete.
1804         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1805         (extract_nps_qcmp_m3): Define.
1806         (extract_nps_qcmp_m2): Define.
1807         (extract_nps_qcmp_m1): Define.
1808         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1809         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1810         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1811         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1812         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1813         NPS_QCMP_M3.
1814
1815 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1816
1817         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1818
1819 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1820
1821         * Makefile.in: Regenerated with automake 1.11.6.
1822         * aclocal.m4: Likewise.
1823
1824 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1825
1826         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1827         instructions.
1828         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1829         (extract_nps_cmem_uimm16): New function.
1830         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1831
1832 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1833
1834         * arc-dis.c (arc_insn_length): New function.
1835         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1836         (find_format): Change insnLen parameter to unsigned.
1837
1838 2016-04-13  Nick Clifton  <nickc@redhat.com>
1839
1840         PR target/19937
1841         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1842         the LD.B and LD.BU instructions.
1843
1844 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1845
1846         * arc-dis.c (find_format): Check for extension flags.
1847         (print_flags): New function.
1848         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1849         .extAuxRegister.
1850         * arc-ext.c (arcExtMap_coreRegName): Use
1851         LAST_EXTENSION_CORE_REGISTER.
1852         (arcExtMap_coreReadWrite): Likewise.
1853         (dump_ARC_extmap): Update printing.
1854         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1855         (arc_aux_regs): Add cpu field.
1856         * arc-regs.h: Add cpu field, lower case name aux registers.
1857
1858 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1859
1860         * arc-tbl.h: Add rtsc, sleep with no arguments.
1861
1862 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1863
1864         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1865         Initialize.
1866         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1867         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1868         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1869         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1870         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1871         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1872         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1873         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1874         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1875         (arc_opcode arc_opcodes): Null terminate the array.
1876         (arc_num_opcodes): Remove.
1877         * arc-ext.h (INSERT_XOP): Define.
1878         (extInstruction_t): Likewise.
1879         (arcExtMap_instName): Delete.
1880         (arcExtMap_insn): New function.
1881         (arcExtMap_genOpcode): Likewise.
1882         * arc-ext.c (ExtInstruction): Remove.
1883         (create_map): Zero initialize instruction fields.
1884         (arcExtMap_instName): Remove.
1885         (arcExtMap_insn): New function.
1886         (dump_ARC_extmap): More info while debuging.
1887         (arcExtMap_genOpcode): New function.
1888         * arc-dis.c (find_format): New function.
1889         (print_insn_arc): Use find_format.
1890         (arc_get_disassembler): Enable dump_ARC_extmap only when
1891         debugging.
1892
1893 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1894
1895         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1896         instruction bits out.
1897
1898 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1899
1900         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1901         * arc-opc.c (arc_flag_operands): Add new flags.
1902         (arc_flag_classes): Add new classes.
1903
1904 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1905
1906         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1907
1908 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1909
1910         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1911         encode1, rflt, crc16, and crc32 instructions.
1912         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1913         (arc_flag_classes): Add C_NPS_R.
1914         (insert_nps_bitop_size_2b): New function.
1915         (extract_nps_bitop_size_2b): Likewise.
1916         (insert_nps_bitop_uimm8): Likewise.
1917         (extract_nps_bitop_uimm8): Likewise.
1918         (arc_operands): Add new operand entries.
1919
1920 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1921
1922         * arc-regs.h: Add a new subclass field.  Add double assist
1923         accumulator register values.
1924         * arc-tbl.h: Use DPA subclass to mark the double assist
1925         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1926         * arc-opc.c (RSP): Define instead of SP.
1927         (arc_aux_regs): Add the subclass field.
1928
1929 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1930
1931         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1932
1933 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1934
1935         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1936         NPS_R_SRC1.
1937
1938 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1939
1940         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1941         issues.  No functional changes.
1942
1943 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1944
1945         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1946         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1947         (RTT): Remove duplicate.
1948         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1949         (PCT_CONFIG*): Remove.
1950         (D1L, D1H, D2H, D2L): Define.
1951
1952 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1953
1954         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1955
1956 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1957
1958         * arc-tbl.h (invld07): Remove.
1959         * arc-ext-tbl.h: New file.
1960         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1961         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1962
1963 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1964
1965         Fix -Wstack-usage warnings.
1966         * aarch64-dis.c (print_operands): Substitute size.
1967         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1968
1969 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1970
1971         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1972         to get a proper diagnostic when an invalid ASR register is used.
1973
1974 2016-03-22  Nick Clifton  <nickc@redhat.com>
1975
1976         * configure: Regenerate.
1977
1978 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1979
1980         * arc-nps400-tbl.h: New file.
1981         * arc-opc.c: Add top level comment.
1982         (insert_nps_3bit_dst): New function.
1983         (extract_nps_3bit_dst): New function.
1984         (insert_nps_3bit_src2): New function.
1985         (extract_nps_3bit_src2): New function.
1986         (insert_nps_bitop_size): New function.
1987         (extract_nps_bitop_size): New function.
1988         (arc_flag_operands): Add nps400 entries.
1989         (arc_flag_classes): Add nps400 entries.
1990         (arc_operands): Add nps400 entries.
1991         (arc_opcodes): Add nps400 include.
1992
1993 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1994
1995         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1996         the new class enum values.
1997
1998 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1999
2000         * arc-dis.c (print_insn_arc): Handle nps400.
2001
2002 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
2003
2004         * arc-opc.c (BASE): Delete.
2005
2006 2016-03-18  Nick Clifton  <nickc@redhat.com>
2007
2008         PR target/19721
2009         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
2010         of MOV insn that aliases an ORR insn.
2011
2012 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
2013
2014         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
2015
2016 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
2017
2018         * mcore-opc.h: Add const qualifiers.
2019         * microblaze-opc.h (struct op_code_struct): Likewise.
2020         * sh-opc.h: Likewise.
2021         * tic4x-dis.c (tic4x_print_indirect): Likewise.
2022         (tic4x_print_op): Likewise.
2023
2024 2016-03-02  Alan Modra  <amodra@gmail.com>
2025
2026         * or1k-desc.h: Regenerate.
2027         * fr30-ibld.c: Regenerate.
2028         * rl78-decode.c: Regenerate.
2029
2030 2016-03-01  Nick Clifton  <nickc@redhat.com>
2031
2032         PR target/19747
2033         * rl78-dis.c (print_insn_rl78_common): Fix typo.
2034
2035 2016-02-24  Renlin Li  <renlin.li@arm.com>
2036
2037         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
2038         (print_insn_coprocessor): Support fp16 instructions.
2039
2040 2016-02-24  Renlin Li  <renlin.li@arm.com>
2041
2042         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
2043         vminnm, vrint(mpna).
2044
2045 2016-02-24  Renlin Li  <renlin.li@arm.com>
2046
2047         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
2048         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
2049
2050 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
2051
2052         * i386-dis.c (print_insn): Parenthesize expression to prevent
2053         truncated addresses.
2054         (OP_J): Likewise.
2055
2056 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
2057             Janek van Oirschot  <jvanoirs@synopsys.com>
2058
2059         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2060         variable.
2061
2062 2016-02-04  Nick Clifton  <nickc@redhat.com>
2063
2064         PR target/19561
2065         * msp430-dis.c (print_insn_msp430): Add a special case for
2066         decoding an RRC instruction with the ZC bit set in the extension
2067         word.
2068
2069 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2070
2071         * cgen-ibld.in (insert_normal): Rework calculation of shift.
2072         * epiphany-ibld.c: Regenerate.
2073         * fr30-ibld.c: Regenerate.
2074         * frv-ibld.c: Regenerate.
2075         * ip2k-ibld.c: Regenerate.
2076         * iq2000-ibld.c: Regenerate.
2077         * lm32-ibld.c: Regenerate.
2078         * m32c-ibld.c: Regenerate.
2079         * m32r-ibld.c: Regenerate.
2080         * mep-ibld.c: Regenerate.
2081         * mt-ibld.c: Regenerate.
2082         * or1k-ibld.c: Regenerate.
2083         * xc16x-ibld.c: Regenerate.
2084         * xstormy16-ibld.c: Regenerate.
2085
2086 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2087
2088         * epiphany-dis.c: Regenerated from latest cpu files.
2089
2090 2016-02-01  Michael McConville  <mmcco@mykolab.com>
2091
2092         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2093         test bit.
2094
2095 2016-01-25  Renlin Li  <renlin.li@arm.com>
2096
2097         * arm-dis.c (mapping_symbol_for_insn): New function.
2098         (find_ifthen_state): Call mapping_symbol_for_insn().
2099
2100 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
2101
2102         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2103         of MSR UAO immediate operand.
2104
2105 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
2106
2107         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2108         instruction support.
2109
2110 2016-01-17  Alan Modra  <amodra@gmail.com>
2111
2112         * configure: Regenerate.
2113
2114 2016-01-14  Nick Clifton  <nickc@redhat.com>
2115
2116         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2117         instructions that can support stack pointer operations.
2118         * rl78-decode.c: Regenerate.
2119         * rl78-dis.c: Fix display of stack pointer in MOVW based
2120         instructions.
2121
2122 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
2123
2124         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2125         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
2126         erxtatus_el1 and erxaddr_el1.
2127
2128 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
2129
2130         * arm-dis.c (arm_opcodes): Add "esb".
2131         (thumb_opcodes): Likewise.
2132
2133 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
2134
2135         * ppc-opc.c <xscmpnedp>: Delete.
2136         <xvcmpnedp>: Likewise.
2137         <xvcmpnedp.>: Likewise.
2138         <xvcmpnesp>: Likewise.
2139         <xvcmpnesp.>: Likewise.
2140
2141 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2142
2143         PR gas/13050
2144         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2145         addition to ISA_A.
2146
2147 2016-01-01  Alan Modra  <amodra@gmail.com>
2148
2149         Update year range in copyright notice of all files.
2150
2151 For older changes see ChangeLog-2015
2152 \f
2153 Copyright (C) 2016 Free Software Foundation, Inc.
2154
2155 Copying and distribution of this file, with or without modification,
2156 are permitted in any medium without royalty provided the copyright
2157 notice and this notice are preserved.
2158
2159 Local Variables:
2160 mode: change-log
2161 left-margin: 8
2162 fill-column: 74
2163 version-control: never
2164 End: