1 2013-04-06 David S. Miller <davem@davemloft.net>
3 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
4 of an opcode, prefer the one with F_PREFERRED set.
5 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
6 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
7 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
8 mark existing mnenomics as aliases. Add "cc" suffix to edge
9 instructions generating condition codes, mark existing mnenomics
10 as aliases. Add "fp" prefix to VIS compare instructions, mark
11 existing mnenomics as aliases.
13 2013-04-03 Nick Clifton <nickc@redhat.com>
15 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
16 destination address by subtracting the operand from the current
18 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
19 a positive value in the insn.
20 (extract_u16_loop): Do not negate the returned value.
21 (D16_LOOP): Add V850_INVERSE_PCREL flag.
23 (ceilf.sw): Remove duplicate entry.
30 (maddf.s): Restrict to E3V5 architectures.
35 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
37 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
39 (print_insn): Pass sizeflag to get_sib.
41 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
44 * tic6x-dis.c: Add support for displaying 16-bit insns.
46 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
49 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
50 individual msb and lsb halves in src1 & src2 fields. Discard the
51 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
52 follow what Ti SDK does in that case as any value in the src1
53 field yields the same output with SDK disassembler.
55 2013-03-12 Michael Eager <eager@eagercon.com>
57 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
59 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
61 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
63 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
65 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
67 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
69 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
71 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
73 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
74 (thumb32_opcodes): Likewise.
75 (print_insn_thumb32): Handle 'S' control char.
77 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
79 * lm32-desc.c: Regenerate.
81 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
83 * i386-reg.tbl (riz): Add RegRex64.
84 * i386-tbl.h: Regenerated.
86 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
88 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
89 (aarch64_feature_crc): New static.
91 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
92 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
93 * aarch64-asm-2.c: Re-generate.
94 * aarch64-dis-2.c: Ditto.
95 * aarch64-opc-2.c: Ditto.
97 2013-02-27 Alan Modra <amodra@gmail.com>
99 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
100 * rl78-decode.c: Regenerate.
102 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
104 * rl78-decode.opc: Fix encoding of DIVWU insn.
105 * rl78-decode.c: Regenerate.
107 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
110 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
112 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
113 (cpu_flags): Add CpuSMAP.
115 * i386-opc.h (CpuSMAP): New.
116 (i386_cpu_flags): Add cpusmap.
118 * i386-opc.tbl: Add clac and stac.
120 * i386-init.h: Regenerated.
121 * i386-tbl.h: Likewise.
123 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
125 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
126 which also makes the disassembler output be in little
127 endian like it should be.
129 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
131 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
133 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
135 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
137 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
138 section disassembled.
140 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
142 * arm-dis.c: Update strht pattern.
144 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
146 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
147 single-float. Disable ll, lld, sc and scd for EE. Disable the
148 trunc.w.s macro for EE.
150 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
151 Andrew Jenner <andrew@codesourcery.com>
153 Based on patches from Altera Corporation.
155 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
157 * Makefile.in: Regenerated.
158 * configure.in: Add case for bfd_nios2_arch.
159 * configure: Regenerated.
160 * disassemble.c (ARCH_nios2): Define.
161 (disassembler): Add case for bfd_arch_nios2.
162 * nios2-dis.c: New file.
163 * nios2-opc.c: New file.
165 2013-02-04 Alan Modra <amodra@gmail.com>
167 * po/POTFILES.in: Regenerate.
168 * rl78-decode.c: Regenerate.
169 * rx-decode.c: Regenerate.
171 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
173 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
174 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
175 * aarch64-asm.c (convert_xtl_to_shll): New function.
176 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
177 calling convert_xtl_to_shll.
178 * aarch64-dis.c (convert_shll_to_xtl): New function.
179 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
180 calling convert_shll_to_xtl.
181 * aarch64-gen.c: Update copyright year.
182 * aarch64-asm-2.c: Re-generate.
183 * aarch64-dis-2.c: Re-generate.
184 * aarch64-opc-2.c: Re-generate.
186 2013-01-24 Nick Clifton <nickc@redhat.com>
188 * v850-dis.c: Add support for e3v5 architecture.
189 * v850-opc.c: Likewise.
191 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
193 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
194 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
195 * aarch64-opc.c (operand_general_constraint_met_p): For
196 AARCH64_MOD_LSL, move the range check on the shift amount before the
197 alignment check; change to call set_sft_amount_out_of_range_error
198 instead of set_imm_out_of_range_error.
199 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
200 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
201 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
204 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
206 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
208 * i386-init.h: Regenerated.
209 * i386-tbl.h: Likewise.
211 2013-01-15 Nick Clifton <nickc@redhat.com>
213 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
215 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
217 2013-01-14 Will Newton <will.newton@imgtec.com>
219 * metag-dis.c (REG_WIDTH): Increase to 64.
221 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
223 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
224 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
225 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
227 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
228 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
229 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
230 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
232 2013-01-10 Will Newton <will.newton@imgtec.com>
234 * Makefile.am: Add Meta.
235 * configure.in: Add Meta.
236 * disassemble.c: Add Meta support.
237 * metag-dis.c: New file.
238 * Makefile.in: Regenerate.
239 * configure: Regenerate.
241 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
243 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
244 (match_opcode): Rename to cr16_match_opcode.
246 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
248 * mips-dis.c: Add names for CP0 registers of r5900.
249 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
250 instructions sq and lq.
251 Add support for MIPS r5900 CPU.
252 Add support for 128 bit MMI (Multimedia Instructions).
253 Add support for EE instructions (Emotion Engine).
254 Disable unsupported floating point instructions (64 bit and
255 undefined compare operations).
256 Enable instructions of MIPS ISA IV which are supported by r5900.
257 Disable 64 bit co processor instructions.
258 Disable 64 bit multiplication and division instructions.
259 Disable instructions for co-processor 2 and 3, because these are
260 not supported (preparation for later VU0 support (Vector Unit)).
261 Disable cvt.w.s because this behaves like trunc.w.s and the
262 correct execution can't be ensured on r5900.
263 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
264 will confuse less developers and compilers.
266 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
268 * aarch64-opc.c (aarch64_print_operand): Change to print
269 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
271 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
272 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
275 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
277 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
278 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
280 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
282 * i386-gen.c (process_copyright): Update copyright year to 2013.
284 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
286 * cr16-dis.c (match_opcode,make_instruction): Remove static
288 (dwordU,wordU): Moved typedefs to opcode/cr16.h
289 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
291 For older changes see ChangeLog-2012
293 Copyright (C) 2013 Free Software Foundation, Inc.
295 Copying and distribution of this file, with or without modification,
296 are permitted in any medium without royalty provided the copyright
297 notice and this notice are preserved.
303 version-control: never