1 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
3 * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
5 Annotate several instructions with the HWCAP2_VIS3B hwcap.
7 2014-10-15 Tristan Gingold <gingold@adacore.com>
9 * configure: Regenerate.
11 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
13 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
14 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
15 Annotate table with HWCAP2 bits.
16 Add instructions xmontmul, xmontsqr, xmpmul.
17 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
18 r,i,%mwait' and `rd %mwait,r' instructions.
19 Add rd/wr instructions for accessing the %mcdper ancillary state
21 (sparc-opcodes): Add sparc5/vis4.0 instructions:
22 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
23 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
24 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
25 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
26 fpsubus16, and faligndatai.
27 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
28 ancillary state register to the table.
29 (print_insn_sparc): Handle the %mcdper ancillary state register.
30 (print_insn_sparc): Handle new operand type '}'.
32 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
34 * i386-dis.c (MOD_0F20): Removed.
38 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
40 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
41 (OP_R): Check mod/rm byte and call OP_E_register.
43 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
45 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
46 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
47 keyword_aridxi): Add audio ISA extension.
48 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
49 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
50 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
51 for nds32-dis.c using.
52 (build_opcode_syntax): Remove dead code.
53 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
54 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
55 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
57 * nds32-asm.h: Declare.
58 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
61 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
62 Matthew Fortune <matthew.fortune@imgtec.com>
64 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
66 (parse_mips_dis_option): Allow MSA and virtualization support for
68 (mips_print_arg_state): Add fields dest_regno and seen_dest.
69 (mips_seen_register): New function.
70 (print_insn_arg): Refactored code to use mips_seen_register
71 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
72 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
73 the register rather than aborting.
74 (print_insn_args): Add length argument. Add code to correctly
75 calculate the instruction address for pc relative instructions.
76 (validate_insn_args): New static function.
77 (print_insn_mips): Prevent jalx disassembling for r6. Use
79 (print_insn_micromips): Use validate_insn_args.
80 all the arguments are valid.
81 * mips-formats.h (PREV_CHECK): New define.
82 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
83 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
88 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
89 MIPS R6 instructions from MIPS R2 instructions.
91 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
93 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
94 (putop): Handle "%LP".
96 2014-09-03 Jiong Wang <jiong.wang@arm.com>
98 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
99 * aarch64-dis-2.c: Update auto-generated file.
101 2014-09-03 Jiong Wang <jiong.wang@arm.com>
103 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
104 (aarch64_feature_lse): New feature added.
106 (aarch64_opcode_table): New LSE instructions added. Improve
107 descriptions for ldarb/ldarh/ldar.
108 (aarch64_opcode_table): Describe PAIRREG.
109 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
110 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
111 (aarch64_print_operand): Recognize PAIRREG.
112 (operand_general_constraint_met_p): Check reg pair constraints for CASP
114 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
115 (do_special_decoding): Recognize F_LSE_SZ.
116 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
118 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
120 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
121 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
122 "sdbbp", "syscall" and "wait".
124 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
125 Maciej W. Rozycki <macro@codesourcery.com>
127 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
128 returned if the U bit is set.
130 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
132 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
133 48-bit "li" encoding.
135 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
137 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
138 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
139 static functions, code was moved from...
140 (print_insn_s390): ...here.
141 (s390_extract_operand): Adjust comment. Change type of first
142 parameter from 'unsigned char *' to 'const bfd_byte *'.
143 (union operand_value): New.
144 (s390_extract_operand): Change return type to union operand_value.
145 Also avoid integer overflow in sign-extension.
146 (s390_print_insn_with_opcode): Adjust to changed return value from
147 s390_extract_operand(). Change "%i" printf format to "%u" for
149 (init_disasm): Simplify initialization of opc_index[]. This also
150 fixes an access after the last element of s390_opcodes[].
151 (print_insn_s390): Simplify the opcode search loop.
152 Check architecture mask against all searched opcodes, not just the
154 (s390_print_insn_with_opcode): Drop function pointer dereferences
156 (print_insn_s390): Likewise.
157 (s390_insn_length): Simplify formula for return value.
158 (s390_print_insn_with_opcode): Avoid special handling for the
159 separator before the first operand. Use new local variable
160 'flags' in place of 'operand->flags'.
162 2014-08-14 Mike Frysinger <vapier@gentoo.org>
164 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
165 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
166 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
167 Change assignment of 1 to priv->comment to TRUE.
168 (print_insn_bfin): Change legal to a bfd_boolean. Change
169 assignment of 0/1 with priv comment and parallel and legal
172 2014-08-14 Mike Frysinger <vapier@gentoo.org>
174 * bfin-dis.c (OUT): Define.
175 (decode_CC2stat_0): Declare new op_names array.
176 Replace multiple if statements with a single one.
178 2014-08-14 Mike Frysinger <vapier@gentoo.org>
180 * bfin-dis.c (struct private): Add iw0.
181 (_print_insn_bfin): Assign iw0 to priv.iw0.
182 (print_insn_bfin): Drop ifetch and use priv.iw0.
184 2014-08-13 Mike Frysinger <vapier@gentoo.org>
186 * bfin-dis.c (comment, parallel): Move from global scope ...
187 (struct private): ... to this new struct.
188 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
189 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
190 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
191 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
192 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
193 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
194 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
195 print_insn_bfin): Declare private struct. Use priv's comment and
198 2014-08-13 Mike Frysinger <vapier@gentoo.org>
200 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
201 (_print_insn_bfin): Add check for unaligned pc.
203 2014-08-13 Mike Frysinger <vapier@gentoo.org>
205 * bfin-dis.c (ifetch): New function.
206 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
209 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
211 * micromips-opc.c (COD): Rename throughout to...
212 (CM): New define, update to use INSN_COPROC_MOVE.
213 (LCD): Rename throughout to...
214 (LC): New define, update to use INSN_LOAD_COPROC.
215 * mips-opc.c: Likewise.
217 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
219 * micromips-opc.c (COD, LCD) New macros.
220 (cfc1, ctc1): Remove FP_S attribute.
221 (dmfc1, mfc1, mfhc1): Add LCD attribute.
222 (dmtc1, mtc1, mthc1): Add COD attribute.
223 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
225 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
226 Alexander Ivchenko <alexander.ivchenko@intel.com>
227 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
228 Sergey Lega <sergey.s.lega@intel.com>
229 Anna Tikhonova <anna.tikhonova@intel.com>
230 Ilya Tocar <ilya.tocar@intel.com>
231 Andrey Turetskiy <andrey.turetskiy@intel.com>
232 Ilya Verbin <ilya.verbin@intel.com>
233 Kirill Yukhin <kirill.yukhin@intel.com>
234 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
236 * i386-dis-evex.h: Updated.
237 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
238 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
239 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
240 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
242 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
243 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
244 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
245 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
246 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
247 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
248 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
249 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
250 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
251 (prefix_table): Add entries for new instructions.
252 (vex_len_table): Ditto.
253 (vex_w_table): Ditto.
254 (OP_E_memory): Update xmmq_mode handling.
255 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
256 (cpu_flags): Add CpuAVX512DQ.
257 * i386-init.h: Regenerared.
258 * i386-opc.h (CpuAVX512DQ): New.
259 (i386_cpu_flags): Add cpuavx512dq.
260 * i386-opc.tbl: Add AVX512DQ instructions.
261 * i386-tbl.h: Regenerate.
263 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
264 Alexander Ivchenko <alexander.ivchenko@intel.com>
265 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
266 Sergey Lega <sergey.s.lega@intel.com>
267 Anna Tikhonova <anna.tikhonova@intel.com>
268 Ilya Tocar <ilya.tocar@intel.com>
269 Andrey Turetskiy <andrey.turetskiy@intel.com>
270 Ilya Verbin <ilya.verbin@intel.com>
271 Kirill Yukhin <kirill.yukhin@intel.com>
272 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
274 * i386-dis-evex.h: Add new instructions (prefixes bellow).
275 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
276 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
277 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
278 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
279 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
280 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
281 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
282 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
283 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
284 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
285 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
286 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
287 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
288 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
289 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
290 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
291 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
292 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
293 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
294 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
295 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
296 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
297 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
298 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
299 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
300 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
301 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
302 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
303 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
304 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
305 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
306 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
307 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
308 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
309 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
310 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
311 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
312 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
313 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
314 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
315 (prefix_table): Add entries for new instructions.
317 (vex_len_table): Ditto.
318 (vex_w_table): Ditto.
319 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
320 mask_bd_mode handling.
321 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
323 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
325 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
326 (OP_EX): Add dqw_swap_mode handling.
327 (OP_VEX): Add mask_bd_mode handling.
328 (OP_Mask): Add mask_bd_mode handling.
329 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
330 (cpu_flags): Add CpuAVX512BW.
331 * i386-init.h: Regenerated.
332 * i386-opc.h (CpuAVX512BW): New.
333 (i386_cpu_flags): Add cpuavx512bw.
334 * i386-opc.tbl: Add AVX512BW instructions.
335 * i386-tbl.h: Regenerate.
337 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
338 Alexander Ivchenko <alexander.ivchenko@intel.com>
339 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
340 Sergey Lega <sergey.s.lega@intel.com>
341 Anna Tikhonova <anna.tikhonova@intel.com>
342 Ilya Tocar <ilya.tocar@intel.com>
343 Andrey Turetskiy <andrey.turetskiy@intel.com>
344 Ilya Verbin <ilya.verbin@intel.com>
345 Kirill Yukhin <kirill.yukhin@intel.com>
346 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
348 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
349 * i386-tbl.h: Regenerate.
351 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
352 Alexander Ivchenko <alexander.ivchenko@intel.com>
353 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
354 Sergey Lega <sergey.s.lega@intel.com>
355 Anna Tikhonova <anna.tikhonova@intel.com>
356 Ilya Tocar <ilya.tocar@intel.com>
357 Andrey Turetskiy <andrey.turetskiy@intel.com>
358 Ilya Verbin <ilya.verbin@intel.com>
359 Kirill Yukhin <kirill.yukhin@intel.com>
360 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
362 * i386-dis.c (intel_operand_size): Support 128/256 length in
363 vex_vsib_q_w_dq_mode.
364 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
365 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
366 (cpu_flags): Add CpuAVX512VL.
367 * i386-init.h: Regenerated.
368 * i386-opc.h (CpuAVX512VL): New.
369 (i386_cpu_flags): Add cpuavx512vl.
370 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
371 * i386-opc.tbl: Add AVX512VL instructions.
372 * i386-tbl.h: Regenerate.
374 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
376 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
377 * or1k-opinst.c: Regenerate.
379 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
381 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
382 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
384 2014-07-04 Alan Modra <amodra@gmail.com>
386 * configure.ac: Rename from configure.in.
387 * Makefile.in: Regenerate.
388 * config.in: Regenerate.
390 2014-07-04 Alan Modra <amodra@gmail.com>
392 * configure.in: Include bfd/version.m4.
393 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
394 (BFD_VERSION): Delete.
395 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
396 * configure: Regenerate.
397 * Makefile.in: Regenerate.
399 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
400 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
401 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
402 Soundararajan <Sounderarajan.D@atmel.com>
404 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
405 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
406 machine is not avrtiny.
408 2014-06-26 Philippe De Muyter <phdm@macqel.be>
410 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
413 2014-06-12 Alan Modra <amodra@gmail.com>
415 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
416 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
418 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
420 * i386-dis.c (fwait_prefix): New.
421 (ckprefix): Set fwait_prefix.
422 (print_insn): Properly print prefixes before fwait.
424 2014-06-07 Alan Modra <amodra@gmail.com>
426 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
428 2014-06-05 Joel Brobecker <brobecker@adacore.com>
430 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
431 bfd's development.sh.
432 * Makefile.in, configure: Regenerate.
434 2014-06-03 Nick Clifton <nickc@redhat.com>
436 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
437 decide when extended addressing is being used.
439 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
441 * sparc-opc.c (cas): Disable for LEON.
444 2014-05-20 Alan Modra <amodra@gmail.com>
446 * m68k-dis.c: Don't include setjmp.h.
448 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
450 * i386-dis.c (ADDR16_PREFIX): Removed.
451 (ADDR32_PREFIX): Likewise.
452 (DATA16_PREFIX): Likewise.
453 (DATA32_PREFIX): Likewise.
454 (prefix_name): Updated.
455 (print_insn): Simplify data and address size prefixes processing.
457 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
459 * or1k-desc.c: Regenerated.
460 * or1k-desc.h: Likewise.
461 * or1k-opc.c: Likewise.
462 * or1k-opc.h: Likewise.
463 * or1k-opinst.c: Likewise.
465 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
467 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
472 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
474 (parse_mips_dis_option): Update MSA and virtualization support to
475 allow mips64r3 and mips64r5.
477 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
479 * mips-opc.c (G3): Remove I4.
481 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
484 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
485 (end_codep): Likewise.
486 (mandatory_prefix): Likewise.
487 (active_seg_prefix): Likewise.
488 (ckprefix): Set active_seg_prefix to the active segment register
490 (seg_prefix): Removed.
491 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
492 for prefix index. Ignore the index if it is invalid and the
493 mandatory prefix isn't required.
494 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
495 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
496 in used_prefixes here. Don't print unused prefixes. Check
497 active_seg_prefix for the active segment register prefix.
498 Restore the DFLAG bit in sizeflag if the data size prefix is
499 unused. Check the unused mandatory PREFIX_XXX prefixes
500 (append_seg): Only print the segment register which gets used.
501 (OP_E_memory): Check active_seg_prefix for the segment register
504 (OP_OFF64): Likewise.
505 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
507 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
510 * config.in: Regenerated.
511 * configure: Likewise.
512 * configure.in: Check if sigsetjmp is available.
513 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
514 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
515 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
516 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
517 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
518 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
519 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
520 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
521 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
522 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
523 (OPCODES_SIGSETJMP): Likewise.
524 (OPCODES_SIGLONGJMP): Likewise.
525 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
526 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
527 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
528 * xtensa-dis.c (dis_private): Replace jmp_buf with
530 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
531 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
532 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
533 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
534 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
536 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-dis.c (print_insn): Handle prefixes before fwait.
541 2014-04-26 Alan Modra <amodra@gmail.com>
543 * po/POTFILES.in: Regenerate.
545 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
547 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
548 to allow the MIPS XPA ASE.
549 (parse_mips_dis_option): Process the -Mxpa option.
550 * mips-opc.c (XPA): New define.
551 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
552 locations of the ctc0 and cfc0 instructions.
554 2014-04-22 Christian Svensson <blue@cmd.nu>
556 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
557 * configure.in: Likewise.
558 * disassemble.c: Likewise.
559 * or1k-asm.c: New file.
560 * or1k-desc.c: New file.
561 * or1k-desc.h: New file.
562 * or1k-dis.c: New file.
563 * or1k-ibld.c: New file.
564 * or1k-opc.c: New file.
565 * or1k-opc.h: New file.
566 * or1k-opinst.c: New file.
567 * Makefile.in: Regenerate.
568 * configure: Regenerate.
569 * openrisc-asm.c: Delete.
570 * openrisc-desc.c: Delete.
571 * openrisc-desc.h: Delete.
572 * openrisc-dis.c: Delete.
573 * openrisc-ibld.c: Delete.
574 * openrisc-opc.c: Delete.
575 * openrisc-opc.h: Delete.
576 * or32-dis.c: Delete.
577 * or32-opc.c: Delete.
579 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
581 * i386-dis.c (rm_table): Add encls, enclu.
582 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
583 (cpu_flags): Add CpuSE1.
584 * i386-opc.h (enum): Add CpuSE1.
585 (i386_cpu_flags): Add cpuse1.
586 * i386-opc.tbl: Add encls, enclu.
587 * i386-init.h: Regenerated.
588 * i386-tbl.h: Likewise.
590 2014-04-02 Anthony Green <green@moxielogic.com>
592 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
593 instructions, sex.b and sex.s.
595 2014-03-26 Jiong Wang <jiong.wang@arm.com>
597 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
600 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
602 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
603 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
605 * i386-tbl.h: Regenerate.
607 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
609 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
610 %hstick_enable added.
612 2014-03-19 Nick Clifton <nickc@redhat.com>
614 * rx-decode.opc (bwl): Allow for bogus instructions with a size
616 (sbwl, ubwl, SCALE): Likewise.
617 * rx-decode.c: Regenerate.
619 2014-03-12 Alan Modra <amodra@gmail.com>
621 * Makefile.in: Regenerate.
623 2014-03-05 Alan Modra <amodra@gmail.com>
625 Update copyright years.
627 2014-03-04 Heiher <r@hev.cc>
629 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
631 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
633 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
634 so that they come after the Loongson extensions.
636 2014-03-03 Alan Modra <amodra@gmail.com>
638 * i386-gen.c (process_copyright): Emit copyright notice on one line.
640 2014-02-28 Alan Modra <amodra@gmail.com>
642 * msp430-decode.c: Regenerate.
644 2014-02-27 Jiong Wang <jiong.wang@arm.com>
646 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
647 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
649 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
651 * aarch64-opc.c (print_register_offset_address): Call
652 get_int_reg_name to prepare the register name.
654 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
656 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
657 * i386-tbl.h: Regenerate.
659 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
661 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
662 (cpu_flags): Add CpuPREFETCHWT1.
663 * i386-init.h: Regenerate.
664 * i386-opc.h (CpuPREFETCHWT1): New.
665 (i386_cpu_flags): Add cpuprefetchwt1.
666 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
667 * i386-tbl.h: Regenerate.
669 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
671 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
673 * i386-tbl.h: Regenerate.
675 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
677 * i386-gen.c (output_cpu_flags): Don't output trailing space.
678 (output_opcode_modifier): Likewise.
679 (output_operand_type): Likewise.
680 * i386-init.h: Regenerated.
681 * i386-tbl.h: Likewise.
683 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
685 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
687 (PREFIX enum): Add PREFIX_0FAE_REG_7.
688 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
689 (prefix_table): Add clflusopt.
690 (mod_table): Add xrstors, xsavec, xsaves.
691 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
692 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
693 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
694 * i386-init.h: Regenerate.
695 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
696 xsaves64, xsavec, xsavec64.
697 * i386-tbl.h: Regenerate.
699 2014-02-10 Alan Modra <amodra@gmail.com>
701 * po/POTFILES.in: Regenerate.
702 * po/opcodes.pot: Regenerate.
704 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
705 Jan Beulich <jbeulich@suse.com>
708 * i386-dis.c (OP_E_memory): Fix shift computation for
709 vex_vsib_q_w_dq_mode.
711 2014-01-09 Bradley Nelson <bradnelson@google.com>
712 Roland McGrath <mcgrathr@google.com>
714 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
715 last_rex_prefix is -1.
717 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
719 * i386-gen.c (process_copyright): Update copyright year to 2014.
721 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
723 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
725 For older changes see ChangeLog-2013
727 Copyright (C) 2014 Free Software Foundation, Inc.
729 Copying and distribution of this file, with or without modification,
730 are permitted in any medium without royalty provided the copyright
731 notice and this notice are preserved.
737 version-control: never