1 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
3 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
4 c.mv/c.li if rs1 is zero.
6 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
8 * i386-gen.c (cpu_flag_init): Replace CpuABM with
9 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
11 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
12 * i386-opc.h (CpuABM): Removed.
14 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
15 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
16 popcnt. Remove CpuABM from lzcnt.
17 * i386-init.h: Regenerated.
18 * i386-tbl.h: Likewise.
20 2020-02-17 Jan Beulich <jbeulich@suse.com>
22 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
23 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
24 VexW1 instead of open-coding them.
25 * i386-tbl.h: Re-generate.
27 2020-02-17 Jan Beulich <jbeulich@suse.com>
29 * i386-opc.tbl (AddrPrefixOpReg): Define.
30 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
31 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
32 templates. Drop NoRex64.
33 * i386-tbl.h: Re-generate.
35 2020-02-17 Jan Beulich <jbeulich@suse.com>
38 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
39 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
40 into Intel syntax instance (with Unpsecified) and AT&T one
42 (vcvtneps2bf16): Likewise, along with folding the two so far
44 * i386-tbl.h: Re-generate.
46 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
48 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
51 2020-02-17 Alan Modra <amodra@gmail.com>
53 * i386-gen.c (cpu_flag_init): Correct last change.
55 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
57 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
60 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
62 * i386-opc.tbl (movsx): Remove Intel syntax comments.
65 2020-02-14 Jan Beulich <jbeulich@suse.com>
68 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
69 destination for Cpu64-only variant.
70 (movzx): Fold patterns.
71 * i386-tbl.h: Re-generate.
73 2020-02-13 Jan Beulich <jbeulich@suse.com>
75 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
76 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
77 CPU_ANY_SSE4_FLAGS entry.
78 * i386-init.h: Re-generate.
80 2020-02-12 Jan Beulich <jbeulich@suse.com>
82 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
83 with Unspecified, making the present one AT&T syntax only.
84 * i386-tbl.h: Re-generate.
86 2020-02-12 Jan Beulich <jbeulich@suse.com>
88 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
89 * i386-tbl.h: Re-generate.
91 2020-02-12 Jan Beulich <jbeulich@suse.com>
94 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
95 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
96 Amd64 and Intel64 templates.
97 (call, jmp): Likewise for far indirect variants. Dro
99 * i386-tbl.h: Re-generate.
101 2020-02-11 Jan Beulich <jbeulich@suse.com>
103 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
104 * i386-opc.h (ShortForm): Delete.
105 (struct i386_opcode_modifier): Remove shortform field.
106 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
107 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
108 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
109 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
111 * i386-tbl.h: Re-generate.
113 2020-02-11 Jan Beulich <jbeulich@suse.com>
115 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
116 fucompi): Drop ShortForm from operand-less templates.
117 * i386-tbl.h: Re-generate.
119 2020-02-11 Alan Modra <amodra@gmail.com>
121 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
122 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
123 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
124 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
125 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
127 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
129 * arm-dis.c (print_insn_cde): Define 'V' parse character.
130 (cde_opcodes): Add VCX* instructions.
132 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
133 Matthew Malcomson <matthew.malcomson@arm.com>
135 * arm-dis.c (struct cdeopcode32): New.
136 (CDE_OPCODE): New macro.
137 (cde_opcodes): New disassembly table.
138 (regnames): New option to table.
139 (cde_coprocs): New global variable.
140 (print_insn_cde): New
141 (print_insn_thumb32): Use print_insn_cde.
142 (parse_arm_disassembler_options): Parse coprocN args.
144 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
147 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
149 * i386-opc.h (AMD64): Removed.
153 (INTEL64ONLY): Likewise.
154 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
155 * i386-opc.tbl (Amd64): New.
157 (Intel64Only): Likewise.
158 Replace AMD64 with Amd64. Update sysenter/sysenter with
159 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
160 * i386-tbl.h: Regenerated.
162 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
165 * z80-dis.c: Add support for GBZ80 opcodes.
167 2020-02-04 Alan Modra <amodra@gmail.com>
169 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
171 2020-02-03 Alan Modra <amodra@gmail.com>
173 * m32c-ibld.c: Regenerate.
175 2020-02-01 Alan Modra <amodra@gmail.com>
177 * frv-ibld.c: Regenerate.
179 2020-01-31 Jan Beulich <jbeulich@suse.com>
181 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
182 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
183 (OP_E_memory): Replace xmm_mdq_mode case label by
184 vex_scalar_w_dq_mode one.
185 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
187 2020-01-31 Jan Beulich <jbeulich@suse.com>
189 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
190 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
191 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
192 (intel_operand_size): Drop vex_w_dq_mode case label.
194 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
196 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
197 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
199 2020-01-30 Alan Modra <amodra@gmail.com>
201 * m32c-ibld.c: Regenerate.
203 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
205 * bpf-opc.c: Regenerate.
207 2020-01-30 Jan Beulich <jbeulich@suse.com>
209 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
210 (dis386): Use them to replace C2/C3 table entries.
211 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
212 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
213 ones. Use Size64 instead of DefaultSize on Intel64 ones.
214 * i386-tbl.h: Re-generate.
216 2020-01-30 Jan Beulich <jbeulich@suse.com>
218 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
220 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
222 * i386-tbl.h: Re-generate.
224 2020-01-30 Alan Modra <amodra@gmail.com>
226 * tic4x-dis.c (tic4x_dp): Make unsigned.
228 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
229 Jan Beulich <jbeulich@suse.com>
232 * i386-dis.c (MOVSXD_Fixup): New function.
233 (movsxd_mode): New enum.
234 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
235 (intel_operand_size): Handle movsxd_mode.
236 (OP_E_register): Likewise.
238 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
239 register on movsxd. Add movsxd with 16-bit destination register
240 for AMD64 and Intel64 ISAs.
241 * i386-tbl.h: Regenerated.
243 2020-01-27 Tamar Christina <tamar.christina@arm.com>
246 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
247 * aarch64-asm-2.c: Regenerate
248 * aarch64-dis-2.c: Likewise.
249 * aarch64-opc-2.c: Likewise.
251 2020-01-21 Jan Beulich <jbeulich@suse.com>
253 * i386-opc.tbl (sysret): Drop DefaultSize.
254 * i386-tbl.h: Re-generate.
256 2020-01-21 Jan Beulich <jbeulich@suse.com>
258 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
260 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
261 * i386-tbl.h: Re-generate.
263 2020-01-20 Nick Clifton <nickc@redhat.com>
265 * po/de.po: Updated German translation.
266 * po/pt_BR.po: Updated Brazilian Portuguese translation.
267 * po/uk.po: Updated Ukranian translation.
269 2020-01-20 Alan Modra <amodra@gmail.com>
271 * hppa-dis.c (fput_const): Remove useless cast.
273 2020-01-20 Alan Modra <amodra@gmail.com>
275 * arm-dis.c (print_insn_arm): Wrap 'T' value.
277 2020-01-18 Nick Clifton <nickc@redhat.com>
279 * configure: Regenerate.
280 * po/opcodes.pot: Regenerate.
282 2020-01-18 Nick Clifton <nickc@redhat.com>
284 Binutils 2.34 branch created.
286 2020-01-17 Christian Biesinger <cbiesinger@google.com>
288 * opintl.h: Fix spelling error (seperate).
290 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
292 * i386-opc.tbl: Add {vex} pseudo prefix.
293 * i386-tbl.h: Regenerated.
295 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
298 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
299 (neon_opcodes): Likewise.
300 (select_arm_features): Make sure we enable MVE bits when selecting
301 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
304 2020-01-16 Jan Beulich <jbeulich@suse.com>
306 * i386-opc.tbl: Drop stale comment from XOP section.
308 2020-01-16 Jan Beulich <jbeulich@suse.com>
310 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
311 (extractps): Add VexWIG to SSE2AVX forms.
312 * i386-tbl.h: Re-generate.
314 2020-01-16 Jan Beulich <jbeulich@suse.com>
316 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
317 Size64 from and use VexW1 on SSE2AVX forms.
318 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
319 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
320 * i386-tbl.h: Re-generate.
322 2020-01-15 Alan Modra <amodra@gmail.com>
324 * tic4x-dis.c (tic4x_version): Make unsigned long.
325 (optab, optab_special, registernames): New file scope vars.
326 (tic4x_print_register): Set up registernames rather than
327 malloc'd registertable.
328 (tic4x_disassemble): Delete optable and optable_special. Use
329 optab and optab_special instead. Throw away old optab,
330 optab_special and registernames when info->mach changes.
332 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
335 * z80-dis.c (suffix): Use .db instruction to generate double
338 2020-01-14 Alan Modra <amodra@gmail.com>
340 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
341 values to unsigned before shifting.
343 2020-01-13 Thomas Troeger <tstroege@gmx.de>
345 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
347 (print_insn_thumb16, print_insn_thumb32): Likewise.
348 (print_insn): Initialize the insn info.
349 * i386-dis.c (print_insn): Initialize the insn info fields, and
352 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
354 * arc-opc.c (C_NE): Make it required.
356 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
358 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
359 reserved register name.
361 2020-01-13 Alan Modra <amodra@gmail.com>
363 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
364 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
366 2020-01-13 Alan Modra <amodra@gmail.com>
368 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
369 result of wasm_read_leb128 in a uint64_t and check that bits
370 are not lost when copying to other locals. Use uint32_t for
371 most locals. Use PRId64 when printing int64_t.
373 2020-01-13 Alan Modra <amodra@gmail.com>
375 * score-dis.c: Formatting.
376 * score7-dis.c: Formatting.
378 2020-01-13 Alan Modra <amodra@gmail.com>
380 * score-dis.c (print_insn_score48): Use unsigned variables for
381 unsigned values. Don't left shift negative values.
382 (print_insn_score32): Likewise.
383 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
385 2020-01-13 Alan Modra <amodra@gmail.com>
387 * tic4x-dis.c (tic4x_print_register): Remove dead code.
389 2020-01-13 Alan Modra <amodra@gmail.com>
391 * fr30-ibld.c: Regenerate.
393 2020-01-13 Alan Modra <amodra@gmail.com>
395 * xgate-dis.c (print_insn): Don't left shift signed value.
396 (ripBits): Formatting, use 1u.
398 2020-01-10 Alan Modra <amodra@gmail.com>
400 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
401 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
403 2020-01-10 Alan Modra <amodra@gmail.com>
405 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
406 and XRREG value earlier to avoid a shift with negative exponent.
407 * m10200-dis.c (disassemble): Similarly.
409 2020-01-09 Nick Clifton <nickc@redhat.com>
412 * z80-dis.c (ld_ii_ii): Use correct cast.
414 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
417 * z80-dis.c (ld_ii_ii): Use character constant when checking
420 2020-01-09 Jan Beulich <jbeulich@suse.com>
422 * i386-dis.c (SEP_Fixup): New.
424 (dis386_twobyte): Use it for sysenter/sysexit.
425 (enum x86_64_isa): Change amd64 enumerator to value 1.
426 (OP_J): Compare isa64 against intel64 instead of amd64.
427 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
429 * i386-tbl.h: Re-generate.
431 2020-01-08 Alan Modra <amodra@gmail.com>
433 * z8k-dis.c: Include libiberty.h
434 (instr_data_s): Make max_fetched unsigned.
435 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
436 Don't exceed byte_info bounds.
437 (output_instr): Make num_bytes unsigned.
438 (unpack_instr): Likewise for nibl_count and loop.
439 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
441 * z8k-opc.h: Regenerate.
443 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
445 * arc-tbl.h (llock): Use 'LLOCK' as class.
447 (scond): Use 'SCOND' as class.
449 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
452 2020-01-06 Alan Modra <amodra@gmail.com>
454 * m32c-ibld.c: Regenerate.
456 2020-01-06 Alan Modra <amodra@gmail.com>
459 * z80-dis.c (suffix): Don't use a local struct buffer copy.
460 Peek at next byte to prevent recursion on repeated prefix bytes.
461 Ensure uninitialised "mybuf" is not accessed.
462 (print_insn_z80): Don't zero n_fetch and n_used here,..
463 (print_insn_z80_buf): ..do it here instead.
465 2020-01-04 Alan Modra <amodra@gmail.com>
467 * m32r-ibld.c: Regenerate.
469 2020-01-04 Alan Modra <amodra@gmail.com>
471 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
473 2020-01-04 Alan Modra <amodra@gmail.com>
475 * crx-dis.c (match_opcode): Avoid shift left of signed value.
477 2020-01-04 Alan Modra <amodra@gmail.com>
479 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
481 2020-01-03 Jan Beulich <jbeulich@suse.com>
483 * aarch64-tbl.h (aarch64_opcode_table): Use
484 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
486 2020-01-03 Jan Beulich <jbeulich@suse.com>
488 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
489 forms of SUDOT and USDOT.
491 2020-01-03 Jan Beulich <jbeulich@suse.com>
493 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
495 * opcodes/aarch64-dis-2.c: Re-generate.
497 2020-01-03 Jan Beulich <jbeulich@suse.com>
499 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
501 * opcodes/aarch64-dis-2.c: Re-generate.
503 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
505 * z80-dis.c: Add support for eZ80 and Z80 instructions.
507 2020-01-01 Alan Modra <amodra@gmail.com>
509 Update year range in copyright notice of all files.
511 For older changes see ChangeLog-2019
513 Copyright (C) 2020 Free Software Foundation, Inc.
515 Copying and distribution of this file, with or without modification,
516 are permitted in any medium without royalty provided the copyright
517 notice and this notice are preserved.
523 version-control: never