opcodes/ChangeLog

   1 2017-12-18  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init): Delete OPERAND_TYPE_REGYMM and
   4         OPERAND_TYPE_REGZMM entries.
   5         * i386-opc.h (enum of opcode modifiers): Extend comment.
   6         i386-opc.tbl (vaddpd, vaddps, vaddsubpd, vaddsubps, vandnpd,
   7         vandnps, vandpd, vandps, vblendpd, vblendps, vblendvpd,
   8         vblendvps, vbroadcastss, vcmpeq_ospd, vcmpeq_osps, vcmpeqpd,
   9         vcmpeqps, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uspd, vcmpeq_usps,
  10         vcmpfalse_ospd, vcmpfalse_osps, vcmpfalsepd, vcmpfalseps,
  11         vcmpge_oqpd, vcmpge_oqps, vcmpgepd, vcmpgeps, vcmpgt_oqpd,
  12         vcmpgt_oqps, vcmpgtpd, vcmpgtps, vcmple_oqpd, vcmple_oqps,
  13         vcmplepd, vcmpleps, vcmplt_oqpd, vcmplt_oqps, vcmpltpd,
  14         vcmpltps, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_ospd,
  15         vcmpneq_osps, vcmpneqpd, vcmpneqps, vcmpneq_uspd, vcmpneq_usps,
  16         vcmpngepd, vcmpngeps, vcmpnge_uqpd, vcmpnge_uqps, vcmpngtpd,
  17         vcmpngtps, vcmpngt_uqpd, vcmpngt_uqps, vcmpnlepd, vcmpnleps,
  18         vcmpnle_uqpd, vcmpnle_uqps, vcmpnltpd, vcmpnltps, vcmpnlt_uqpd,
  19         vcmpnlt_uqps, vcmpordpd, vcmpordps, vcmpord_spd, vcmpord_sps,
  20         vcmppd, vcmpps, vcmptruepd, vcmptrueps, vcmptrue_uspd,
  21         vcmptrue_usps, vcmpunordpd, vcmpunordps, vcmpunord_spd,
  22         vcmpunord_sps, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps, vcvtps2dq,
  23         vcvttpd2dq, vcvttps2dq, vdivpd, vdivps, vdpps, vhaddpd, vhaddps,
  24         vhsubpd, vhsubps, vlddqu, vmaskmovpd, vmaskmovps, vmaxpd,
  25         vmaxps, vminpd, vminps, vmovapd, vmovaps, vmovdqa, vmovdqu,
  26         vmovmskpd, vmovmskps, vmovntdq, vmovntpd, vmovntps, vmovshdup,
  27         vmovsldup, vmovupd, vmovups, vmulpd, vmulps, vorpd, vorps,
  28         vpermilpd, vpermilps, vptest, vrcpps, vroundpd, vroundps,
  29         vrsqrtps, vshufpd, vshufps, vsqrtpd, vsqrtps, vsubpd, vsubps,
  30         vtestpd, vtestps, vunpckhpd, vunpckhps, vunpcklpd, vunpcklps,
  31         vxorpd, vxorps, vpblendd, vpbroadcastb, vpbroadcastd,
  32         vpbroadcastw, vpbroadcastq, vpmaskmovd, vpmaskmovq, vpsllvd,
  33         vpsllvq, vpsravd, vpsravq, vpsrlvd, vpsrlvq): Fold 128- and
  34         256-bit forms. Use CheckRegSize instead of IgnoreSize where
  35         appropriate. Drop Xmmword and Ymmword from the results where
  36         possible.
  37         * i386-tbl.h: Re-generate.
  38
  39 2017-12-18  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
  42         RegZMM.
  43         (opcode_modifiers): Drop FirstXmm0.
  44         (operand_types): Replace RegXMM, RegYMM, and RegZMM with just
  45         RegSIMD.
  46         * i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
  47         (struct i386_opcode_modifier): Drop firstxmm0.
  48         (enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
  49         just RegSIMD. Extend comment.
  50         (union i386_operand_type): Replace regxmm, regymm, and regzmm
  51         with just regsimd.
  52         * i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
  53         Acc|Xmmword.
  54         * i386-reg.tbl (xmm0): Add Acc.
  55         * i386-init.h, i386-tbl.h: Re-generate.
  56
  57 2017-12-18  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-gen.c (operand_type_shorthands): Add FloatAcc and
  60         FloatReg.
  61         (operand_types): Drop FloatAcc and FloatReg.
  62         * i386-opc.h (enum of operand types): Likewise. Extend comment.
  63         (union i386_operand_type): Drop floatacc and floatreg.
  64         * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
  65         * i386-init.h, i386-tbl.h: Re-generate.
  66
  67 2017-12-18  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-gen.c (operand_type_shorthands): New.
  70         (opcode_modifiers): Replace Reg<N> with just Reg.
  71         (set_bitfield_from_cpu_flag_init): Rename to
  72         set_bitfield_from_shorthand. Drop value parameter. Process
  73         operand_type_shorthands.
  74         (set_bitfield): Adjust call accordingly.
  75         * i386-opc.h (enum of operand types): Replace Reg<N> with just
  76         Reg.
  77         (union i386_operand_type): Replace reg<N> with just reg.
  78         * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
  79         vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
  80         separate register and memory forms.
  81         * i386-reg.tbl (al): Drop Byte.
  82         (ax): Drop Word.
  83         (eax): Drop Dword.
  84         (rax): Drop Qword.
  85         * i386-init.h, i386-tbl.h: Re-generate.
  86
  87 2017-12-15  Dimitar Dimitrov  <dimitar@dinux.eu>
  88
  89         * disassemble.c (disassemble_init_for_target): Don't put PRU
  90         between powerpc and rs6000 cases.
  91
  92 2017-12-15  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
  95         movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
  96         sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
  97         stos, sub, test, xor): Drop CheckRegSize from variants not
  98         allowing for two (or more) register operands.
  99         * i386-tbl.h: Re-generate.
 100
 101 2017-12-13  Jim Wilson  <jimw@sifive.com>
 102
 103         PR 22599
 104         * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
 105
 106 2017-12-13  Dimitar Dimitrov  <dimitar@dinux.eu>
 107
 108         * disassemble.c: Enable disassembler_needs_relocs for PRU.
 109
 110 2017-12-11  Petr Pavlu  <petr.pavlu@arm.com>
 111             Renlin Li  <renlin.li@arm.com>
 112
 113         * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
 114         (get_sym_code_type): Here.
 115
 116 2017-12-03  Alan Modra  <amodra@gmail.com>
 117
 118         * ppc-opc.c (extract_li20): Rewrite.
 119
 120 2017-12-01  Peter Bergner  <bergner@vnet.ibm.com>
 121
 122         * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
 123         (operand_value_powerpc): Update return and argument type.
 124         <value, top>: Update type.
 125         (skip_optional_operands): Update argument type.
 126         (lookup_powerpc): Likewise.
 127         (lookup_vle): Likewise.
 128         <table_opcd, table_mask, insn2>: Update type.
 129         (lookup_spe2): Update argument type.
 130         <table_opcd, table_mask, insn2>: Update type.
 131         (print_insn_powerpc) <insn, value>: Update type.
 132         Use PPC_INT_FMT for printing instructions and operands.
 133         * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
 134         insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
 135         insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
 136         extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
 137         extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
 138         insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
 139         extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
 140         insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
 141         extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
 142         insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
 143         extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
 144         insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
 145         extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
 146         insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
 147         extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
 148         insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
 149         extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
 150         insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
 151         extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
 152         extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
 153         extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
 154         insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
 155         extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
 156         insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
 157         extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
 158         extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
 159         (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
 160         BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
 161         DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
 162         SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
 163         VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
 164         VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
 165         VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
 166         XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
 167         XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
 168         XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
 169         XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
 170
 171 2017-11-29  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
 174         New.
 175         (output_cpu_flags): Update active_cpu_flags.
 176         (process_i386_opcode_modifier): Update active_isstring.
 177         (output_operand_type): Rename "macro"   parameter to "stage",
 178         changing its type.
 179         (process_i386_operand_type): Likewise. Track presence of
 180         BaseIndex and emit DispN accordingly.
 181         (output_i386_opcode, process_i386_registers,
 182         process_i386_initializers): Adjust calls to
 183         process_i386_operand_type() for its changed parameter type.
 184         * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
 185         all insns operands having BaseIndex set.
 186         * i386-tbl.h: Re-generate.
 187
 188 2017-11-29  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
 191         entry.
 192         (operand_types): Remove Vec_Disp8 entry.
 193         * i386-opc.h (Vec_Disp8): Delete.
 194         (union i386_operand_type): Remove vec_disp8.
 195         (i386-opc.tbl): Remove Vec_Disp8.
 196         * i386-init.h, i386-tbl.h: Re-generate.
 197
 198 2017-11-29  Stefan Stroe  <stroestefan@gmail.com>
 199
 200         * po/Make-in (datadir): Define as @datadir@.
 201         (localedir): Define as @localedir@.
 202         (gnulocaledir, gettextsrcdir): Use @datarootdir@.
 203
 204 2017-11-27  Nick Clifton  <nickc@redhat.com>
 205
 206         * po/zh_CN.po: Updated simplified Chinese translation.
 207
 208 2017-11-24  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
 211         "df" groups.
 212
 213 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 214
 215         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
 216         * i386-tbl.h: Regenerate.
 217
 218 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
 221         the 16-bit addressing case.
 222
 223 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
 226         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
 227         * i386-opc.tbl (ud1, ud2b): Add operands.
 228         (ud0): New.
 229         * i386-tbl.h: Re-generate.
 230
 231 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 232
 233         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
 234         * i386-tbl.h: Regenerate.
 235
 236 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 237
 238         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
 239         * i386-tbl.h: Regenerate.
 240
 241 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 242
 243         *arc-opc (insert_rhv2): Check h-regs range.
 244
 245 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
 246
 247         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
 248         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
 249
 250 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 251
 252         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
 253         and AARCH64_FEATURE_F16.
 254
 255 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 256
 257         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
 258         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
 259         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
 260         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
 261         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
 262         (ldapur, ldapursw, stlur): New.
 263         * aarch64-dis-2.c: Regenerate.
 264
 265 2017-11-16  Jan Beulich  <jbeulich@suse.com>
 266
 267         (get_valid_dis386): Never flag bad opcode when
 268         vex.register_specifier is beyond 7. Always store all four
 269         bits of it. Move 16-/32-bit override in EVEX handling after
 270         all to be overridden bits have been set.
 271         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
 272         Use rex to determine GPR register set.
 273         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
 274         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
 275
 276 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
 279         determine GPR register set.
 280
 281 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
 284         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
 285         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
 286         pass.
 287         (OP_REG_VexI4): Drop low 4 bits check.
 288
 289 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-reg.tbl (axl): Remove Acc and Byte.
 292         * i386-tbl.h: Re-generate.
 293
 294 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
 297         (vex_len_table): Use VPCOM.
 298
 299 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
 302         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
 303         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
 304         vpcmpw): Move up.
 305         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
 306         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 307         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 308         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 309         vpcmpnltuw): New.
 310         * i386-tbl.h: Re-generate.
 311
 312 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 315         smov, ssca, stos, ssto, xlat): Drop Disp*.
 316         * i386-tbl.h: Re-generate.
 317
 318 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 321         xsaveopt64): Add No_qSuf.
 322         * i386-tbl.h: Re-generate.
 323
 324 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 325
 326         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 327         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 328         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 329         sder32_el2, vncr_el2.
 330         (aarch64_sys_reg_supported_p): Likewise.
 331         (aarch64_pstatefields): Add dit register.
 332         (aarch64_pstatefield_supported_p): Likewise.
 333         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 334         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 335         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 336         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 337         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 338         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 339         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 340
 341 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 342
 343         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 344         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 345         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 346         (QL_STLW, QL_STLX): New.
 347
 348 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 349
 350         * aarch64-asm.h (ins_addr_offset): New.
 351         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 352         (aarch64_ins_addr_offset): New.
 353         * aarch64-asm-2.c: Regenerate.
 354         * aarch64-dis.h (ext_addr_offset): New.
 355         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 356         (aarch64_ext_addr_offset): New.
 357         * aarch64-dis-2.c: Regenerate.
 358         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 359         FLD_imm4_2 and FLD_SM3_imm2.
 360         * aarch64-opc.c (fields): Add FLD_imm6_2,
 361         FLD_imm4_2 and FLD_SM3_imm2.
 362         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 363         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 364         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 365         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 366         * aarch64-tbl.h
 367         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 368
 369 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 370
 371         * aarch64-tbl.h
 372         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 373         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 374         (aarch64_feature_fp_16_v8_2): New.
 375         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 376         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 377         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 378
 379 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 380
 381         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 382         (aarch64_feature_sha2, aarch64_feature_aes): New.
 383         (SHA2, AES): New.
 384         (AES_INSN, SHA2_INSN): New.
 385         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 386         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 387          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 388         Change to SHA2_INS.
 389
 390 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 391             Tamar Christina <tamar.christina@arm.com>
 392
 393         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 394         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 395
 396 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 397
 398         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 399
 400 2017-11-07  Alan Modra  <amodra@gmail.com>
 401
 402         * opintl.h: Formatting, comment fixes.
 403         (gettext, ngettext): Redefine when ENABLE_NLS.
 404         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 405         (_): Define using gettext.
 406         (textdomain, bindtextdomain): Use safer "do nothing".
 407
 408 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 409
 410         * arc-dis.c (print_hex): New variable.
 411         (parse_option): Check for hex option.
 412         (print_insn_arc): Use hexadecimal representation for short
 413         immediate values when requested.
 414         (print_arc_disassembler_options): Add hex option to the list.
 415
 416 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 417
 418         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 419         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 420         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 421         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 422         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 423         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 424         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 425         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 426         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 427         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 428         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 429         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 430         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 431         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 432         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 433         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 434         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 435         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 436         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 437         Changed opcodes.
 438         (prealloc, prefetch*): Place them before ld instruction.
 439         * arc-opc.c (skip_this_opcode): Add ARITH class.
 440
 441 2017-10-25  Alan Modra  <amodra@gmail.com>
 442
 443         PR 22348
 444         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 445         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 446         (imm4flag, size_changed): Likewise.
 447         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 448         (words, allWords, processing_argument_number): Likewise.
 449         (cst4flag, size_changed): Likewise.
 450         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 451         (crx_cst4_maps): Rename from cst4_maps.
 452         (crx_no_op_insn): Rename from no_op_insn.
 453
 454 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 455
 456         * riscv-opc.c (match_c_addi16sp) : New function.
 457         (match_c_addi4spn): New function.
 458         (match_c_lui): Don't allow 0-immediate encodings.
 459         (riscv_opcodes) <addi>: Use the above functions.
 460         <add>: Likewise.
 461         <c.addi4spn>: Likewise.
 462         <c.addi16sp>: Likewise.
 463
 464 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 465
 466         * i386-init.h: Regenerate
 467         * i386-tbl.h: Likewise
 468
 469 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 470
 471         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 472         (enum): Add EVEX_W_0F3854_P_2.
 473         * i386-dis-evex.h (evex_table): Updated.
 474         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 475         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 476         (cpu_flags): Add CpuAVX512_BITALG.
 477         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 478         (i386_cpu_flags): Add cpuavx512_bitalg..
 479         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 480         * i386-init.h: Regenerate.
 481         * i386-tbl.h: Likewise.
 482
 483 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 484
 485         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 486         * i386-dis-evex.h (evex_table): Updated.
 487         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 488         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 489         (cpu_flags): Add CpuAVX512_VNNI.
 490         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 491         (i386_cpu_flags): Add cpuavx512_vnni.
 492         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 493         * i386-init.h: Regenerate.
 494         * i386-tbl.h: Likewise.
 495
 496 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 497
 498         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 499         (enum): Remove VEX_LEN_0F3A44_P_2.
 500         (vex_len_table): Ditto.
 501         (enum): Remove VEX_W_0F3A44_P_2.
 502         (vew_w_table): Ditto.
 503         (prefix_table): Adjust instructions (see prefixes above).
 504         * i386-dis-evex.h (evex_table):
 505         Add new instructions (see prefixes above).
 506         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 507         (bitfield_cpu_flags): Ditto.
 508         * i386-opc.h (enum): Ditto.
 509         (i386_cpu_flags): Ditto.
 510         (CpuUnused): Comment out to avoid zero-width field problem.
 511         * i386-opc.tbl (vpclmulqdq): New instruction.
 512         * i386-init.h: Regenerate.
 513         * i386-tbl.h: Ditto.
 514
 515 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 516
 517         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 518         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 519         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 520         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 521         (vex_len_table): Ditto.
 522         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 523         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 524         (vew_w_table): Ditto.
 525         (prefix_table): Adjust instructions (see prefixes above).
 526         * i386-dis-evex.h (evex_table):
 527         Add new instructions (see prefixes above).
 528         * i386-gen.c (cpu_flag_init): Add VAES.
 529         (bitfield_cpu_flags): Ditto.
 530         * i386-opc.h (enum): Ditto.
 531         (i386_cpu_flags): Ditto.
 532         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 533         * i386-init.h: Regenerate.
 534         * i386-tbl.h: Ditto.
 535
 536 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 537
 538         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 539         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 540         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 541         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 542         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 543         (prefix_table): Updated (see prefixes above).
 544         (three_byte_table): Likewise.
 545         (vex_w_table): Likewise.
 546         * i386-dis-evex.h: Likewise.
 547         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 548         (cpu_flags): Add CpuGFNI.
 549         * i386-opc.h (enum): Add CpuGFNI.
 550         (i386_cpu_flags): Add cpugfni.
 551         * i386-opc.tbl: Add Intel GFNI instructions.
 552         * i386-init.h: Regenerate.
 553         * i386-tbl.h: Likewise.
 554
 555 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 556
 557         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 558         Define EXbScalar and EXwScalar for OP_EX.
 559         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 560         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 561         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 562         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 563         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 564         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 565         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 566         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 567         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 568         (OP_E_memory): Likewise.
 569         * i386-dis-evex.h: Updated.
 570         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 571         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 572         (cpu_flags): Add CpuAVX512_VBMI2.
 573         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 574         (i386_cpu_flags): Add cpuavx512_vbmi2.
 575         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 576         * i386-init.h: Regenerate.
 577         * i386-tbl.h: Likewise.
 578
 579 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 580
 581         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 582
 583 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 584
 585         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 586         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 587         K15. Add jmpix pattern.
 588
 589 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 590
 591         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 592
 593 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 594
 595         * s390-opc.c (INSTR_SI_RD): New macro.
 596         (INSTR_S_RD): Adjust example instruction.
 597         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 598         SI_RD.
 599
 600 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 601
 602         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 603         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 604         VLE multimple load/store instructions. Old e_ldm* variants are
 605         kept as aliases.
 606         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 607
 608 2017-09-27  Nick Clifton  <nickc@redhat.com>
 609
 610         PR 22179
 611         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 612         names for the fmv.x.s and fmv.s.x instructions respectively.
 613
 614 2017-09-26  do  <do@nerilex.org>
 615
 616         PR 22123
 617         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 618         be used on CPUs that have emacs support.
 619
 620 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 621
 622         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 623
 624 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 625
 626         * nds32-asm.c: Rename __BIT() to N32_BIT().
 627         * nds32-asm.h: Likewise.
 628         * nds32-dis.c: Likewise.
 629
 630 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 631
 632         * i386-dis.c (last_active_prefix): Removed.
 633         (ckprefix): Don't set last_active_prefix.
 634         (NOTRACK_Fixup): Don't check last_active_prefix.
 635
 636 2017-08-31  Nick Clifton  <nickc@redhat.com>
 637
 638         * po/fr.po: Updated French translation.
 639
 640 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 641
 642         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 643         fields.
 644
 645 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 646             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 647
 648         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 649         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 650         New entries efs2 and spe2.
 651         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 652         (SPE2_OPCD_SEGS): New macro.
 653         (spe2_opcd_indices): New.
 654         (disassemble_init_powerpc): Handle SPE2 opcodes.
 655         (lookup_spe2): New function.
 656         (print_insn_powerpc): call lookup_spe2.
 657         * ppc-opc.c (insert_evuimm1_ex0): New function.
 658         (extract_evuimm1_ex0): Likewise.
 659         (insert_evuimm_lt8): Likewise.
 660         (extract_evuimm_lt8): Likewise.
 661         (insert_off_spe2): Likewise.
 662         (extract_off_spe2): Likewise.
 663         (insert_Ddd): Likewise.
 664         (extract_Ddd): Likewise.
 665         (DD): New operand.
 666         (EVUIMM_LT8): Likewise.
 667         (EVUIMM_LT16): Adjust.
 668         (MMMM): New operand.
 669         (EVUIMM_1): Likewise.
 670         (EVUIMM_1_EX0): Likewise.
 671         (EVUIMM_2): Adjust.
 672         (NNN): New operand.
 673         (VX_OFF_SPE2): Likewise.
 674         (BBB): Likewise.
 675         (DDD): Likewise.
 676         (VX_MASK_DDD): New mask.
 677         (HH): New operand.
 678         (VX_RA_CONST): New macro.
 679         (VX_RA_CONST_MASK): Likewise.
 680         (VX_RB_CONST): Likewise.
 681         (VX_RB_CONST_MASK): Likewise.
 682         (VX_OFF_SPE2_MASK): Likewise.
 683         (VX_SPE_CRFD): Likewise.
 684         (VX_SPE_CRFD_MASK VX): Likewise.
 685         (VX_SPE2_CLR): Likewise.
 686         (VX_SPE2_CLR_MASK): Likewise.
 687         (VX_SPE2_SPLATB): Likewise.
 688         (VX_SPE2_SPLATB_MASK): Likewise.
 689         (VX_SPE2_OCTET): Likewise.
 690         (VX_SPE2_OCTET_MASK): Likewise.
 691         (VX_SPE2_DDHH): Likewise.
 692         (VX_SPE2_DDHH_MASK): Likewise.
 693         (VX_SPE2_HH): Likewise.
 694         (VX_SPE2_HH_MASK): Likewise.
 695         (VX_SPE2_EVMAR): Likewise.
 696         (VX_SPE2_EVMAR_MASK): Likewise.
 697         (PPCSPE2): Likewise.
 698         (PPCEFS2): Likewise.
 699         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 700         (powerpc_macros): Map old SPE instructions have new names
 701         with the same opcodes. Add SPE2 instructions which just are
 702         mapped to SPE2.
 703         (spe2_opcodes): Add SPE2 opcodes.
 704
 705 2017-08-23  Alan Modra  <amodra@gmail.com>
 706
 707         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 708         extract functions earlier, deleting forward declarations.
 709         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 710         RA_MASK.
 711
 712 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 713
 714         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 715
 716 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 717             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 718
 719         * ppc-opc.c (insert_evuimm2_ex0): New function.
 720         (extract_evuimm2_ex0): Likewise.
 721         (insert_evuimm4_ex0): Likewise.
 722         (extract_evuimm4_ex0): Likewise.
 723         (insert_evuimm8_ex0): Likewise.
 724         (extract_evuimm8_ex0): Likewise.
 725         (insert_evuimm_lt16): Likewise.
 726         (extract_evuimm_lt16): Likewise.
 727         (insert_rD_rS_even): Likewise.
 728         (extract_rD_rS_even): Likewise.
 729         (insert_off_lsp): Likewise.
 730         (extract_off_lsp): Likewise.
 731         (RD_EVEN): New operand.
 732         (RS_EVEN): Likewise.
 733         (RSQ): Adjust.
 734         (EVUIMM_LT16): New operand.
 735         (HTM_SI): Adjust.
 736         (EVUIMM_2_EX0): New operand.
 737         (EVUIMM_4): Adjust.
 738         (EVUIMM_4_EX0): New operand.
 739         (EVUIMM_8): Adjust.
 740         (EVUIMM_8_EX0): New operand.
 741         (WS): Adjust.
 742         (VX_OFF): New operand.
 743         (VX_LSP): New macro.
 744         (VX_LSP_MASK): Likewise.
 745         (VX_LSP_OFF_MASK): Likewise.
 746         (PPC_OPCODE_LSP): Likewise.
 747         (vle_opcodes): Add LSP opcodes.
 748         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 749
 750 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 751
 752         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 753         register operands in CRC instructions.
 754         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 755         comments.
 756
 757 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 758
 759         * disassemble.c (disassembler): Mark big and mach with
 760         ATTRIBUTE_UNUSED.
 761
 762 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 763
 764         * disassemble.c (disassembler): Remove arch/mach/endian
 765         assertions.
 766
 767 2017-07-25  Nick Clifton  <nickc@redhat.com>
 768
 769         PR 21739
 770         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 771         message.
 772         (insert_r0): Likewise.
 773         (insert_r1): Likewise.
 774         (insert_r2): Likewise.
 775         (insert_r3): Likewise.
 776         (insert_sp): Likewise.
 777         (insert_gp): Likewise.
 778         (insert_pcl): Likewise.
 779         (insert_blink): Likewise.
 780         (insert_ilink1): Likewise.
 781         (insert_ilink2): Likewise.
 782         (insert_ras): Likewise.
 783         (insert_rbs): Likewise.
 784         (insert_rcs): Likewise.
 785         (insert_simm3s): Likewise.
 786         (insert_rrange): Likewise.
 787         (insert_r13el): Likewise.
 788         (insert_fpel): Likewise.
 789         (insert_blinkel): Likewise.
 790         (insert_pclel): Likewise.
 791         (insert_nps_bitop_size_2b): Likewise.
 792         (insert_nps_imm_offset): Likewise.
 793         (insert_nps_imm_entry): Likewise.
 794         (insert_nps_size_16bit): Likewise.
 795         (insert_nps_##NAME##_pos): Likewise.
 796         (insert_nps_##NAME): Likewise.
 797         (insert_nps_bitop_ins_ext): Likewise.
 798         (insert_nps_##NAME): Likewise.
 799         (insert_nps_min_hofs): Likewise.
 800         (insert_nps_##NAME): Likewise.
 801         (insert_nps_rbdouble_64): Likewise.
 802         (insert_nps_misc_imm_offset): Likewise.
 803         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 804         option description.
 805
 806 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 807             Jiong Wang  <jiong.wang@arm.com>
 808
 809         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 810         correct the print.
 811         * aarch64-dis-2.c: Regenerated.
 812
 813 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 814
 815         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 816         table.
 817
 818 2017-07-20  Nick Clifton  <nickc@redhat.com>
 819
 820         * po/de.po: Updated German translation.
 821
 822 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 823
 824         * arc-regs.h (sec_stat): New aux register.
 825         (aux_kernel_sp): Likewise.
 826         (aux_sec_u_sp): Likewise.
 827         (aux_sec_k_sp): Likewise.
 828         (sec_vecbase_build): Likewise.
 829         (nsc_table_top): Likewise.
 830         (nsc_table_base): Likewise.
 831         (ersec_stat): Likewise.
 832         (aux_sec_except): Likewise.
 833
 834 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 835
 836         * arc-opc.c (extract_uimm12_20): New function.
 837         (UIMM12_20): New operand.
 838         (SIMM3_5_S): Adjust.
 839         * arc-tbl.h (sjli): Add new instruction.
 840
 841 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 842             John Eric Martin  <John.Martin@emmicro-us.com>
 843
 844         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 845         (UIMM3_23): Adjust accordingly.
 846         * arc-regs.h: Add/correct jli_base register.
 847         * arc-tbl.h (jli_s): Likewise.
 848
 849 2017-07-18  Nick Clifton  <nickc@redhat.com>
 850
 851         PR 21775
 852         * aarch64-opc.c: Fix spelling typos.
 853         * i386-dis.c: Likewise.
 854
 855 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 856
 857         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 858         max_addr_offset and octets variables to size_t.
 859
 860 2017-07-12  Alan Modra  <amodra@gmail.com>
 861
 862         * po/da.po: Update from translationproject.org/latest/opcodes/.
 863         * po/de.po: Likewise.
 864         * po/es.po: Likewise.
 865         * po/fi.po: Likewise.
 866         * po/fr.po: Likewise.
 867         * po/id.po: Likewise.
 868         * po/it.po: Likewise.
 869         * po/nl.po: Likewise.
 870         * po/pt_BR.po: Likewise.
 871         * po/ro.po: Likewise.
 872         * po/sv.po: Likewise.
 873         * po/tr.po: Likewise.
 874         * po/uk.po: Likewise.
 875         * po/vi.po: Likewise.
 876         * po/zh_CN.po: Likewise.
 877
 878 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 879             Alan Modra  <amodra@gmail.com>
 880
 881         * cgen.sh: Mark generated files read-only.
 882         * epiphany-asm.c: Regenerate.
 883         * epiphany-desc.c: Regenerate.
 884         * epiphany-desc.h: Regenerate.
 885         * epiphany-dis.c: Regenerate.
 886         * epiphany-ibld.c: Regenerate.
 887         * epiphany-opc.c: Regenerate.
 888         * epiphany-opc.h: Regenerate.
 889         * fr30-asm.c: Regenerate.
 890         * fr30-desc.c: Regenerate.
 891         * fr30-desc.h: Regenerate.
 892         * fr30-dis.c: Regenerate.
 893         * fr30-ibld.c: Regenerate.
 894         * fr30-opc.c: Regenerate.
 895         * fr30-opc.h: Regenerate.
 896         * frv-asm.c: Regenerate.
 897         * frv-desc.c: Regenerate.
 898         * frv-desc.h: Regenerate.
 899         * frv-dis.c: Regenerate.
 900         * frv-ibld.c: Regenerate.
 901         * frv-opc.c: Regenerate.
 902         * frv-opc.h: Regenerate.
 903         * ip2k-asm.c: Regenerate.
 904         * ip2k-desc.c: Regenerate.
 905         * ip2k-desc.h: Regenerate.
 906         * ip2k-dis.c: Regenerate.
 907         * ip2k-ibld.c: Regenerate.
 908         * ip2k-opc.c: Regenerate.
 909         * ip2k-opc.h: Regenerate.
 910         * iq2000-asm.c: Regenerate.
 911         * iq2000-desc.c: Regenerate.
 912         * iq2000-desc.h: Regenerate.
 913         * iq2000-dis.c: Regenerate.
 914         * iq2000-ibld.c: Regenerate.
 915         * iq2000-opc.c: Regenerate.
 916         * iq2000-opc.h: Regenerate.
 917         * lm32-asm.c: Regenerate.
 918         * lm32-desc.c: Regenerate.
 919         * lm32-desc.h: Regenerate.
 920         * lm32-dis.c: Regenerate.
 921         * lm32-ibld.c: Regenerate.
 922         * lm32-opc.c: Regenerate.
 923         * lm32-opc.h: Regenerate.
 924         * lm32-opinst.c: Regenerate.
 925         * m32c-asm.c: Regenerate.
 926         * m32c-desc.c: Regenerate.
 927         * m32c-desc.h: Regenerate.
 928         * m32c-dis.c: Regenerate.
 929         * m32c-ibld.c: Regenerate.
 930         * m32c-opc.c: Regenerate.
 931         * m32c-opc.h: Regenerate.
 932         * m32r-asm.c: Regenerate.
 933         * m32r-desc.c: Regenerate.
 934         * m32r-desc.h: Regenerate.
 935         * m32r-dis.c: Regenerate.
 936         * m32r-ibld.c: Regenerate.
 937         * m32r-opc.c: Regenerate.
 938         * m32r-opc.h: Regenerate.
 939         * m32r-opinst.c: Regenerate.
 940         * mep-asm.c: Regenerate.
 941         * mep-desc.c: Regenerate.
 942         * mep-desc.h: Regenerate.
 943         * mep-dis.c: Regenerate.
 944         * mep-ibld.c: Regenerate.
 945         * mep-opc.c: Regenerate.
 946         * mep-opc.h: Regenerate.
 947         * mt-asm.c: Regenerate.
 948         * mt-desc.c: Regenerate.
 949         * mt-desc.h: Regenerate.
 950         * mt-dis.c: Regenerate.
 951         * mt-ibld.c: Regenerate.
 952         * mt-opc.c: Regenerate.
 953         * mt-opc.h: Regenerate.
 954         * or1k-asm.c: Regenerate.
 955         * or1k-desc.c: Regenerate.
 956         * or1k-desc.h: Regenerate.
 957         * or1k-dis.c: Regenerate.
 958         * or1k-ibld.c: Regenerate.
 959         * or1k-opc.c: Regenerate.
 960         * or1k-opc.h: Regenerate.
 961         * or1k-opinst.c: Regenerate.
 962         * xc16x-asm.c: Regenerate.
 963         * xc16x-desc.c: Regenerate.
 964         * xc16x-desc.h: Regenerate.
 965         * xc16x-dis.c: Regenerate.
 966         * xc16x-ibld.c: Regenerate.
 967         * xc16x-opc.c: Regenerate.
 968         * xc16x-opc.h: Regenerate.
 969         * xstormy16-asm.c: Regenerate.
 970         * xstormy16-desc.c: Regenerate.
 971         * xstormy16-desc.h: Regenerate.
 972         * xstormy16-dis.c: Regenerate.
 973         * xstormy16-ibld.c: Regenerate.
 974         * xstormy16-opc.c: Regenerate.
 975         * xstormy16-opc.h: Regenerate.
 976
 977 2017-07-07  Alan Modra  <amodra@gmail.com>
 978
 979         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 980         * m32c-dis.c: Regenerate.
 981         * mep-dis.c: Regenerate.
 982
 983 2017-07-05  Borislav Petkov  <bp@suse.de>
 984
 985         * i386-dis.c: Enable ModRM.reg /6 aliases.
 986
 987 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 988
 989         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 990         with vmrs and vmsr.
 991
 992 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 993
 994         * configure: Regenerate.
 995
 996 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 997
 998         * po/opcodes.pot: Regenerate.
 999
1000 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
1001
1002         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
1003         entries to the MSA ASE instruction block.
1004
1005 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
1006             Maciej W. Rozycki  <macro@imgtec.com>
1007
1008         * micromips-opc.c (XPA, XPAVZ): New macros.
1009         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
1010         "mthgc0".
1011
1012 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
1013             Maciej W. Rozycki  <macro@imgtec.com>
1014
1015         * micromips-opc.c (I36): New macro.
1016         (micromips_opcodes): Add "eretnc".
1017
1018 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
1019             Andrew Bennett  <andrew.bennett@imgtec.com>
1020
1021         * mips-dis.c (mips_calculate_combination_ases): Handle the
1022         ASE_XPA_VIRT flag.
1023         (parse_mips_ase_option): New function.
1024         (parse_mips_dis_option): Factor out ASE option handling to the
1025         new function.  Call `mips_calculate_combination_ases'.
1026         * mips-opc.c (XPAVZ): New macro.
1027         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
1028         "mfhgc0", "mthc0" and "mthgc0".
1029
1030 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
1031
1032         * mips-dis.c (mips_calculate_combination_ases): New function.
1033         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
1034         calculation to the new function.
1035         (set_default_mips_dis_options): Call the new function.
1036
1037 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1038
1039         * arc-dis.c (parse_disassembler_options): Use
1040         FOR_EACH_DISASSEMBLER_OPTION.
1041
1042 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1043
1044         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
1045         disassembler option strings.
1046         (parse_cpu_option): Likewise.
1047
1048 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
1049
1050         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
1051         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
1052         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
1053         (aarch64_feature_dotprod, DOT_INSN): New.
1054         (udot, sdot): New.
1055         * aarch64-dis-2.c: Regenerated.
1056
1057 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
1058
1059         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1060
1061 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
1062             Matthew Fortune  <matthew.fortune@imgtec.com>
1063             Andrew Bennett  <andrew.bennett@imgtec.com>
1064
1065         * mips-formats.h (INT_BIAS): New macro.
1066         (INT_ADJ): Redefine in INT_BIAS terms.
1067         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1068         (mips_print_save_restore): New function.
1069         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1070         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1071         call.
1072         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1073         (print_mips16_insn_arg): Call `mips_print_save_restore' for
1074         OP_SAVE_RESTORE_LIST handling, factored out from here.
1075         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1076         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1077         (mips_builtin_opcodes): Add "restore" and "save" entries.
1078         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1079         (IAMR2): New macro.
1080         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1081
1082 2017-06-23  Andrew Waterman  <andrew@sifive.com>
1083
1084         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1085         alias; do not mark SLTI instruction as an alias.
1086
1087 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1088
1089         * i386-dis.c (RM_0FAE_REG_5): Removed.
1090         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1091         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1092         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1093         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
1094         PREFIX_MOD_3_0F01_REG_5_RM_0.
1095         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
1096         PREFIX_MOD_3_0FAE_REG_5.
1097         (mod_table): Update MOD_0FAE_REG_5.
1098         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
1099         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1100         * i386-tbl.h: Regenerated.
1101
1102 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1103
1104         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1105         * i386-opc.tbl: Likewise.
1106         * i386-tbl.h: Regenerated.
1107
1108 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1109
1110         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1111         and "jmp{&|}".
1112         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1113         prefix.
1114
1115 2017-06-19  Nick Clifton  <nickc@redhat.com>
1116
1117         PR binutils/21614
1118         * score-dis.c (score_opcodes): Add sentinel.
1119
1120 2017-06-16  Alan Modra  <amodra@gmail.com>
1121
1122         * rx-decode.c: Regenerate.
1123
1124 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
1125
1126         PR binutils/21594
1127         * i386-dis.c (OP_E_register): Check valid bnd register.
1128         (OP_G): Likewise.
1129
1130 2017-06-15  Nick Clifton  <nickc@redhat.com>
1131
1132         PR binutils/21595
1133         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1134         range value.
1135
1136 2017-06-15  Nick Clifton  <nickc@redhat.com>
1137
1138         PR binutils/21588
1139         * rl78-decode.opc (OP_BUF_LEN): Define.
1140         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1141         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1142         array.
1143         * rl78-decode.c: Regenerate.
1144
1145 2017-06-15  Nick Clifton  <nickc@redhat.com>
1146
1147         PR binutils/21586
1148         * bfin-dis.c (gregs): Clip index to prevent overflow.
1149         (regs): Likewise.
1150         (regs_lo): Likewise.
1151         (regs_hi): Likewise.
1152
1153 2017-06-14  Nick Clifton  <nickc@redhat.com>
1154
1155         PR binutils/21576
1156         * score7-dis.c (score_opcodes): Add sentinel.
1157
1158 2017-06-14  Yao Qi  <yao.qi@linaro.org>
1159
1160         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1161         * arm-dis.c: Likewise.
1162         * ia64-dis.c: Likewise.
1163         * mips-dis.c: Likewise.
1164         * spu-dis.c: Likewise.
1165         * disassemble.h (print_insn_aarch64): New declaration, moved from
1166         include/dis-asm.h.
1167         (print_insn_big_arm, print_insn_big_mips): Likewise.
1168         (print_insn_i386, print_insn_ia64): Likewise.
1169         (print_insn_little_arm, print_insn_little_mips): Likewise.
1170
1171 2017-06-14  Nick Clifton  <nickc@redhat.com>
1172
1173         PR binutils/21587
1174         * rx-decode.opc: Include libiberty.h
1175         (GET_SCALE): New macro - validates access to SCALE array.
1176         (GET_PSCALE): New macro - validates access to PSCALE array.
1177         (DIs, SIs, S2Is, rx_disp): Use new macros.
1178         * rx-decode.c: Regenerate.
1179
1180 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1181
1182         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1183
1184 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
1185
1186         * arc-dis.c (enforced_isa_mask): Declare.
1187         (cpu_types): Likewise.
1188         (parse_cpu_option): New function.
1189         (parse_disassembler_options): Use it.
1190         (print_insn_arc): Use enforced_isa_mask.
1191         (print_arc_disassembler_options): Document new options.
1192
1193 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1194
1195         * alpha-dis.c: Include disassemble.h, don't include
1196         dis-asm.h.
1197         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1198         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1199         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1200         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1201         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1202         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1203         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1204         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1205         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1206         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1207         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1208         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1209         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1210         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1211         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1212         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1213         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1214         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1215         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1216         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1217         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1218         * z80-dis.c, z8k-dis.c: Likewise.
1219         * disassemble.h: New file.
1220
1221 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1222
1223         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1224         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1225
1226 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1227
1228         * disassemble.c (disassembler): Add arguments a, big and mach.
1229         Use them.
1230
1231 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1232
1233         * i386-dis.c (NOTRACK_Fixup): New.
1234         (NOTRACK): Likewise.
1235         (NOTRACK_PREFIX): Likewise.
1236         (last_active_prefix): Likewise.
1237         (reg_table): Use NOTRACK on indirect call and jmp.
1238         (ckprefix): Set last_active_prefix.
1239         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1240         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1241         * i386-opc.h (NoTrackPrefixOk): New.
1242         (i386_opcode_modifier): Add notrackprefixok.
1243         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1244         Add notrack.
1245         * i386-tbl.h: Regenerated.
1246
1247 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1248
1249         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1250         (X_IMM2): Define.
1251         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1252         bfd_mach_sparc_v9m8.
1253         (print_insn_sparc): Handle new operand types.
1254         * sparc-opc.c (MASK_M8): Define.
1255         (v6): Add MASK_M8.
1256         (v6notlet): Likewise.
1257         (v7): Likewise.
1258         (v8): Likewise.
1259         (v9): Likewise.
1260         (v9a): Likewise.
1261         (v9b): Likewise.
1262         (v9c): Likewise.
1263         (v9d): Likewise.
1264         (v9e): Likewise.
1265         (v9v): Likewise.
1266         (v9m): Likewise.
1267         (v9andleon): Likewise.
1268         (m8): Define.
1269         (HWS_VM8): Define.
1270         (HWS2_VM8): Likewise.
1271         (sparc_opcode_archs): Add entry for "m8".
1272         (sparc_opcodes): Add OSA2017 and M8 instructions
1273         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1274         fpx{ll,ra,rl}64x,
1275         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1276         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1277         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1278         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1279         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1280         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1281         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1282         ASI_CORE_SELECT_COMMIT_NHT.
1283
1284 2017-05-18  Alan Modra  <amodra@gmail.com>
1285
1286         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1287         * aarch64-dis.c: Likewise.
1288         * aarch64-gen.c: Likewise.
1289         * aarch64-opc.c: Likewise.
1290
1291 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1292             Matthew Fortune  <matthew.fortune@imgtec.com>
1293
1294         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1295         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1296         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1297         (print_insn_arg) <OP_REG28>: Add handler.
1298         (validate_insn_args) <OP_REG28>: Handle.
1299         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1300         32-bit encoding and 9-bit immediates.
1301         (print_insn_mips16): Handle MIPS16 instructions that require
1302         32-bit encoding and MFC0/MTC0 operand decoding.
1303         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1304         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1305         (RD_C0, WR_C0, E2, E2MT): New macros.
1306         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1307         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1308         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1309         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1310         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1311         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1312         instructions, "swl", "swr", "sync" and its "sync_acquire",
1313         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1314         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1315         regular/extended entries for original MIPS16 ISA revision
1316         instructions whose extended forms are subdecoded in the MIPS16e2
1317         ISA revision: "li", "sll" and "srl".
1318
1319 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1320
1321         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1322         reference in CP0 move operand decoding.
1323
1324 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1325
1326         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1327         type to hexadecimal.
1328         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1329
1330 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1331
1332         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1333         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1334         "sync_rmb" and "sync_wmb" as aliases.
1335         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1336         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1337
1338 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1339
1340         * arc-dis.c (parse_option): Update quarkse_em option..
1341         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1342         QUARKSE1.
1343         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1344
1345 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1346
1347         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1348
1349 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1350
1351         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1352         register.
1353
1354 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1355
1356         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1357         and branches and not synthetic data instructions.
1358
1359 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1360
1361         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1362
1363 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1364
1365         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1366         * arc-opc.c (insert_r13el): New function.
1367         (R13_EL): Define.
1368         * arc-tbl.h: Add new enter/leave variants.
1369
1370 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1371
1372         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1373
1374 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1375
1376         * mips-dis.c (print_mips_disassembler_options): Add
1377         `no-aliases'.
1378
1379 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1380
1381         * mips16-opc.c (AL): New macro.
1382         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1383         of "ld" and "lw" as aliases.
1384
1385 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1386
1387         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1388         arguments.
1389
1390 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1391             Alan Modra  <amodra@gmail.com>
1392
1393         * ppc-opc.c (ELEV): Define.
1394         (vle_opcodes): Add se_rfgi and e_sc.
1395         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1396         for E200Z4.
1397
1398 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1399
1400         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1401
1402 2017-04-21  Nick Clifton  <nickc@redhat.com>
1403
1404         PR binutils/21380
1405         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1406         LD3R and LD4R.
1407
1408 2017-04-13  Alan Modra  <amodra@gmail.com>
1409
1410         * epiphany-desc.c: Regenerate.
1411         * fr30-desc.c: Regenerate.
1412         * frv-desc.c: Regenerate.
1413         * ip2k-desc.c: Regenerate.
1414         * iq2000-desc.c: Regenerate.
1415         * lm32-desc.c: Regenerate.
1416         * m32c-desc.c: Regenerate.
1417         * m32r-desc.c: Regenerate.
1418         * mep-desc.c: Regenerate.
1419         * mt-desc.c: Regenerate.
1420         * or1k-desc.c: Regenerate.
1421         * xc16x-desc.c: Regenerate.
1422         * xstormy16-desc.c: Regenerate.
1423
1424 2017-04-11  Alan Modra  <amodra@gmail.com>
1425
1426         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1427         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1428         PPC_OPCODE_TMR for e6500.
1429         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1430         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1431         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1432         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1433         (PPCHTM): Define as PPC_OPCODE_POWER8.
1434         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1435
1436 2017-04-10  Alan Modra  <amodra@gmail.com>
1437
1438         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1439         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1440         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1441         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1442
1443 2017-04-09  Pip Cet  <pipcet@gmail.com>
1444
1445         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1446         appropriate floating-point precision directly.
1447
1448 2017-04-07  Alan Modra  <amodra@gmail.com>
1449
1450         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1451         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1452         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1453         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1454         vector instructions with E6500 not PPCVEC2.
1455
1456 2017-04-06  Pip Cet  <pipcet@gmail.com>
1457
1458         * Makefile.am: Add wasm32-dis.c.
1459         * configure.ac: Add wasm32-dis.c to wasm32 target.
1460         * disassemble.c: Add wasm32 disassembler code.
1461         * wasm32-dis.c: New file.
1462         * Makefile.in: Regenerate.
1463         * configure: Regenerate.
1464         * po/POTFILES.in: Regenerate.
1465         * po/opcodes.pot: Regenerate.
1466
1467 2017-04-05  Pedro Alves  <palves@redhat.com>
1468
1469         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1470         * arm-dis.c (parse_arm_disassembler_options): Constify.
1471         * ppc-dis.c (powerpc_init_dialect): Constify local.
1472         * vax-dis.c (parse_disassembler_options): Constify.
1473
1474 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1475
1476         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1477         RISCV_GP_SYMBOL.
1478
1479 2017-03-30  Pip Cet  <pipcet@gmail.com>
1480
1481         * configure.ac: Add (empty) bfd_wasm32_arch target.
1482         * configure: Regenerate
1483         * po/opcodes.pot: Regenerate.
1484
1485 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1486
1487         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1488         OSA2015.
1489         * opcodes/sparc-opc.c (asi_table): New ASIs.
1490
1491 2017-03-29  Alan Modra  <amodra@gmail.com>
1492
1493         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1494         "raw" option.
1495         (lookup_powerpc): Don't special case -1 dialect.  Handle
1496         PPC_OPCODE_RAW.
1497         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1498         lookup_powerpc call, pass it on second.
1499
1500 2017-03-27  Alan Modra  <amodra@gmail.com>
1501
1502         PR 21303
1503         * ppc-dis.c (struct ppc_mopt): Comment.
1504         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1505
1506 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1507
1508         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1509         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1510         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1511         (insert_nps_misc_imm_offset): New function.
1512         (extract_nps_misc imm_offset): New function.
1513         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1514         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1515
1516 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1517
1518         * s390-mkopc.c (main): Remove vx2 check.
1519         * s390-opc.txt: Remove vx2 instruction flags.
1520
1521 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1522
1523         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1524         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1525         (insert_nps_imm_offset): New function.
1526         (extract_nps_imm_offset): New function.
1527         (insert_nps_imm_entry): New function.
1528         (extract_nps_imm_entry): New function.
1529
1530 2017-03-17  Alan Modra  <amodra@gmail.com>
1531
1532         PR 21248
1533         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1534         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1535         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1536
1537 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1538
1539         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1540         <c.andi>: Likewise.
1541         <c.addiw> Likewise.
1542
1543 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1544
1545         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1546
1547 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1548
1549         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1550         <srl> Likewise.
1551         <srai> Likewise.
1552         <sra> Likewise.
1553
1554 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1555
1556         * i386-gen.c (opcode_modifiers): Replace S with Load.
1557         * i386-opc.h (S): Removed.
1558         (Load): New.
1559         (i386_opcode_modifier): Replace s with load.
1560         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1561         and {evex}.  Replace S with Load.
1562         * i386-tbl.h: Regenerated.
1563
1564 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1565
1566         * i386-opc.tbl: Use CpuCET on rdsspq.
1567         * i386-tbl.h: Regenerated.
1568
1569 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1570
1571         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1572         <vsx>: Do not use PPC_OPCODE_VSX3;
1573
1574 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1575
1576         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1577
1578 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1579
1580         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1581         (MOD_0F1E_PREFIX_1): Likewise.
1582         (MOD_0F38F5_PREFIX_2): Likewise.
1583         (MOD_0F38F6_PREFIX_0): Likewise.
1584         (RM_0F1E_MOD_3_REG_7): Likewise.
1585         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1586         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1587         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1588         (PREFIX_0F1E): Likewise.
1589         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1590         (PREFIX_0F38F5): Likewise.
1591         (dis386_twobyte): Use PREFIX_0F1E.
1592         (reg_table): Add REG_0F1E_MOD_3.
1593         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1594         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1595         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1596         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1597         (three_byte_table): Use PREFIX_0F38F5.
1598         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1599         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1600         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1601         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1602         PREFIX_MOD_3_0F01_REG_5_RM_2.
1603         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1604         (cpu_flags): Add CpuCET.
1605         * i386-opc.h (CpuCET): New enum.
1606         (CpuUnused): Commented out.
1607         (i386_cpu_flags): Add cpucet.
1608         * i386-opc.tbl: Add Intel CET instructions.
1609         * i386-init.h: Regenerated.
1610         * i386-tbl.h: Likewise.
1611
1612 2017-03-06  Alan Modra  <amodra@gmail.com>
1613
1614         PR 21124
1615         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1616         (extract_raq, extract_ras, extract_rbx): New functions.
1617         (powerpc_operands): Use opposite corresponding insert function.
1618         (Q_MASK): Define.
1619         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1620         register restriction.
1621
1622 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1623
1624         * disassemble.c Include "safe-ctype.h".
1625         (disassemble_init_for_target): Handle s390 init.
1626         (remove_whitespace_and_extra_commas): New function.
1627         (disassembler_options_cmp): Likewise.
1628         * arm-dis.c: Include "libiberty.h".
1629         (NUM_ELEM): Delete.
1630         (regnames): Use long disassembler style names.
1631         Add force-thumb and no-force-thumb options.
1632         (NUM_ARM_REGNAMES): Rename from this...
1633         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1634         (get_arm_regname_num_options): Delete.
1635         (set_arm_regname_option): Likewise.
1636         (get_arm_regnames): Likewise.
1637         (parse_disassembler_options): Likewise.
1638         (parse_arm_disassembler_option): Rename from this...
1639         (parse_arm_disassembler_options): ...to this.  Make static.
1640         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1641         (print_insn): Use parse_arm_disassembler_options.
1642         (disassembler_options_arm): New function.
1643         (print_arm_disassembler_options): Handle updated regnames.
1644         * ppc-dis.c: Include "libiberty.h".
1645         (ppc_opts): Add "32" and "64" entries.
1646         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1647         (powerpc_init_dialect): Add break to switch statement.
1648         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1649         (disassembler_options_powerpc): New function.
1650         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1651         Remove printing of "32" and "64".
1652         * s390-dis.c: Include "libiberty.h".
1653         (init_flag): Remove unneeded variable.
1654         (struct s390_options_t): New structure type.
1655         (options): New structure.
1656         (init_disasm): Rename from this...
1657         (disassemble_init_s390): ...to this.  Add initializations for
1658         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1659         (print_insn_s390): Delete call to init_disasm.
1660         (disassembler_options_s390): New function.
1661         (print_s390_disassembler_options): Print using information from
1662         struct 'options'.
1663         * po/opcodes.pot: Regenerate.
1664
1665 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1666
1667         * i386-dis.c (PCMPESTR_Fixup): New.
1668         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1669         (prefix_table): Use PCMPESTR_Fixup.
1670         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1671         PCMPESTR_Fixup.
1672         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1673         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1674         Split 64-bit and non-64-bit variants.
1675         * opcodes/i386-tbl.h: Re-generate.
1676
1677 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1678
1679         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1680         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1681         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1682         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1683         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1684         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1685         (OP_SVE_V_HSD): New macros.
1686         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1687         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1688         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1689         (aarch64_opcode_table): Add new SVE instructions.
1690         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1691         for rotation operands.  Add new SVE operands.
1692         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1693         (ins_sve_quad_index): Likewise.
1694         (ins_imm_rotate): Split into...
1695         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1696         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1697         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1698         functions.
1699         (aarch64_ins_sve_addr_ri_s4): New function.
1700         (aarch64_ins_sve_quad_index): Likewise.
1701         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1702         * aarch64-asm-2.c: Regenerate.
1703         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1704         (ext_sve_quad_index): Likewise.
1705         (ext_imm_rotate): Split into...
1706         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1707         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1708         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1709         functions.
1710         (aarch64_ext_sve_addr_ri_s4): New function.
1711         (aarch64_ext_sve_quad_index): Likewise.
1712         (aarch64_ext_sve_index): Allow quad indices.
1713         (do_misc_decoding): Likewise.
1714         * aarch64-dis-2.c: Regenerate.
1715         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1716         aarch64_field_kinds.
1717         (OPD_F_OD_MASK): Widen by one bit.
1718         (OPD_F_NO_ZR): Bump accordingly.
1719         (get_operand_field_width): New function.
1720         * aarch64-opc.c (fields): Add new SVE fields.
1721         (operand_general_constraint_met_p): Handle new SVE operands.
1722         (aarch64_print_operand): Likewise.
1723         * aarch64-opc-2.c: Regenerate.
1724
1725 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1726
1727         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1728         (aarch64_feature_compnum): ...this.
1729         (SIMD_V8_3): Replace with...
1730         (COMPNUM): ...this.
1731         (CNUM_INSN): New macro.
1732         (aarch64_opcode_table): Use it for the complex number instructions.
1733
1734 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1735
1736         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1737
1738 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1739
1740         Add support for associating SPARC ASIs with an architecture level.
1741         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1742         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1743         decoding of SPARC ASIs.
1744
1745 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1746
1747         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1748         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1749
1750 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1751
1752         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1753         1 (instead of to itself). Correct typo.
1754
1755 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1756
1757         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1758         pseudoinstructions.
1759
1760 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1761
1762         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1763         (aarch64_sys_reg_supported_p): Handle them.
1764
1765 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1766
1767         * arc-opc.c (UIMM6_20R): Define.
1768         (SIMM12_20): Use above.
1769         (SIMM12_20R): Define.
1770         (SIMM3_5_S): Use above.
1771         (UIMM7_A32_11R_S): Define.
1772         (UIMM7_9_S): Use above.
1773         (UIMM3_13R_S): Define.
1774         (SIMM11_A32_7_S): Use above.
1775         (SIMM9_8R): Define.
1776         (UIMM10_A32_8_S): Use above.
1777         (UIMM8_8R_S): Define.
1778         (W6): Use above.
1779         (arc_relax_opcodes): Use all above defines.
1780
1781 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1782
1783         * arc-regs.h: Distinguish some of the registers different on
1784         ARC700 and HS38 cpus.
1785
1786 2017-02-14  Alan Modra  <amodra@gmail.com>
1787
1788         PR 21118
1789         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1790         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1791
1792 2017-02-11  Stafford Horne  <shorne@gmail.com>
1793             Alan Modra  <amodra@gmail.com>
1794
1795         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1796         Use insn_bytes_value and insn_int_value directly instead.  Don't
1797         free allocated memory until function exit.
1798
1799 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1800
1801         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1802
1803 2017-02-03  Nick Clifton  <nickc@redhat.com>
1804
1805         PR 21096
1806         * aarch64-opc.c (print_register_list): Ensure that the register
1807         list index will fir into the tb buffer.
1808         (print_register_offset_address): Likewise.
1809         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1810
1811 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1812
1813         PR 21056
1814         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1815         instructions when the previous fetch packet ends with a 32-bit
1816         instruction.
1817
1818 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1819
1820         * pru-opc.c: Remove vague reference to a future GDB port.
1821
1822 2017-01-20  Nick Clifton  <nickc@redhat.com>
1823
1824         * po/ga.po: Updated Irish translation.
1825
1826 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1827
1828         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1829
1830 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1831
1832         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1833         if FETCH_DATA returns 0.
1834         (m68k_scan_mask): Likewise.
1835         (print_insn_m68k): Update code to handle -1 return value.
1836
1837 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1838
1839         * m68k-dis.c (enum print_insn_arg_error): New.
1840         (NEXTBYTE): Replace -3 with
1841         PRINT_INSN_ARG_MEMORY_ERROR.
1842         (NEXTULONG): Likewise.
1843         (NEXTSINGLE): Likewise.
1844         (NEXTDOUBLE): Likewise.
1845         (NEXTDOUBLE): Likewise.
1846         (NEXTPACKED): Likewise.
1847         (FETCH_ARG): Likewise.
1848         (FETCH_DATA): Update comments.
1849         (print_insn_arg): Update comments. Replace magic numbers with
1850         enum.
1851         (match_insn_m68k): Likewise.
1852
1853 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1854
1855         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1856         * i386-dis-evex.h (evex_table): Updated.
1857         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1858         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1859         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1860         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1861         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1862         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1863         * i386-init.h: Regenerate.
1864         * i386-tbl.h: Ditto.
1865
1866 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1867
1868         * msp430-dis.c (msp430_singleoperand): Return -1 if
1869         msp430dis_opcode_signed returns false.
1870         (msp430_doubleoperand): Likewise.
1871         (msp430_branchinstr): Return -1 if
1872         msp430dis_opcode_unsigned returns false.
1873         (msp430x_calla_instr): Likewise.
1874         (print_insn_msp430): Likewise.
1875
1876 2017-01-05  Nick Clifton  <nickc@redhat.com>
1877
1878         PR 20946
1879         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1880         could not be matched.
1881         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1882         NULL.
1883
1884 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1885
1886         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1887         (aarch64_opcode_table): Use RCPC_INSN.
1888
1889 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1890
1891         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1892         extension.
1893         * riscv-opcodes/all-opcodes: Likewise.
1894
1895 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1896
1897         * riscv-dis.c (print_insn_args): Add fall through comment.
1898
1899 2017-01-03  Nick Clifton  <nickc@redhat.com>
1900
1901         * po/sr.po: New Serbian translation.
1902         * configure.ac (ALL_LINGUAS): Add sr.
1903         * configure: Regenerate.
1904
1905 2017-01-02  Alan Modra  <amodra@gmail.com>
1906
1907         * epiphany-desc.h: Regenerate.
1908         * epiphany-opc.h: Regenerate.
1909         * fr30-desc.h: Regenerate.
1910         * fr30-opc.h: Regenerate.
1911         * frv-desc.h: Regenerate.
1912         * frv-opc.h: Regenerate.
1913         * ip2k-desc.h: Regenerate.
1914         * ip2k-opc.h: Regenerate.
1915         * iq2000-desc.h: Regenerate.
1916         * iq2000-opc.h: Regenerate.
1917         * lm32-desc.h: Regenerate.
1918         * lm32-opc.h: Regenerate.
1919         * m32c-desc.h: Regenerate.
1920         * m32c-opc.h: Regenerate.
1921         * m32r-desc.h: Regenerate.
1922         * m32r-opc.h: Regenerate.
1923         * mep-desc.h: Regenerate.
1924         * mep-opc.h: Regenerate.
1925         * mt-desc.h: Regenerate.
1926         * mt-opc.h: Regenerate.
1927         * or1k-desc.h: Regenerate.
1928         * or1k-opc.h: Regenerate.
1929         * xc16x-desc.h: Regenerate.
1930         * xc16x-opc.h: Regenerate.
1931         * xstormy16-desc.h: Regenerate.
1932         * xstormy16-opc.h: Regenerate.
1933
1934 2017-01-02  Alan Modra  <amodra@gmail.com>
1935
1936         Update year range in copyright notice of all files.
1937
1938 For older changes see ChangeLog-2016
1939 \f
1940 Copyright (C) 2017 Free Software Foundation, Inc.
1941
1942 Copying and distribution of this file, with or without modification,
1943 are permitted in any medium without royalty provided the copyright
1944 notice and this notice are preserved.
1945
1946 Local Variables:
1947 mode: change-log
1948 left-margin: 8
1949 fill-column: 74
1950 version-control: never
1951 End: