opcodes/ChangeLog

   1 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/25622
   4         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
   5         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
   6         * i386-tbl.h: Regenerated.
   7
   8 2020-02-26  Alan Modra  <amodra@gmail.com>
   9
  10         * aarch64-asm.c: Indent labels correctly.
  11         * aarch64-dis.c: Likewise.
  12         * aarch64-gen.c: Likewise.
  13         * aarch64-opc.c: Likewise.
  14         * alpha-dis.c: Likewise.
  15         * i386-dis.c: Likewise.
  16         * nds32-asm.c: Likewise.
  17         * nfp-dis.c: Likewise.
  18         * visium-dis.c: Likewise.
  19
  20 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  21
  22         * arc-regs.h (int_vector_base): Make it available for all ARC
  23         CPUs.
  24
  25 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  26
  27         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  28         changed.
  29
  30 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  31
  32         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  33         c.mv/c.li if rs1 is zero.
  34
  35 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  38         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  39         CPU_POPCNT_FLAGS.
  40         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  41         * i386-opc.h (CpuABM): Removed.
  42         (CpuPOPCNT): New.
  43         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  44         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  45         popcnt.  Remove CpuABM from lzcnt.
  46         * i386-init.h: Regenerated.
  47         * i386-tbl.h: Likewise.
  48
  49 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  52         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  53         VexW1 instead of open-coding them.
  54         * i386-tbl.h: Re-generate.
  55
  56 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl (AddrPrefixOpReg): Define.
  59         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  60         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  61         templates. Drop NoRex64.
  62         * i386-tbl.h: Re-generate.
  63
  64 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  65
  66         PR gas/6518
  67         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  68         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  69         into Intel syntax instance (with Unpsecified) and AT&T one
  70         (without).
  71         (vcvtneps2bf16): Likewise, along with folding the two so far
  72         separate ones.
  73         * i386-tbl.h: Re-generate.
  74
  75 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  78         CPU_ANY_SSE4A_FLAGS.
  79
  80 2020-02-17  Alan Modra  <amodra@gmail.com>
  81
  82         * i386-gen.c (cpu_flag_init): Correct last change.
  83
  84 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  85
  86         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  87         CPU_ANY_SSE4_FLAGS.
  88
  89 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  92         (movzx): Likewise.
  93
  94 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  95
  96         PR gas/25438
  97         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  98         destination for Cpu64-only variant.
  99         (movzx): Fold patterns.
 100         * i386-tbl.h: Re-generate.
 101
 102 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 105         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 106         CPU_ANY_SSE4_FLAGS entry.
 107         * i386-init.h: Re-generate.
 108
 109 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 112         with Unspecified, making the present one AT&T syntax only.
 113         * i386-tbl.h: Re-generate.
 114
 115 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 118         * i386-tbl.h: Re-generate.
 119
 120 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 121
 122         PR gas/24546
 123         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 124         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 125         Amd64 and Intel64 templates.
 126         (call, jmp): Likewise for far indirect variants. Dro
 127         Unspecified.
 128         * i386-tbl.h: Re-generate.
 129
 130 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 133         * i386-opc.h (ShortForm): Delete.
 134         (struct i386_opcode_modifier): Remove shortform field.
 135         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 136         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 137         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 138         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 139         Drop ShortForm.
 140         * i386-tbl.h: Re-generate.
 141
 142 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 145         fucompi): Drop ShortForm from operand-less templates.
 146         * i386-tbl.h: Re-generate.
 147
 148 2020-02-11  Alan Modra  <amodra@gmail.com>
 149
 150         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 151         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 152         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 153         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 154         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 155
 156 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 157
 158         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 159         (cde_opcodes): Add VCX* instructions.
 160
 161 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 162             Matthew Malcomson  <matthew.malcomson@arm.com>
 163
 164         * arm-dis.c (struct cdeopcode32): New.
 165         (CDE_OPCODE): New macro.
 166         (cde_opcodes): New disassembly table.
 167         (regnames): New option to table.
 168         (cde_coprocs): New global variable.
 169         (print_insn_cde): New
 170         (print_insn_thumb32): Use print_insn_cde.
 171         (parse_arm_disassembler_options): Parse coprocN args.
 172
 173 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         PR gas/25516
 176         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 177         with ISA64.
 178         * i386-opc.h (AMD64): Removed.
 179         (Intel64): Likewose.
 180         (AMD64): New.
 181         (INTEL64): Likewise.
 182         (INTEL64ONLY): Likewise.
 183         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 184         * i386-opc.tbl (Amd64): New.
 185         (Intel64): Likewise.
 186         (Intel64Only): Likewise.
 187         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 188         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 189         * i386-tbl.h: Regenerated.
 190
 191 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 192
 193         PR 25469
 194         * z80-dis.c: Add support for GBZ80 opcodes.
 195
 196 2020-02-04  Alan Modra  <amodra@gmail.com>
 197
 198         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 199
 200 2020-02-03  Alan Modra  <amodra@gmail.com>
 201
 202         * m32c-ibld.c: Regenerate.
 203
 204 2020-02-01  Alan Modra  <amodra@gmail.com>
 205
 206         * frv-ibld.c: Regenerate.
 207
 208 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 211         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 212         (OP_E_memory): Replace xmm_mdq_mode case label by
 213         vex_scalar_w_dq_mode one.
 214         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 215
 216 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 219         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 220         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 221         (intel_operand_size): Drop vex_w_dq_mode case label.
 222
 223 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 224
 225         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 226         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 227
 228 2020-01-30  Alan Modra  <amodra@gmail.com>
 229
 230         * m32c-ibld.c: Regenerate.
 231
 232 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 233
 234         * bpf-opc.c: Regenerate.
 235
 236 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 239         (dis386): Use them to replace C2/C3 table entries.
 240         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 241         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 242         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 243         * i386-tbl.h: Re-generate.
 244
 245 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 248         forms.
 249         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 250         DefaultSize.
 251         * i386-tbl.h: Re-generate.
 252
 253 2020-01-30  Alan Modra  <amodra@gmail.com>
 254
 255         * tic4x-dis.c (tic4x_dp): Make unsigned.
 256
 257 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 258             Jan Beulich  <jbeulich@suse.com>
 259
 260         PR binutils/25445
 261         * i386-dis.c (MOVSXD_Fixup): New function.
 262         (movsxd_mode): New enum.
 263         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 264         (intel_operand_size): Handle movsxd_mode.
 265         (OP_E_register): Likewise.
 266         (OP_G): Likewise.
 267         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 268         register on movsxd.  Add movsxd with 16-bit destination register
 269         for AMD64 and Intel64 ISAs.
 270         * i386-tbl.h: Regenerated.
 271
 272 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 273
 274         PR 25403
 275         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 276         * aarch64-asm-2.c: Regenerate
 277         * aarch64-dis-2.c: Likewise.
 278         * aarch64-opc-2.c: Likewise.
 279
 280 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (sysret): Drop DefaultSize.
 283         * i386-tbl.h: Re-generate.
 284
 285 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 288         Dword.
 289         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 290         * i386-tbl.h: Re-generate.
 291
 292 2020-01-20  Nick Clifton  <nickc@redhat.com>
 293
 294         * po/de.po: Updated German translation.
 295         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 296         * po/uk.po: Updated Ukranian translation.
 297
 298 2020-01-20  Alan Modra  <amodra@gmail.com>
 299
 300         * hppa-dis.c (fput_const): Remove useless cast.
 301
 302 2020-01-20  Alan Modra  <amodra@gmail.com>
 303
 304         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 305
 306 2020-01-18  Nick Clifton  <nickc@redhat.com>
 307
 308         * configure: Regenerate.
 309         * po/opcodes.pot: Regenerate.
 310
 311 2020-01-18  Nick Clifton  <nickc@redhat.com>
 312
 313         Binutils 2.34 branch created.
 314
 315 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 316
 317         * opintl.h: Fix spelling error (seperate).
 318
 319 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 320
 321         * i386-opc.tbl: Add {vex} pseudo prefix.
 322         * i386-tbl.h: Regenerated.
 323
 324 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 325
 326         PR 25376
 327         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 328         (neon_opcodes): Likewise.
 329         (select_arm_features): Make sure we enable MVE bits when selecting
 330         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 331         any architecture.
 332
 333 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-opc.tbl: Drop stale comment from XOP section.
 336
 337 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 340         (extractps): Add VexWIG to SSE2AVX forms.
 341         * i386-tbl.h: Re-generate.
 342
 343 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 344
 345         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 346         Size64 from and use VexW1 on SSE2AVX forms.
 347         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 348         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 349         * i386-tbl.h: Re-generate.
 350
 351 2020-01-15  Alan Modra  <amodra@gmail.com>
 352
 353         * tic4x-dis.c (tic4x_version): Make unsigned long.
 354         (optab, optab_special, registernames): New file scope vars.
 355         (tic4x_print_register): Set up registernames rather than
 356         malloc'd registertable.
 357         (tic4x_disassemble): Delete optable and optable_special.  Use
 358         optab and optab_special instead.  Throw away old optab,
 359         optab_special and registernames when info->mach changes.
 360
 361 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 362
 363         PR 25377
 364         * z80-dis.c (suffix): Use .db instruction to generate double
 365         prefix.
 366
 367 2020-01-14  Alan Modra  <amodra@gmail.com>
 368
 369         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 370         values to unsigned before shifting.
 371
 372 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 373
 374         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 375         flow instructions.
 376         (print_insn_thumb16, print_insn_thumb32): Likewise.
 377         (print_insn): Initialize the insn info.
 378         * i386-dis.c (print_insn): Initialize the insn info fields, and
 379         detect jumps.
 380
 381 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 382
 383         * arc-opc.c (C_NE): Make it required.
 384
 385 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 386
 387         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 388         reserved register name.
 389
 390 2020-01-13  Alan Modra  <amodra@gmail.com>
 391
 392         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 393         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 394
 395 2020-01-13  Alan Modra  <amodra@gmail.com>
 396
 397         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 398         result of wasm_read_leb128 in a uint64_t and check that bits
 399         are not lost when copying to other locals.  Use uint32_t for
 400         most locals.  Use PRId64 when printing int64_t.
 401
 402 2020-01-13  Alan Modra  <amodra@gmail.com>
 403
 404         * score-dis.c: Formatting.
 405         * score7-dis.c: Formatting.
 406
 407 2020-01-13  Alan Modra  <amodra@gmail.com>
 408
 409         * score-dis.c (print_insn_score48): Use unsigned variables for
 410         unsigned values.  Don't left shift negative values.
 411         (print_insn_score32): Likewise.
 412         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 413
 414 2020-01-13  Alan Modra  <amodra@gmail.com>
 415
 416         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 417
 418 2020-01-13  Alan Modra  <amodra@gmail.com>
 419
 420         * fr30-ibld.c: Regenerate.
 421
 422 2020-01-13  Alan Modra  <amodra@gmail.com>
 423
 424         * xgate-dis.c (print_insn): Don't left shift signed value.
 425         (ripBits): Formatting, use 1u.
 426
 427 2020-01-10  Alan Modra  <amodra@gmail.com>
 428
 429         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 430         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 431
 432 2020-01-10  Alan Modra  <amodra@gmail.com>
 433
 434         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 435         and XRREG value earlier to avoid a shift with negative exponent.
 436         * m10200-dis.c (disassemble): Similarly.
 437
 438 2020-01-09  Nick Clifton  <nickc@redhat.com>
 439
 440         PR 25224
 441         * z80-dis.c (ld_ii_ii): Use correct cast.
 442
 443 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 444
 445         PR 25224
 446         * z80-dis.c (ld_ii_ii): Use character constant when checking
 447         opcode byte value.
 448
 449 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-dis.c (SEP_Fixup): New.
 452         (SEP): Define.
 453         (dis386_twobyte): Use it for sysenter/sysexit.
 454         (enum x86_64_isa): Change amd64 enumerator to value 1.
 455         (OP_J): Compare isa64 against intel64 instead of amd64.
 456         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 457         forms.
 458         * i386-tbl.h: Re-generate.
 459
 460 2020-01-08  Alan Modra  <amodra@gmail.com>
 461
 462         * z8k-dis.c: Include libiberty.h
 463         (instr_data_s): Make max_fetched unsigned.
 464         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 465         Don't exceed byte_info bounds.
 466         (output_instr): Make num_bytes unsigned.
 467         (unpack_instr): Likewise for nibl_count and loop.
 468         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 469         idx unsigned.
 470         * z8k-opc.h: Regenerate.
 471
 472 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 473
 474         * arc-tbl.h (llock): Use 'LLOCK' as class.
 475         (llockd): Likewise.
 476         (scond): Use 'SCOND' as class.
 477         (scondd): Likewise.
 478         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 479         (scondd): Likewise.
 480
 481 2020-01-06  Alan Modra  <amodra@gmail.com>
 482
 483         * m32c-ibld.c: Regenerate.
 484
 485 2020-01-06  Alan Modra  <amodra@gmail.com>
 486
 487         PR 25344
 488         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 489         Peek at next byte to prevent recursion on repeated prefix bytes.
 490         Ensure uninitialised "mybuf" is not accessed.
 491         (print_insn_z80): Don't zero n_fetch and n_used here,..
 492         (print_insn_z80_buf): ..do it here instead.
 493
 494 2020-01-04  Alan Modra  <amodra@gmail.com>
 495
 496         * m32r-ibld.c: Regenerate.
 497
 498 2020-01-04  Alan Modra  <amodra@gmail.com>
 499
 500         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 501
 502 2020-01-04  Alan Modra  <amodra@gmail.com>
 503
 504         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 505
 506 2020-01-04  Alan Modra  <amodra@gmail.com>
 507
 508         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 509
 510 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 511
 512         * aarch64-tbl.h (aarch64_opcode_table): Use
 513         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 514
 515 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 516
 517         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 518         forms of SUDOT and USDOT.
 519
 520 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 521
 522         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 523         uzip{1,2}.
 524         * opcodes/aarch64-dis-2.c: Re-generate.
 525
 526 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 527
 528         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 529         FMMLA encoding.
 530         * opcodes/aarch64-dis-2.c: Re-generate.
 531
 532 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 533
 534         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 535
 536 2020-01-01  Alan Modra  <amodra@gmail.com>
 537
 538         Update year range in copyright notice of all files.
 539
 540 For older changes see ChangeLog-2019
 541 \f
 542 Copyright (C) 2020 Free Software Foundation, Inc.
 543
 544 Copying and distribution of this file, with or without modification,
 545 are permitted in any medium without royalty provided the copyright
 546 notice and this notice are preserved.
 547
 548 Local Variables:
 549 mode: change-log
 550 left-margin: 8
 551 fill-column: 74
 552 version-control: never
 553 End: