1 2016-12-31 Dimitar Dimitrov <dimitar@dinux.eu>
3 * Makefile.am: Add PRU source files.
4 * configure.ac: Add PRU target.
5 * disassemble.c (disassembler): Register PRU arch.
8 * Makefile.in: Regenerate.
9 * configure: Regenerate.
11 2016-12-29 Yao Qi <yao.qi@linaro.org>
13 * avr-dis.c: Include "bfd_stdint.h"
14 (avrdis_opcode): Change return type to int, add argument
15 insn. Set *INSN on success.
16 (print_insn_avr): Check return value of avrdis_opcode, and
19 2016-12-28 Alan Modra <amodra@gmail.com>
21 * configure.ac: Revert 2016-12-23.
22 * Makefile.am: Likewise.
24 (mips-dis.lo): Add rule.
25 * Makefile.in: Regenerate.
26 * aclocal.m4: Regenerate.
27 * config.in: Regenerate.
28 * configure: Regenerate.
30 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
32 * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
33 `4' and `s' operand codes.
34 (mips16_opcodes): Add "asmacro" entry.
36 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
38 * mips-dis.c (print_mips16_insn_arg): Simplify processing of
40 * mips16-opc.c (decode_mips16_operand): Switch the extended
41 form of the `<' operand type to LSB position 22.
43 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
45 * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
46 operand codes with `.' and `F' respectively.
47 (mips16_opcodes): Likewise.
49 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
51 * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
52 matching for INSN2_SHORT_ONLY opcode table entries.
53 * mips16-opc.c (SH): New macro.
54 (mips16_opcodes): Set SH in `pinfo2' for non-extensible
55 instruction entries: "nop", "addu", "and", "break", "cmp",
56 "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
57 "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
58 "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
59 "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
60 "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
61 "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
62 "seh", "sew", "zeb", "zeh", "zew" and "extend".
64 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
66 * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
69 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
71 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
74 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
76 * mips-dis.c (set_default_mips_dis_options): Use
77 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
78 call to `bfd_mips_elf_get_abiflags'.
79 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
80 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
81 * aclocal.m4: Regenerate.
82 * configure: Regenerate.
83 * config.in: Regenerate.
84 * Makefile.in: Regenerate.
86 2016-12-23 Tristan Gingold <gingold@adacore.com>
88 * configure: Regenerate.
90 2016-12-23 Tristan Gingold <gingold@adacore.com>
92 * po/opcodes.pot: Regenerate.
94 2016-12-21 Andrew Waterman <andrew@sifive.com>
96 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
98 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
100 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
101 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
102 (print_insn_mips16): Check opcode entries for validity against
103 the ISA level and ASE set selected.
105 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
107 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
108 `insn' together, with `extend' as the high-order 16 bits.
109 (match_kind): New enum.
110 (print_insn_mips16): Rework for 32-bit instruction matching.
111 Do not dump EXTEND prefixes here.
112 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
113 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
116 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
118 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
119 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
122 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
124 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
125 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
128 2016-12-20 Andrew Waterman <andrew@sifive.com>
130 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
133 2016-12-20 Andrew Waterman <andrew@sifive.com>
135 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
138 2016-12-20 Andrew Waterman <andrew@sifive.com>
140 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
143 2016-12-20 Andrew Waterman <andrew@sifive.com>
145 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
146 XLEN when none is provided.
148 2016-12-20 Andrew Waterman <andrew@sifive.com>
150 * riscv-opc.c: Formatting fixes.
152 2016-12-20 Alan Modra <amodra@gmail.com>
154 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
155 * Makefile.in: Regenerate.
156 * po/POTFILES.in: Regenerate.
158 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
160 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
161 Only examine ELF file structures here.
163 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
165 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
166 `bfd_mips_elf_get_abiflags' here.
168 2016-12-16 Nick Clifton <nickc@redhat.com>
170 * arm-dis.c (print_insn_thumb32): Fix compile time warning
171 computing value_in_comment.
173 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
175 * mips-dis.c (mips_convert_abiflags_ases): New function.
176 (set_default_mips_dis_options): Also infer ASE flags from ELF
179 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
181 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
182 header flag interpretation code.
184 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
186 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
187 `pinfo2' with SP-relative "sd" entries.
189 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
191 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
194 2016-12-13 Renlin Li <renlin.li@arm.com>
196 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
198 (operand_general_constraint_met_p): Remove case for CP_REG.
199 (aarch64_print_operand): Print CRn, CRm operand using imm field.
200 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
202 (aarch64_opcode_table): Change CRn, CRm operand class and type.
203 * aarch64-opc-2.c : Regenerate.
204 * aarch64-asm-2.c : Likewise.
205 * aarch64-dis-2.c : Likewise.
207 2016-12-12 Yao Qi <yao.qi@linaro.org>
209 * rx-dis.c: Include <setjmp.h>
210 (struct private): New.
211 (rx_get_byte): Check return value of read_memory_func, and
212 call memory_error_func and OPCODES_SIGLONGJMP on error.
213 (print_insn_rx): Call OPCODES_SIGSETJMP.
215 2016-12-12 Yao Qi <yao.qi@linaro.org>
217 * rl78-dis.c: Include <setjmp.h>.
218 (struct private): New.
219 (rl78_get_byte): Check return value of read_memory_func, and
220 call memory_error_func and OPCODES_SIGLONGJMP on error.
221 (print_insn_rl78_common): Call OPCODES_SIGJMP.
223 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
225 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
227 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
229 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
232 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
234 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
235 to separate `extend' and its uninterpreted argument output.
236 Separate hexadecimal halves of undecoded extended instructions
239 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
241 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
242 indentation space across.
244 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
246 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
247 adjustment for PC-relative operations following MIPS16e compact
248 jumps or undefined RR/J(AL)R(C) encodings.
250 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
252 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
253 variable to `reglane_index'.
255 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
257 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
259 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
261 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
263 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
265 * mips16-opc.c (mips16_opcodes): Update comment naming structure
268 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
270 * mips-dis.c (print_mips_disassembler_options): Reformat output.
272 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
274 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
275 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
277 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
279 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
281 2016-12-01 Nick Clifton <nickc@redhat.com>
284 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
287 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
289 * arc-opc.c (insert_ra_chk): New function.
290 (insert_rb_chk): Likewise.
291 (insert_rad): Update text error message.
292 (insert_rcd): Likewise.
293 (insert_rhv2): Likewise.
294 (insert_r0): Likewise.
295 (insert_r1): Likewise.
296 (insert_r2): Likewise.
297 (insert_r3): Likewise.
298 (insert_sp): Likewise.
299 (insert_gp): Likewise.
300 (insert_pcl): Likewise.
301 (insert_blink): Likewise.
302 (insert_ilink1): Likewise.
303 (insert_ilink2): Likewise.
304 (insert_ras): Likewise.
305 (insert_rbs): Likewise.
306 (insert_rcs): Likewise.
307 (insert_simm3s): Likewise.
308 (insert_rrange): Likewise.
309 (insert_fpel): Likewise.
310 (insert_blinkel): Likewise.
311 (insert_pcel): Likewise.
312 (insert_nps_3bit_dst): Likewise.
313 (insert_nps_3bit_dst_short): Likewise.
314 (insert_nps_3bit_src2_short): Likewise.
315 (insert_nps_bitop_size_2b): Likewise.
316 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
321 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
322 * arc-tbl.h (div, divu): All instructions are DIVREM class.
323 Change first insn argument to check for LP_COUNT usage.
325 (ld, ldd): All instructions are LOAD class. Change first insn
326 argument to check for LP_COUNT usage.
327 (st, std): All instructions are STORE class.
328 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
329 Change first insn argument to check for LP_COUNT usage.
330 (mov): All instructions are MOVE class. Change first insn
331 argument to check for LP_COUNT usage.
333 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
335 * arc-dis.c (is_compatible_p): Remove function.
336 (skip_this_opcode): Don't add any decoding class to decode list.
338 (find_format_from_table): Go through all opcodes, and warn if we
339 use a guessed mnemonic.
341 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
342 Amit Pawar <amit.pawar@amd.com>
345 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
348 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
350 * configure: Regenerate.
352 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
354 * sparc-opc.c (HWS_V8): Definition moved from
355 gas/config/tc-sparc.c.
365 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
368 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
370 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
373 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
375 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
376 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
377 (aarch64_opcode_table): Add fcmla and fcadd.
378 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
379 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
380 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
381 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
382 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
383 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
384 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
385 (operand_general_constraint_met_p): Rotate and index range check.
386 (aarch64_print_operand): Handle rotate operand.
387 * aarch64-asm-2.c: Regenerate.
388 * aarch64-dis-2.c: Likewise.
389 * aarch64-opc-2.c: Likewise.
391 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
393 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
394 * aarch64-asm-2.c: Regenerate.
395 * aarch64-dis-2.c: Regenerate.
396 * aarch64-opc-2.c: Regenerate.
398 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
400 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
401 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
402 * aarch64-asm-2.c: Regenerate.
403 * aarch64-dis-2.c: Regenerate.
404 * aarch64-opc-2.c: Regenerate.
406 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
408 * aarch64-tbl.h (QL_X1NIL): New.
409 (arch64_opcode_table): Add ldraa, ldrab.
410 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
411 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
412 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
413 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
414 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
415 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
416 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
417 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
418 (aarch64_print_operand): Likewise.
419 * aarch64-asm-2.c: Regenerate.
420 * aarch64-dis-2.c: Regenerate.
421 * aarch64-opc-2.c: Regenerate.
423 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
425 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
426 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
427 * aarch64-asm-2.c: Regenerate.
428 * aarch64-dis-2.c: Regenerate.
429 * aarch64-opc-2.c: Regenerate.
431 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
433 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
434 (AARCH64_OPERANDS): Add Rm_SP.
435 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
436 * aarch64-asm-2.c: Regenerate.
437 * aarch64-dis-2.c: Regenerate.
438 * aarch64-opc-2.c: Regenerate.
440 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
442 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
443 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
444 autdzb, xpaci, xpacd.
445 * aarch64-asm-2.c: Regenerate.
446 * aarch64-dis-2.c: Regenerate.
447 * aarch64-opc-2.c: Regenerate.
449 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
451 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
452 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
453 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
454 (aarch64_sys_reg_supported_p): Add feature test for new registers.
456 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
458 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
459 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
460 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
462 * aarch64-asm-2.c: Regenerate.
463 * aarch64-dis-2.c: Regenerate.
465 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
467 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
469 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
472 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
473 * i386-dis.c (EdqwS): Removed.
474 (dqw_swap_mode): Likewise.
475 (intel_operand_size): Don't check dqw_swap_mode.
476 (OP_E_register): Likewise.
477 (OP_E_memory): Likewise.
480 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
481 * i386-tbl.h: Regerated.
483 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
485 * i386-opc.tbl: Merge AVX512F vmovq.
486 * i386-tbl.h: Regerated.
488 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
491 * i386-dis.c (THREE_BYTE_0F7A): Removed.
492 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
493 (three_byte_table): Remove THREE_BYTE_0F7A.
495 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
498 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
499 (FGRPd9_4): Replace 1 with 2.
500 (FGRPd9_5): Replace 2 with 3.
501 (FGRPd9_6): Replace 3 with 4.
502 (FGRPd9_7): Replace 4 with 5.
503 (FGRPda_5): Replace 5 with 6.
504 (FGRPdb_4): Replace 6 with 7.
505 (FGRPde_3): Replace 7 with 8.
506 (FGRPdf_4): Replace 8 with 9.
507 (fgrps): Add an entry for Bad_Opcode.
509 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
511 * arc-opc.c (arc_flag_operands): Add F_DI14.
512 (arc_flag_classes): Add C_DI14.
513 * arc-nps400-tbl.h: Add new exc instructions.
515 2016-11-03 Graham Markall <graham.markall@embecosm.com>
517 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
519 * arc-nps-400-tbl.h: Add dcmac instruction.
520 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
521 (insert_nps_rbdouble_64): Added.
522 (extract_nps_rbdouble_64): Added.
523 (insert_nps_proto_size): Added.
524 (extract_nps_proto_size): Added.
526 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
528 * arc-dis.c (struct arc_operand_iterator): Remove all fields
529 relating to long instruction processing, add new limm field.
530 (OPCODE): Rename to...
531 (OPCODE_32BIT_INSN): ...this.
533 (skip_this_opcode): Handle different instruction lengths, update
535 (special_flag_p): Update parameter type.
536 (find_format_from_table): Update for more instruction lengths.
537 (find_format_long_instructions): Delete.
538 (find_format): Update for more instruction lengths.
539 (arc_insn_length): Likewise.
540 (extract_operand_value): Update for more instruction lengths.
541 (operand_iterator_next): Remove code relating to long
543 (arc_opcode_to_insn_type): New function.
544 (print_insn_arc):Update for more instructions lengths.
545 * arc-ext.c (extInstruction_t): Change argument type.
546 * arc-ext.h (extInstruction_t): Change argument type.
547 * arc-fxi.h: Change type unsigned to unsigned long long
548 extensively throughout.
549 * arc-nps400-tbl.h: Add long instructions taken from
550 arc_long_opcodes table in arc-opc.c.
551 * arc-opc.c: Update parameter types on insert/extract handlers.
552 (arc_long_opcodes): Delete.
553 (arc_num_long_opcodes): Delete.
554 (arc_opcode_len): Update for more instruction lengths.
556 2016-11-03 Graham Markall <graham.markall@embecosm.com>
558 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
560 2016-11-03 Graham Markall <graham.markall@embecosm.com>
562 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
564 (find_format_long_instructions): Likewise.
565 * arc-opc.c (arc_opcode_len): New function.
567 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
569 * arc-nps400-tbl.h: Fix some instruction masks.
571 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
573 * i386-dis.c (REG_82): Removed.
574 (X86_64_82_REG_0): Likewise.
575 (X86_64_82_REG_1): Likewise.
576 (X86_64_82_REG_2): Likewise.
577 (X86_64_82_REG_3): Likewise.
578 (X86_64_82_REG_4): Likewise.
579 (X86_64_82_REG_5): Likewise.
580 (X86_64_82_REG_6): Likewise.
581 (X86_64_82_REG_7): Likewise.
583 (dis386): Use X86_64_82 instead of REG_82.
584 (reg_table): Remove REG_82.
585 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
586 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
587 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
590 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
593 * i386-dis.c (REG_82): New.
594 (X86_64_82_REG_0): Likewise.
595 (X86_64_82_REG_1): Likewise.
596 (X86_64_82_REG_2): Likewise.
597 (X86_64_82_REG_3): Likewise.
598 (X86_64_82_REG_4): Likewise.
599 (X86_64_82_REG_5): Likewise.
600 (X86_64_82_REG_6): Likewise.
601 (X86_64_82_REG_7): Likewise.
602 (dis386): Use REG_82.
603 (reg_table): Add REG_82.
604 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
605 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
606 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
608 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
610 * i386-dis.c (REG_82): Renamed to ...
613 (reg_table): Likewise.
615 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
617 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
618 * i386-dis-evex.h (evex_table): Updated.
619 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
620 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
621 (cpu_flags): Add CpuAVX512_4VNNIW.
622 * i386-opc.h (enum): (AVX512_4VNNIW): New.
623 (i386_cpu_flags): Add cpuavx512_4vnniw.
624 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
625 * i386-init.h: Regenerate.
628 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
630 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
631 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
632 * i386-dis-evex.h (evex_table): Updated.
633 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
634 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
635 (cpu_flags): Add CpuAVX512_4FMAPS.
636 (opcode_modifiers): Add ImplicitQuadGroup modifier.
637 * i386-opc.h (AVX512_4FMAP): New.
638 (i386_cpu_flags): Add cpuavx512_4fmaps.
639 (ImplicitQuadGroup): New.
640 (i386_opcode_modifier): Add implicitquadgroup.
641 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
642 * i386-init.h: Regenerate.
645 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
646 Andrew Waterman <andrew@sifive.com>
648 Add support for RISC-V architecture.
649 * configure.ac: Add entry for bfd_riscv_arch.
650 * configure: Regenerate.
651 * disassemble.c (disassembler): Add support for riscv.
652 (disassembler_usage): Likewise.
653 * riscv-dis.c: New file.
654 * riscv-opc.c: New file.
656 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
658 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
659 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
660 (rm_table): Update the RM_0FAE_REG_7 entry.
661 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
662 (cpu_flags): Remove CpuPCOMMIT.
663 * i386-opc.h (CpuPCOMMIT): Removed.
664 (i386_cpu_flags): Remove cpupcommit.
665 * i386-opc.tbl: Remove pcommit.
666 * i386-init.h: Regenerated.
667 * i386-tbl.h: Likewise.
669 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
672 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
673 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
674 32-bit mode. Don't check vex.register_specifier in 32-bit
676 (OP_VEX): Check for invalid mask registers.
678 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
681 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
684 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
687 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
689 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
691 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
692 local variable to `index_regno'.
694 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
696 * arc-tbl.h: Removed any "inv.+" instructions from the table.
698 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
700 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
703 2016-10-11 Jiong Wang <jiong.wang@arm.com>
706 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
708 2016-10-07 Jiong Wang <jiong.wang@arm.com>
711 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
714 2016-10-07 Alan Modra <amodra@gmail.com>
716 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
718 2016-10-06 Alan Modra <amodra@gmail.com>
720 * aarch64-opc.c: Spell fall through comments consistently.
721 * i386-dis.c: Likewise.
722 * aarch64-dis.c: Add missing fall through comments.
723 * aarch64-opc.c: Likewise.
724 * arc-dis.c: Likewise.
725 * arm-dis.c: Likewise.
726 * i386-dis.c: Likewise.
727 * m68k-dis.c: Likewise.
728 * mep-asm.c: Likewise.
729 * ns32k-dis.c: Likewise.
730 * sh-dis.c: Likewise.
731 * tic4x-dis.c: Likewise.
732 * tic6x-dis.c: Likewise.
733 * vax-dis.c: Likewise.
735 2016-10-06 Alan Modra <amodra@gmail.com>
737 * arc-ext.c (create_map): Add missing break.
738 * msp430-decode.opc (encode_as): Likewise.
739 * msp430-decode.c: Regenerate.
741 2016-10-06 Alan Modra <amodra@gmail.com>
743 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
744 * crx-dis.c (print_insn_crx): Likewise.
746 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
749 * i386-dis.c (putop): Don't assign alt twice.
751 2016-09-29 Jiong Wang <jiong.wang@arm.com>
754 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
756 2016-09-29 Alan Modra <amodra@gmail.com>
758 * ppc-opc.c (L): Make compulsory.
759 (LOPT): New, optional form of L.
760 (HTM_R): Define as LOPT.
762 (L32OPT): New, optional for 32-bit L.
763 (L2OPT): New, 2-bit L for dcbf.
766 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
767 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
769 <tlbiel, tlbie>: Use LOPT.
770 <wclr, wclrall>: Use L2.
772 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
774 * Makefile.in: Regenerate.
775 * configure: Likewise.
777 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
779 * arc-ext-tbl.h (EXTINSN2OPF): Define.
780 (EXTINSN2OP): Use EXTINSN2OPF.
781 (bspeekm, bspop, modapp): New extension instructions.
782 * arc-opc.c (F_DNZ_ND): Define.
787 * arc-tbl.h (dbnz): New instruction.
788 (prealloc): Allow it for ARC EM.
791 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
793 * aarch64-opc.c (print_immediate_offset_address): Print spaces
794 after commas in addresses.
795 (aarch64_print_operand): Likewise.
797 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
799 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
800 rather than "should be" or "expected to be" in error messages.
802 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
804 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
805 (print_mnemonic_name): ...here.
806 (print_comment): New function.
807 (print_aarch64_insn): Call it.
808 * aarch64-opc.c (aarch64_conds): Add SVE names.
809 (aarch64_print_operand): Print alternative condition names in
812 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
814 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
815 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
816 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
817 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
818 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
819 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
820 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
821 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
822 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
823 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
824 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
825 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
826 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
827 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
828 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
829 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
830 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
831 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
832 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
833 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
834 (OP_SVE_XWU, OP_SVE_XXU): New macros.
835 (aarch64_feature_sve): New variable.
837 (_SVE_INSN): Likewise.
838 (aarch64_opcode_table): Add SVE instructions.
839 * aarch64-opc.h (extract_fields): Declare.
840 * aarch64-opc-2.c: Regenerate.
841 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
842 * aarch64-asm-2.c: Regenerate.
843 * aarch64-dis.c (extract_fields): Make global.
844 (do_misc_decoding): Handle the new SVE aarch64_ops.
845 * aarch64-dis-2.c: Regenerate.
847 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
849 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
850 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
852 * aarch64-opc.c (fields): Add corresponding entries.
853 * aarch64-asm.c (aarch64_get_variant): New function.
854 (aarch64_encode_variant_using_iclass): Likewise.
855 (aarch64_opcode_encode): Call it.
856 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
857 (aarch64_opcode_decode): Call it.
859 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
861 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
862 and FP register operands.
863 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
864 (FLD_SVE_Vn): New aarch64_field_kinds.
865 * aarch64-opc.c (fields): Add corresponding entries.
866 (aarch64_print_operand): Handle the new SVE core and FP register
868 * aarch64-opc-2.c: Regenerate.
869 * aarch64-asm-2.c: Likewise.
870 * aarch64-dis-2.c: Likewise.
872 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
874 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
876 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
877 * aarch64-opc.c (fields): Add corresponding entry.
878 (operand_general_constraint_met_p): Handle the new SVE FP immediate
880 (aarch64_print_operand): Likewise.
881 * aarch64-opc-2.c: Regenerate.
882 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
883 (ins_sve_float_zero_one): New inserters.
884 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
885 (aarch64_ins_sve_float_half_two): Likewise.
886 (aarch64_ins_sve_float_zero_one): Likewise.
887 * aarch64-asm-2.c: Regenerate.
888 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
889 (ext_sve_float_zero_one): New extractors.
890 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
891 (aarch64_ext_sve_float_half_two): Likewise.
892 (aarch64_ext_sve_float_zero_one): Likewise.
893 * aarch64-dis-2.c: Regenerate.
895 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
897 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
898 integer immediate operands.
899 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
900 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
901 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
902 * aarch64-opc.c (fields): Add corresponding entries.
903 (operand_general_constraint_met_p): Handle the new SVE integer
905 (aarch64_print_operand): Likewise.
906 (aarch64_sve_dupm_mov_immediate_p): New function.
907 * aarch64-opc-2.c: Regenerate.
908 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
909 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
910 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
911 (aarch64_ins_limm): ...here.
912 (aarch64_ins_inv_limm): New function.
913 (aarch64_ins_sve_aimm): Likewise.
914 (aarch64_ins_sve_asimm): Likewise.
915 (aarch64_ins_sve_limm_mov): Likewise.
916 (aarch64_ins_sve_shlimm): Likewise.
917 (aarch64_ins_sve_shrimm): Likewise.
918 * aarch64-asm-2.c: Regenerate.
919 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
920 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
921 * aarch64-dis.c (decode_limm): New function, split out from...
922 (aarch64_ext_limm): ...here.
923 (aarch64_ext_inv_limm): New function.
924 (decode_sve_aimm): Likewise.
925 (aarch64_ext_sve_aimm): Likewise.
926 (aarch64_ext_sve_asimm): Likewise.
927 (aarch64_ext_sve_limm_mov): Likewise.
928 (aarch64_top_bit): Likewise.
929 (aarch64_ext_sve_shlimm): Likewise.
930 (aarch64_ext_sve_shrimm): Likewise.
931 * aarch64-dis-2.c: Regenerate.
933 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
935 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
937 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
938 the AARCH64_MOD_MUL_VL entry.
939 (value_aligned_p): Cope with non-power-of-two alignments.
940 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
941 (print_immediate_offset_address): Likewise.
942 (aarch64_print_operand): Likewise.
943 * aarch64-opc-2.c: Regenerate.
944 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
945 (ins_sve_addr_ri_s9xvl): New inserters.
946 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
947 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
948 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
949 * aarch64-asm-2.c: Regenerate.
950 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
951 (ext_sve_addr_ri_s9xvl): New extractors.
952 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
953 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
954 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
955 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
956 * aarch64-dis-2.c: Regenerate.
958 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
960 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
962 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
963 (FLD_SVE_xs_22): New aarch64_field_kinds.
964 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
965 (get_operand_specific_data): New function.
966 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
967 FLD_SVE_xs_14 and FLD_SVE_xs_22.
968 (operand_general_constraint_met_p): Handle the new SVE address
970 (sve_reg): New array.
971 (get_addr_sve_reg_name): New function.
972 (aarch64_print_operand): Handle the new SVE address operands.
973 * aarch64-opc-2.c: Regenerate.
974 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
975 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
976 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
977 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
978 (aarch64_ins_sve_addr_rr_lsl): Likewise.
979 (aarch64_ins_sve_addr_rz_xtw): Likewise.
980 (aarch64_ins_sve_addr_zi_u5): Likewise.
981 (aarch64_ins_sve_addr_zz): Likewise.
982 (aarch64_ins_sve_addr_zz_lsl): Likewise.
983 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
984 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
985 * aarch64-asm-2.c: Regenerate.
986 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
987 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
988 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
989 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
990 (aarch64_ext_sve_addr_ri_u6): Likewise.
991 (aarch64_ext_sve_addr_rr_lsl): Likewise.
992 (aarch64_ext_sve_addr_rz_xtw): Likewise.
993 (aarch64_ext_sve_addr_zi_u5): Likewise.
994 (aarch64_ext_sve_addr_zz): Likewise.
995 (aarch64_ext_sve_addr_zz_lsl): Likewise.
996 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
997 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
998 * aarch64-dis-2.c: Regenerate.
1000 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1002 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
1003 AARCH64_OPND_SVE_PATTERN_SCALED.
1004 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
1005 * aarch64-opc.c (fields): Add a corresponding entry.
1006 (set_multiplier_out_of_range_error): New function.
1007 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
1008 (operand_general_constraint_met_p): Handle
1009 AARCH64_OPND_SVE_PATTERN_SCALED.
1010 (print_register_offset_address): Use PRIi64 to print the
1012 (aarch64_print_operand): Likewise. Handle
1013 AARCH64_OPND_SVE_PATTERN_SCALED.
1014 * aarch64-opc-2.c: Regenerate.
1015 * aarch64-asm.h (ins_sve_scale): New inserter.
1016 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
1017 * aarch64-asm-2.c: Regenerate.
1018 * aarch64-dis.h (ext_sve_scale): New inserter.
1019 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
1020 * aarch64-dis-2.c: Regenerate.
1022 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1024 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
1025 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
1026 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
1027 (FLD_SVE_prfop): Likewise.
1028 * aarch64-opc.c: Include libiberty.h.
1029 (aarch64_sve_pattern_array): New variable.
1030 (aarch64_sve_prfop_array): Likewise.
1031 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
1032 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
1033 AARCH64_OPND_SVE_PRFOP.
1034 * aarch64-asm-2.c: Regenerate.
1035 * aarch64-dis-2.c: Likewise.
1036 * aarch64-opc-2.c: Likewise.
1038 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1040 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
1041 AARCH64_OPND_QLF_P_[ZM].
1042 (aarch64_print_operand): Print /z and /m where appropriate.
1044 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1046 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
1047 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
1048 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
1049 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
1050 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
1051 * aarch64-opc.c (fields): Add corresponding entries here.
1052 (operand_general_constraint_met_p): Check that SVE register lists
1053 have the correct length. Check the ranges of SVE index registers.
1054 Check for cases where p8-p15 are used in 3-bit predicate fields.
1055 (aarch64_print_operand): Handle the new SVE operands.
1056 * aarch64-opc-2.c: Regenerate.
1057 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
1058 * aarch64-asm.c (aarch64_ins_sve_index): New function.
1059 (aarch64_ins_sve_reglist): Likewise.
1060 * aarch64-asm-2.c: Regenerate.
1061 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
1062 * aarch64-dis.c (aarch64_ext_sve_index): New function.
1063 (aarch64_ext_sve_reglist): Likewise.
1064 * aarch64-dis-2.c: Regenerate.
1066 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1068 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1069 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1070 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1071 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1074 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1076 * aarch64-opc.c (get_offset_int_reg_name): New function.
1077 (print_immediate_offset_address): Likewise.
1078 (print_register_offset_address): Take the base and offset
1079 registers as parameters.
1080 (aarch64_print_operand): Update caller accordingly. Use
1081 print_immediate_offset_address.
1083 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1085 * aarch64-opc.c (BANK): New macro.
1086 (R32, R64): Take a register number as argument
1087 (int_reg): Use BANK.
1089 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1091 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1092 (aarch64_print_operand): Update accordingly.
1094 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1096 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1098 * aarch64-asm.h (ins_fpimm): New inserter.
1099 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1100 * aarch64-asm-2.c: Regenerate.
1101 * aarch64-dis.h (ext_fpimm): New extractor.
1102 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1103 (aarch64_ext_fpimm): New function.
1104 * aarch64-dis-2.c: Regenerate.
1106 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1108 * aarch64-asm.c: Include libiberty.h.
1109 (insert_fields): New function.
1110 (aarch64_ins_imm): Use it.
1111 * aarch64-dis.c (extract_fields): New function.
1112 (aarch64_ext_imm): Use it.
1114 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1116 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1117 with an esize parameter.
1118 (operand_general_constraint_met_p): Update accordingly.
1119 Fix misindented code.
1120 * aarch64-asm.c (aarch64_ins_limm): Update call to
1121 aarch64_logical_immediate_p.
1123 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1125 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1127 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1129 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1131 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1133 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1135 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1137 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1138 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1139 xor3>: Delete mnemonics.
1140 <cp_abort>: Rename mnemonic from ...
1141 <cpabort>: ...to this.
1142 <setb>: Change to a X form instruction.
1143 <sync>: Change to 1 operand form.
1144 <copy>: Delete mnemonic.
1145 <copy_first>: Rename mnemonic from ...
1147 <paste, paste.>: Delete mnemonics.
1148 <paste_last>: Rename mnemonic from ...
1149 <paste.>: ...to this.
1151 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1153 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1155 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1157 * s390-mkopc.c (main): Support alternate arch strings.
1159 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1161 * s390-opc.txt: Fix kmctr instruction type.
1163 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1165 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1166 * i386-init.h: Regenerated.
1168 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1170 * opcodes/arc-dis.c (print_insn_arc): Changed.
1172 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1174 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1177 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1179 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1180 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1181 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1183 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1185 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1186 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1187 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1188 PREFIX_MOD_3_0FAE_REG_4.
1189 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1190 PREFIX_MOD_3_0FAE_REG_4.
1191 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1192 (cpu_flags): Add CpuPTWRITE.
1193 * i386-opc.h (CpuPTWRITE): New.
1194 (i386_cpu_flags): Add cpuptwrite.
1195 * i386-opc.tbl: Add ptwrite instruction.
1196 * i386-init.h: Regenerated.
1197 * i386-tbl.h: Likewise.
1199 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1201 * arc-dis.h: Wrap around in extern "C".
1203 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1205 * aarch64-tbl.h (V8_2_INSN): New macro.
1206 (aarch64_opcode_table): Use it.
1208 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1210 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1211 CORE_INSN, __FP_INSN and SIMD_INSN.
1213 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1215 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1216 (aarch64_opcode_table): Update uses accordingly.
1218 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1219 Kwok Cheung Yeung <kcy@codesourcery.com>
1222 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1223 'e_cmplwi' to 'e_cmpli' instead.
1224 (OPVUPRT, OPVUPRT_MASK): Define.
1225 (powerpc_opcodes): Add E200Z4 insns.
1226 (vle_opcodes): Add context save/restore insns.
1228 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1230 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1231 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1234 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1236 * arc-nps400-tbl.h: Change block comments to GNU format.
1237 * arc-dis.c: Add new globals addrtypenames,
1238 addrtypenames_max, and addtypeunknown.
1239 (get_addrtype): New function.
1240 (print_insn_arc): Print colons and address types when
1242 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1243 define insert and extract functions for all address types.
1244 (arc_operands): Add operands for colon and all address
1246 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1247 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1248 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1249 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1250 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1251 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1253 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1255 * configure: Regenerated.
1257 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1259 * arc-dis.c (skipclass): New structure.
1260 (decodelist): New variable.
1261 (is_compatible_p): New function.
1262 (new_element): Likewise.
1263 (skip_class_p): Likewise.
1264 (find_format_from_table): Use skip_class_p function.
1265 (find_format): Decode first the extension instructions.
1266 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1268 (parse_option): New function.
1269 (parse_disassembler_options): Likewise.
1270 (print_arc_disassembler_options): Likewise.
1271 (print_insn_arc): Use parse_disassembler_options function. Proper
1272 select ARCv2 cpu variant.
1273 * disassemble.c (disassembler_usage): Add ARC disassembler
1276 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1278 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1279 annotation from the "nal" entry and reorder it beyond "bltzal".
1281 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1283 * sparc-opc.c (ldtxa): New macro.
1284 (sparc_opcodes): Use the macro defined above to add entries for
1285 the LDTXA instructions.
1286 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1289 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1291 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1294 2016-07-01 Jan Beulich <jbeulich@suse.com>
1296 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1297 (movzb): Adjust to cover all permitted suffixes.
1299 * i386-tbl.h: Re-generate.
1301 2016-07-01 Jan Beulich <jbeulich@suse.com>
1303 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1304 (lgdt): Remove Tbyte from non-64-bit variant.
1305 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1306 xsaves64, xsavec64): Remove Disp16.
1307 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1308 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1310 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1311 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1312 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1314 * i386-tbl.h: Re-generate.
1316 2016-07-01 Jan Beulich <jbeulich@suse.com>
1318 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1319 * i386-tbl.h: Re-generate.
1321 2016-06-30 Yao Qi <yao.qi@linaro.org>
1323 * arm-dis.c (print_insn): Fix typo in comment.
1325 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1327 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1328 range of ldst_elemlist operands.
1329 (print_register_list): Use PRIi64 to print the index.
1330 (aarch64_print_operand): Likewise.
1332 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1334 * mcore-opc.h: Remove sentinal.
1335 * mcore-dis.c (print_insn_mcore): Adjust.
1337 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1339 * arc-opc.c: Correct description of availability of NPS400
1342 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1344 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1345 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1346 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1347 xor3>: New mnemonics.
1348 <setb>: Change to a VX form instruction.
1349 (insert_sh6): Add support for rldixor.
1350 (extract_sh6): Likewise.
1352 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1354 * arc-ext.h: Wrap in extern C.
1356 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1358 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1359 Use same method for determining instruction length on ARC700 and
1361 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1362 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1363 with the NPS400 subclass.
1364 * arc-opc.c: Likewise.
1366 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1368 * sparc-opc.c (rdasr): New macro.
1374 (sparc_opcodes): Use the macros above to fix and expand the
1375 definition of read/write instructions from/to
1376 asr/privileged/hyperprivileged instructions.
1377 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1378 %hva_mask_nz. Prefer softint_set and softint_clear over
1379 set_softint and clear_softint.
1380 (print_insn_sparc): Support %ver in Rd.
1382 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1384 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1385 architecture according to the hardware capabilities they require.
1387 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1389 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1390 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1391 bfd_mach_sparc_v9{c,d,e,v,m}.
1392 * sparc-opc.c (MASK_V9C): Define.
1393 (MASK_V9D): Likewise.
1394 (MASK_V9E): Likewise.
1395 (MASK_V9V): Likewise.
1396 (MASK_V9M): Likewise.
1397 (v6): Add MASK_V9{C,D,E,V,M}.
1398 (v6notlet): Likewise.
1402 (v9andleon): Likewise.
1410 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1412 2016-06-15 Nick Clifton <nickc@redhat.com>
1414 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1415 constants to match expected behaviour.
1416 (nds32_parse_opcode): Likewise. Also for whitespace.
1418 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1420 * arc-opc.c (extract_rhv1): Extract value from insn.
1422 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1424 * arc-nps400-tbl.h: Add ldbit instruction.
1425 * arc-opc.c: Add flag classes required for ldbit.
1427 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1429 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1430 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1431 support the above instructions.
1433 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1435 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1436 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1437 csma, cbba, zncv, and hofs.
1438 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1439 support the above instructions.
1441 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1443 * arc-nps400-tbl.h: Add andab and orab instructions.
1445 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1447 * arc-nps400-tbl.h: Add addl-like instructions.
1449 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1451 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1453 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1455 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1458 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1460 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1462 (init_disasm): Handle new command line option "insnlength".
1463 (print_s390_disassembler_options): Mention new option in help
1465 (print_insn_s390): Use the encoded insn length when dumping
1466 unknown instructions.
1468 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1470 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1471 to the address and set as symbol address for LDS/ STS immediate operands.
1473 2016-06-07 Alan Modra <amodra@gmail.com>
1475 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1476 cpu for "vle" to e500.
1477 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1478 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1479 (PPCNONE): Delete, substitute throughout.
1480 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1481 except for major opcode 4 and 31.
1482 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1484 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1486 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1487 ARM_EXT_RAS in relevant entries.
1489 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1492 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1495 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1498 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1499 (indir_v_mode): New.
1500 Add comments for '&'.
1501 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1502 (putop): Handle '&'.
1503 (intel_operand_size): Handle indir_v_mode.
1504 (OP_E_register): Likewise.
1505 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1506 64-bit indirect call/jmp for AMD64.
1507 * i386-tbl.h: Regenerated
1509 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1511 * arc-dis.c (struct arc_operand_iterator): New structure.
1512 (find_format_from_table): All the old content from find_format,
1513 with some minor adjustments, and parameter renaming.
1514 (find_format_long_instructions): New function.
1515 (find_format): Rewritten.
1516 (arc_insn_length): Add LSB parameter.
1517 (extract_operand_value): New function.
1518 (operand_iterator_next): New function.
1519 (print_insn_arc): Use new functions to find opcode, and iterator
1521 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1522 (extract_nps_3bit_dst_short): New function.
1523 (insert_nps_3bit_src2_short): New function.
1524 (extract_nps_3bit_src2_short): New function.
1525 (insert_nps_bitop1_size): New function.
1526 (extract_nps_bitop1_size): New function.
1527 (insert_nps_bitop2_size): New function.
1528 (extract_nps_bitop2_size): New function.
1529 (insert_nps_bitop_mod4_msb): New function.
1530 (extract_nps_bitop_mod4_msb): New function.
1531 (insert_nps_bitop_mod4_lsb): New function.
1532 (extract_nps_bitop_mod4_lsb): New function.
1533 (insert_nps_bitop_dst_pos3_pos4): New function.
1534 (extract_nps_bitop_dst_pos3_pos4): New function.
1535 (insert_nps_bitop_ins_ext): New function.
1536 (extract_nps_bitop_ins_ext): New function.
1537 (arc_operands): Add new operands.
1538 (arc_long_opcodes): New global array.
1539 (arc_num_long_opcodes): New global.
1540 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1542 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1544 * nds32-asm.h: Add extern "C".
1545 * sh-opc.h: Likewise.
1547 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1549 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1550 0,b,limm to the rflt instruction.
1552 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1554 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1557 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1560 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1561 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1562 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1563 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1564 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1565 * i386-init.h: Regenerated.
1567 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1570 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1571 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1572 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1573 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1574 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1575 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1576 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1577 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1578 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1579 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1580 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1581 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1582 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1583 CpuRegMask for AVX512.
1584 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1586 (set_bitfield_from_cpu_flag_init): New function.
1587 (set_bitfield): Remove const on f. Call
1588 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1589 * i386-opc.h (CpuRegMMX): New.
1590 (CpuRegXMM): Likewise.
1591 (CpuRegYMM): Likewise.
1592 (CpuRegZMM): Likewise.
1593 (CpuRegMask): Likewise.
1594 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1596 * i386-init.h: Regenerated.
1597 * i386-tbl.h: Likewise.
1599 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1602 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1603 (opcode_modifiers): Add AMD64 and Intel64.
1604 (main): Properly verify CpuMax.
1605 * i386-opc.h (CpuAMD64): Removed.
1606 (CpuIntel64): Likewise.
1607 (CpuMax): Set to CpuNo64.
1608 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1610 (Intel64): Likewise.
1611 (i386_opcode_modifier): Add amd64 and intel64.
1612 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1614 * i386-init.h: Regenerated.
1615 * i386-tbl.h: Likewise.
1617 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1620 * i386-gen.c (main): Fail if CpuMax is incorrect.
1621 * i386-opc.h (CpuMax): Set to CpuIntel64.
1622 * i386-tbl.h: Regenerated.
1624 2016-05-27 Nick Clifton <nickc@redhat.com>
1627 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1628 (msp430dis_opcode_unsigned): New function.
1629 (msp430dis_opcode_signed): New function.
1630 (msp430_singleoperand): Use the new opcode reading functions.
1631 Only disassenmble bytes if they were successfully read.
1632 (msp430_doubleoperand): Likewise.
1633 (msp430_branchinstr): Likewise.
1634 (msp430x_callx_instr): Likewise.
1635 (print_insn_msp430): Check that it is safe to read bytes before
1636 attempting disassembly. Use the new opcode reading functions.
1638 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1640 * ppc-opc.c (CY): New define. Document it.
1641 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1643 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1645 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1646 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1647 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1648 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1650 * i386-init.h: Regenerated.
1652 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1655 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1656 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1657 * i386-init.h: Regenerated.
1659 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1661 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1662 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1663 * i386-init.h: Regenerated.
1665 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1667 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1669 (print_insn_arc): Set insn_type information.
1670 * arc-opc.c (C_CC): Add F_CLASS_COND.
1671 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1672 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1673 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1674 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1675 (brne, brne_s, jeq_s, jne_s): Likewise.
1677 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1679 * arc-tbl.h (neg): New instruction variant.
1681 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1683 * arc-dis.c (find_format, find_format, get_auxreg)
1684 (print_insn_arc): Changed.
1685 * arc-ext.h (INSERT_XOP): Likewise.
1687 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1689 * tic54x-dis.c (sprint_mmr): Adjust.
1690 * tic54x-opc.c: Likewise.
1692 2016-05-19 Alan Modra <amodra@gmail.com>
1694 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1696 2016-05-19 Alan Modra <amodra@gmail.com>
1698 * ppc-opc.c: Formatting.
1699 (NSISIGNOPT): Define.
1700 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1702 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1704 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1705 replacing references to `micromips_ase' throughout.
1706 (_print_insn_mips): Don't use file-level microMIPS annotation to
1707 determine the disassembly mode with the symbol table.
1709 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1711 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1713 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1715 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1717 * mips-opc.c (D34): New macro.
1718 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1720 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1722 * i386-dis.c (prefix_table): Add RDPID instruction.
1723 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1724 (cpu_flags): Add RDPID bitfield.
1725 * i386-opc.h (enum): Add RDPID element.
1726 (i386_cpu_flags): Add RDPID field.
1727 * i386-opc.tbl: Add RDPID instruction.
1728 * i386-init.h: Regenerate.
1729 * i386-tbl.h: Regenerate.
1731 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1733 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1734 branch type of a symbol.
1735 (print_insn): Likewise.
1737 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1739 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1740 Mainline Security Extensions instructions.
1741 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1742 Extensions instructions.
1743 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1745 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1748 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1750 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1752 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1754 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1755 (arcExtMap_genOpcode): Likewise.
1756 * arc-opc.c (arg_32bit_rc): Define new variable.
1757 (arg_32bit_u6): Likewise.
1758 (arg_32bit_limm): Likewise.
1760 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1762 * aarch64-gen.c (VERIFIER): Define.
1763 * aarch64-opc.c (VERIFIER): Define.
1764 (verify_ldpsw): Use static linkage.
1765 * aarch64-opc.h (verify_ldpsw): Remove.
1766 * aarch64-tbl.h: Use VERIFIER for verifiers.
1768 2016-04-28 Nick Clifton <nickc@redhat.com>
1771 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1772 * aarch64-opc.c (verify_ldpsw): New function.
1773 * aarch64-opc.h (verify_ldpsw): New prototype.
1774 * aarch64-tbl.h: Add initialiser for verifier field.
1775 (LDPSW): Set verifier to verify_ldpsw.
1777 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1781 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1782 smaller than address size.
1784 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1786 * alpha-dis.c: Regenerate.
1787 * crx-dis.c: Likewise.
1788 * disassemble.c: Likewise.
1789 * epiphany-opc.c: Likewise.
1790 * fr30-opc.c: Likewise.
1791 * frv-opc.c: Likewise.
1792 * ip2k-opc.c: Likewise.
1793 * iq2000-opc.c: Likewise.
1794 * lm32-opc.c: Likewise.
1795 * lm32-opinst.c: Likewise.
1796 * m32c-opc.c: Likewise.
1797 * m32r-opc.c: Likewise.
1798 * m32r-opinst.c: Likewise.
1799 * mep-opc.c: Likewise.
1800 * mt-opc.c: Likewise.
1801 * or1k-opc.c: Likewise.
1802 * or1k-opinst.c: Likewise.
1803 * tic80-opc.c: Likewise.
1804 * xc16x-opc.c: Likewise.
1805 * xstormy16-opc.c: Likewise.
1807 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1809 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1810 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1811 calcsd, and calcxd instructions.
1812 * arc-opc.c (insert_nps_bitop_size): Delete.
1813 (extract_nps_bitop_size): Delete.
1814 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1815 (extract_nps_qcmp_m3): Define.
1816 (extract_nps_qcmp_m2): Define.
1817 (extract_nps_qcmp_m1): Define.
1818 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1819 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1820 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1821 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1822 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1825 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1827 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1829 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1831 * Makefile.in: Regenerated with automake 1.11.6.
1832 * aclocal.m4: Likewise.
1834 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1836 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1838 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1839 (extract_nps_cmem_uimm16): New function.
1840 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1842 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1844 * arc-dis.c (arc_insn_length): New function.
1845 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1846 (find_format): Change insnLen parameter to unsigned.
1848 2016-04-13 Nick Clifton <nickc@redhat.com>
1851 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1852 the LD.B and LD.BU instructions.
1854 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1856 * arc-dis.c (find_format): Check for extension flags.
1857 (print_flags): New function.
1858 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1860 * arc-ext.c (arcExtMap_coreRegName): Use
1861 LAST_EXTENSION_CORE_REGISTER.
1862 (arcExtMap_coreReadWrite): Likewise.
1863 (dump_ARC_extmap): Update printing.
1864 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1865 (arc_aux_regs): Add cpu field.
1866 * arc-regs.h: Add cpu field, lower case name aux registers.
1868 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1870 * arc-tbl.h: Add rtsc, sleep with no arguments.
1872 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1874 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1876 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1877 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1878 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1879 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1880 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1881 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1882 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1883 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1884 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1885 (arc_opcode arc_opcodes): Null terminate the array.
1886 (arc_num_opcodes): Remove.
1887 * arc-ext.h (INSERT_XOP): Define.
1888 (extInstruction_t): Likewise.
1889 (arcExtMap_instName): Delete.
1890 (arcExtMap_insn): New function.
1891 (arcExtMap_genOpcode): Likewise.
1892 * arc-ext.c (ExtInstruction): Remove.
1893 (create_map): Zero initialize instruction fields.
1894 (arcExtMap_instName): Remove.
1895 (arcExtMap_insn): New function.
1896 (dump_ARC_extmap): More info while debuging.
1897 (arcExtMap_genOpcode): New function.
1898 * arc-dis.c (find_format): New function.
1899 (print_insn_arc): Use find_format.
1900 (arc_get_disassembler): Enable dump_ARC_extmap only when
1903 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1905 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1906 instruction bits out.
1908 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1910 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1911 * arc-opc.c (arc_flag_operands): Add new flags.
1912 (arc_flag_classes): Add new classes.
1914 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1916 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1918 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1920 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1921 encode1, rflt, crc16, and crc32 instructions.
1922 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1923 (arc_flag_classes): Add C_NPS_R.
1924 (insert_nps_bitop_size_2b): New function.
1925 (extract_nps_bitop_size_2b): Likewise.
1926 (insert_nps_bitop_uimm8): Likewise.
1927 (extract_nps_bitop_uimm8): Likewise.
1928 (arc_operands): Add new operand entries.
1930 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1932 * arc-regs.h: Add a new subclass field. Add double assist
1933 accumulator register values.
1934 * arc-tbl.h: Use DPA subclass to mark the double assist
1935 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1936 * arc-opc.c (RSP): Define instead of SP.
1937 (arc_aux_regs): Add the subclass field.
1939 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1941 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1943 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1945 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1948 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1950 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1951 issues. No functional changes.
1953 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1955 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1956 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1957 (RTT): Remove duplicate.
1958 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1959 (PCT_CONFIG*): Remove.
1960 (D1L, D1H, D2H, D2L): Define.
1962 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1964 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1966 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1968 * arc-tbl.h (invld07): Remove.
1969 * arc-ext-tbl.h: New file.
1970 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1971 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1973 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1975 Fix -Wstack-usage warnings.
1976 * aarch64-dis.c (print_operands): Substitute size.
1977 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1979 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1981 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1982 to get a proper diagnostic when an invalid ASR register is used.
1984 2016-03-22 Nick Clifton <nickc@redhat.com>
1986 * configure: Regenerate.
1988 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1990 * arc-nps400-tbl.h: New file.
1991 * arc-opc.c: Add top level comment.
1992 (insert_nps_3bit_dst): New function.
1993 (extract_nps_3bit_dst): New function.
1994 (insert_nps_3bit_src2): New function.
1995 (extract_nps_3bit_src2): New function.
1996 (insert_nps_bitop_size): New function.
1997 (extract_nps_bitop_size): New function.
1998 (arc_flag_operands): Add nps400 entries.
1999 (arc_flag_classes): Add nps400 entries.
2000 (arc_operands): Add nps400 entries.
2001 (arc_opcodes): Add nps400 include.
2003 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
2005 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
2006 the new class enum values.
2008 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
2010 * arc-dis.c (print_insn_arc): Handle nps400.
2012 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
2014 * arc-opc.c (BASE): Delete.
2016 2016-03-18 Nick Clifton <nickc@redhat.com>
2019 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
2020 of MOV insn that aliases an ORR insn.
2022 2016-03-16 Jiong Wang <jiong.wang@arm.com>
2024 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
2026 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
2028 * mcore-opc.h: Add const qualifiers.
2029 * microblaze-opc.h (struct op_code_struct): Likewise.
2030 * sh-opc.h: Likewise.
2031 * tic4x-dis.c (tic4x_print_indirect): Likewise.
2032 (tic4x_print_op): Likewise.
2034 2016-03-02 Alan Modra <amodra@gmail.com>
2036 * or1k-desc.h: Regenerate.
2037 * fr30-ibld.c: Regenerate.
2038 * rl78-decode.c: Regenerate.
2040 2016-03-01 Nick Clifton <nickc@redhat.com>
2043 * rl78-dis.c (print_insn_rl78_common): Fix typo.
2045 2016-02-24 Renlin Li <renlin.li@arm.com>
2047 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
2048 (print_insn_coprocessor): Support fp16 instructions.
2050 2016-02-24 Renlin Li <renlin.li@arm.com>
2052 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
2053 vminnm, vrint(mpna).
2055 2016-02-24 Renlin Li <renlin.li@arm.com>
2057 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
2058 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
2060 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
2062 * i386-dis.c (print_insn): Parenthesize expression to prevent
2063 truncated addresses.
2066 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
2067 Janek van Oirschot <jvanoirs@synopsys.com>
2069 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2072 2016-02-04 Nick Clifton <nickc@redhat.com>
2075 * msp430-dis.c (print_insn_msp430): Add a special case for
2076 decoding an RRC instruction with the ZC bit set in the extension
2079 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2081 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2082 * epiphany-ibld.c: Regenerate.
2083 * fr30-ibld.c: Regenerate.
2084 * frv-ibld.c: Regenerate.
2085 * ip2k-ibld.c: Regenerate.
2086 * iq2000-ibld.c: Regenerate.
2087 * lm32-ibld.c: Regenerate.
2088 * m32c-ibld.c: Regenerate.
2089 * m32r-ibld.c: Regenerate.
2090 * mep-ibld.c: Regenerate.
2091 * mt-ibld.c: Regenerate.
2092 * or1k-ibld.c: Regenerate.
2093 * xc16x-ibld.c: Regenerate.
2094 * xstormy16-ibld.c: Regenerate.
2096 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2098 * epiphany-dis.c: Regenerated from latest cpu files.
2100 2016-02-01 Michael McConville <mmcco@mykolab.com>
2102 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2105 2016-01-25 Renlin Li <renlin.li@arm.com>
2107 * arm-dis.c (mapping_symbol_for_insn): New function.
2108 (find_ifthen_state): Call mapping_symbol_for_insn().
2110 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2112 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2113 of MSR UAO immediate operand.
2115 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2117 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2118 instruction support.
2120 2016-01-17 Alan Modra <amodra@gmail.com>
2122 * configure: Regenerate.
2124 2016-01-14 Nick Clifton <nickc@redhat.com>
2126 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2127 instructions that can support stack pointer operations.
2128 * rl78-decode.c: Regenerate.
2129 * rl78-dis.c: Fix display of stack pointer in MOVW based
2132 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2134 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2135 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2136 erxtatus_el1 and erxaddr_el1.
2138 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2140 * arm-dis.c (arm_opcodes): Add "esb".
2141 (thumb_opcodes): Likewise.
2143 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2145 * ppc-opc.c <xscmpnedp>: Delete.
2146 <xvcmpnedp>: Likewise.
2147 <xvcmpnedp.>: Likewise.
2148 <xvcmpnesp>: Likewise.
2149 <xvcmpnesp.>: Likewise.
2151 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2154 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2157 2016-01-01 Alan Modra <amodra@gmail.com>
2159 Update year range in copyright notice of all files.
2161 For older changes see ChangeLog-2015
2163 Copyright (C) 2016 Free Software Foundation, Inc.
2165 Copying and distribution of this file, with or without modification,
2166 are permitted in any medium without royalty provided the copyright
2167 notice and this notice are preserved.
2173 version-control: never