opcodes/ChangeLog

   1 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
   2
   3         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
   4
   5 2020-05-11  Alan Modra  <amodra@gmail.com>
   6
   7         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
   8
   9 2020-05-11  Alan Modra  <amodra@gmail.com>
  10
  11         * ppc-dis.c (ppc_opts): Add "power10" entry.
  12         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
  13         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
  14
  15 2020-05-11  Nick Clifton  <nickc@redhat.com>
  16
  17         * po/fr.po: Updated French translation.
  18
  19 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
  20
  21         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
  22         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
  23         (operand_general_constraint_met_p): validate
  24         AARCH64_OPND_UNDEFINED.
  25         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  26         for FLD_imm16_2.
  27         * aarch64-asm-2.c: Regenerated.
  28         * aarch64-dis-2.c: Regenerated.
  29         * aarch64-opc-2.c: Regenerated.
  30
  31 2020-04-29  Nick Clifton  <nickc@redhat.com>
  32
  33         PR 22699
  34         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  35         and SETRC insns.
  36
  37 2020-04-29  Nick Clifton  <nickc@redhat.com>
  38
  39         * po/sv.po: Updated Swedish translation.
  40
  41 2020-04-29  Nick Clifton  <nickc@redhat.com>
  42
  43         PR 22699
  44         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  45         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  46         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  47         IMM0_8U case.
  48
  49 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  50
  51         PR 25848
  52         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  53         cmpi only on m68020up and cpu32.
  54
  55 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  56
  57         * aarch64-asm.c (aarch64_ins_none): New.
  58         * aarch64-asm.h (ins_none): New declaration.
  59         * aarch64-dis.c (aarch64_ext_none): New.
  60         * aarch64-dis.h (ext_none): New declaration.
  61         * aarch64-opc.c (aarch64_print_operand): Update case for
  62         AARCH64_OPND_BARRIER_PSB.
  63         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  64         (AARCH64_OPERANDS): Update inserter/extracter for
  65         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  66         * aarch64-asm-2.c: Regenerated.
  67         * aarch64-dis-2.c: Regenerated.
  68         * aarch64-opc-2.c: Regenerated.
  69
  70 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  71
  72         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  73         (aarch64_feature_ras, RAS): Likewise.
  74         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  75         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  76         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  77         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  78         * aarch64-asm-2.c: Regenerated.
  79         * aarch64-dis-2.c: Regenerated.
  80         * aarch64-opc-2.c: Regenerated.
  81
  82 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  83
  84         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  85         (print_insn_neon): Support disassembly of conditional
  86         instructions.
  87
  88 2020-02-16  David Faust  <david.faust@oracle.com>
  89
  90         * bpf-desc.c: Regenerate.
  91         * bpf-desc.h: Likewise.
  92         * bpf-opc.c: Regenerate.
  93         * bpf-opc.h: Likewise.
  94
  95 2020-04-07  Lili Cui  <lili.cui@intel.com>
  96
  97         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  98         (prefix_table): New instructions (see prefixes above).
  99         (rm_table): Likewise
 100         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 101         CPU_ANY_TSXLDTRK_FLAGS.
 102         (cpu_flags): Add CpuTSXLDTRK.
 103         * i386-opc.h (enum): Add CpuTSXLDTRK.
 104         (i386_cpu_flags): Add cputsxldtrk.
 105         * i386-opc.tbl: Add XSUSPLDTRK insns.
 106         * i386-init.h: Regenerate.
 107         * i386-tbl.h: Likewise.
 108
 109 2020-04-02  Lili Cui  <lili.cui@intel.com>
 110
 111         * i386-dis.c (prefix_table): New instructions serialize.
 112         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 113         CPU_ANY_SERIALIZE_FLAGS.
 114         (cpu_flags): Add CpuSERIALIZE.
 115         * i386-opc.h (enum): Add CpuSERIALIZE.
 116         (i386_cpu_flags): Add cpuserialize.
 117         * i386-opc.tbl: Add SERIALIZE insns.
 118         * i386-init.h: Regenerate.
 119         * i386-tbl.h: Likewise.
 120
 121 2020-03-26  Alan Modra  <amodra@gmail.com>
 122
 123         * disassemble.h (opcodes_assert): Declare.
 124         (OPCODES_ASSERT): Define.
 125         * disassemble.c: Don't include assert.h.  Include opintl.h.
 126         (opcodes_assert): New function.
 127         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 128         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 129         calculate maxlen.  Omit insn decoding when insn length exceeds
 130         maxlen.  Exit from nibble loop when looking for E, before
 131         accessing next data byte.  Move processing of E outside loop.
 132         Replace tests of maxlen in loop with assertions.
 133
 134 2020-03-26  Alan Modra  <amodra@gmail.com>
 135
 136         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 137
 138 2020-03-25  Alan Modra  <amodra@gmail.com>
 139
 140         * z80-dis.c (suffix): Init mybuf.
 141
 142 2020-03-22  Alan Modra  <amodra@gmail.com>
 143
 144         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 145         successflly read from section.
 146
 147 2020-03-22  Alan Modra  <amodra@gmail.com>
 148
 149         * arc-dis.c (find_format): Use ISO C string concatenation rather
 150         than line continuation within a string.  Don't access needs_limm
 151         before testing opcode != NULL.
 152
 153 2020-03-22  Alan Modra  <amodra@gmail.com>
 154
 155         * ns32k-dis.c (print_insn_arg): Update comment.
 156         (print_insn_ns32k): Reduce size of index_offset array, and
 157         initialize, passing -1 to print_insn_arg for args that are not
 158         an index.  Don't exit arg loop early.  Abort on bad arg number.
 159
 160 2020-03-22  Alan Modra  <amodra@gmail.com>
 161
 162         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 163         * s12z-opc.c: Formatting.
 164         (operands_f): Return an int.
 165         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 166         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 167         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 168         (exg_sex_discrim): Likewise.
 169         (create_immediate_operand, create_bitfield_operand),
 170         (create_register_operand_with_size, create_register_all_operand),
 171         (create_register_all16_operand, create_simple_memory_operand),
 172         (create_memory_operand, create_memory_auto_operand): Don't
 173         segfault on malloc failure.
 174         (z_ext24_decode): Return an int status, negative on fail, zero
 175         on success.
 176         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 177         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 178         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 179         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 180         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 181         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 182         (loop_primitive_decode, shift_decode, psh_pul_decode),
 183         (bit_field_decode): Similarly.
 184         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 185         to return value, update callers.
 186         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 187         Don't segfault on NULL operand.
 188         (decode_operation): Return OP_INVALID on first fail.
 189         (decode_s12z): Check all reads, returning -1 on fail.
 190
 191 2020-03-20  Alan Modra  <amodra@gmail.com>
 192
 193         * metag-dis.c (print_insn_metag): Don't ignore status from
 194         read_memory_func.
 195
 196 2020-03-20  Alan Modra  <amodra@gmail.com>
 197
 198         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 199         Initialize parts of buffer not written when handling a possible
 200         2-byte insn at end of section.  Don't attempt decoding of such
 201         an insn by the 4-byte machinery.
 202
 203 2020-03-20  Alan Modra  <amodra@gmail.com>
 204
 205         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 206         partially filled buffer.  Prevent lookup of 4-byte insns when
 207         only VLE 2-byte insns are possible due to section size.  Print
 208         ".word" rather than ".long" for 2-byte leftovers.
 209
 210 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 211
 212         PR 25641
 213         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 214
 215 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-dis.c (X86_64_0D): Rename to ...
 218         (X86_64_0E): ... this.
 219
 220 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 223         * Makefile.in: Regenerated.
 224
 225 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 228         3-operand pseudos.
 229         * i386-tbl.h: Re-generate.
 230
 231 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 234         vprot*, vpsha*, and vpshl*.
 235         * i386-tbl.h: Re-generate.
 236
 237 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 240         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 241         * i386-tbl.h: Re-generate.
 242
 243 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 244
 245         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 246         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 247         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 248         * i386-tbl.h: Re-generate.
 249
 250 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 251
 252         * i386-gen.c (struct template_arg, struct template_instance,
 253         struct template_param, struct template, templates,
 254         parse_template, expand_templates): New.
 255         (process_i386_opcodes): Various local variables moved to
 256         expand_templates. Call parse_template and expand_templates.
 257         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 263         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 264         register and memory source templates. Replace VexW= by VexW*
 265         where applicable.
 266         * i386-tbl.h: Re-generate.
 267
 268 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 271         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 272         * i386-tbl.h: Re-generate.
 273
 274 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 277         * i386-tbl.h: Re-generate.
 278
 279 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 282         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 283         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 284         VexW0 on SSE2AVX variants.
 285         (vmovq): Drop NoRex64 from XMM/XMM variants.
 286         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 287         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 288         applicable use VexW0.
 289         * i386-tbl.h: Re-generate.
 290
 291 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 294         * i386-opc.h (Rex64): Delete.
 295         (struct i386_opcode_modifier): Remove rex64 field.
 296         * i386-opc.tbl (crc32): Drop Rex64.
 297         Replace Rex64 with Size64 everywhere else.
 298         * i386-tbl.h: Re-generate.
 299
 300 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-dis.c (OP_E_memory): Exclude recording of used address
 303         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 304         addressed memory operands for MPX insns.
 305
 306 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 309         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 310         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 311         (ptwrite): Split into non-64-bit and 64-bit forms.
 312         * i386-tbl.h: Re-generate.
 313
 314 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 317         template.
 318         * i386-tbl.h: Re-generate.
 319
 320 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 323         (prefix_table): Move vmmcall here. Add vmgexit.
 324         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 325         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 326         (cpu_flags): Add CpuSEV_ES entry.
 327         * i386-opc.h (CpuSEV_ES): New.
 328         (union i386_cpu_flags): Add cpusev_es field.
 329         * i386-opc.tbl (vmgexit): New.
 330         * i386-init.h, i386-tbl.h: Re-generate.
 331
 332 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 335         with MnemonicSize.
 336         * i386-opc.h (IGNORESIZE): New.
 337         (DEFAULTSIZE): Likewise.
 338         (IgnoreSize): Removed.
 339         (DefaultSize): Likewise.
 340         (MnemonicSize): New.
 341         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 342         mnemonicsize.
 343         * i386-opc.tbl (IgnoreSize): New.
 344         (DefaultSize): Likewise.
 345         * i386-tbl.h: Regenerated.
 346
 347 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 348
 349         PR 25627
 350         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 351         instructions.
 352
 353 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         PR gas/25622
 356         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 357         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 358         * i386-tbl.h: Regenerated.
 359
 360 2020-02-26  Alan Modra  <amodra@gmail.com>
 361
 362         * aarch64-asm.c: Indent labels correctly.
 363         * aarch64-dis.c: Likewise.
 364         * aarch64-gen.c: Likewise.
 365         * aarch64-opc.c: Likewise.
 366         * alpha-dis.c: Likewise.
 367         * i386-dis.c: Likewise.
 368         * nds32-asm.c: Likewise.
 369         * nfp-dis.c: Likewise.
 370         * visium-dis.c: Likewise.
 371
 372 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 373
 374         * arc-regs.h (int_vector_base): Make it available for all ARC
 375         CPUs.
 376
 377 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 378
 379         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 380         changed.
 381
 382 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 383
 384         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 385         c.mv/c.li if rs1 is zero.
 386
 387 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 390         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 391         CPU_POPCNT_FLAGS.
 392         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 393         * i386-opc.h (CpuABM): Removed.
 394         (CpuPOPCNT): New.
 395         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 396         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 397         popcnt.  Remove CpuABM from lzcnt.
 398         * i386-init.h: Regenerated.
 399         * i386-tbl.h: Likewise.
 400
 401 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 404         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 405         VexW1 instead of open-coding them.
 406         * i386-tbl.h: Re-generate.
 407
 408 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-opc.tbl (AddrPrefixOpReg): Define.
 411         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 412         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 413         templates. Drop NoRex64.
 414         * i386-tbl.h: Re-generate.
 415
 416 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 417
 418         PR gas/6518
 419         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 420         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 421         into Intel syntax instance (with Unpsecified) and AT&T one
 422         (without).
 423         (vcvtneps2bf16): Likewise, along with folding the two so far
 424         separate ones.
 425         * i386-tbl.h: Re-generate.
 426
 427 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 428
 429         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 430         CPU_ANY_SSE4A_FLAGS.
 431
 432 2020-02-17  Alan Modra  <amodra@gmail.com>
 433
 434         * i386-gen.c (cpu_flag_init): Correct last change.
 435
 436 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 437
 438         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 439         CPU_ANY_SSE4_FLAGS.
 440
 441 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 444         (movzx): Likewise.
 445
 446 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 447
 448         PR gas/25438
 449         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 450         destination for Cpu64-only variant.
 451         (movzx): Fold patterns.
 452         * i386-tbl.h: Re-generate.
 453
 454 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 457         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 458         CPU_ANY_SSE4_FLAGS entry.
 459         * i386-init.h: Re-generate.
 460
 461 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 464         with Unspecified, making the present one AT&T syntax only.
 465         * i386-tbl.h: Re-generate.
 466
 467 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 468
 469         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 470         * i386-tbl.h: Re-generate.
 471
 472 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 473
 474         PR gas/24546
 475         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 476         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 477         Amd64 and Intel64 templates.
 478         (call, jmp): Likewise for far indirect variants. Dro
 479         Unspecified.
 480         * i386-tbl.h: Re-generate.
 481
 482 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 485         * i386-opc.h (ShortForm): Delete.
 486         (struct i386_opcode_modifier): Remove shortform field.
 487         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 488         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 489         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 490         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 491         Drop ShortForm.
 492         * i386-tbl.h: Re-generate.
 493
 494 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 497         fucompi): Drop ShortForm from operand-less templates.
 498         * i386-tbl.h: Re-generate.
 499
 500 2020-02-11  Alan Modra  <amodra@gmail.com>
 501
 502         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 503         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 504         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 505         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 506         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 507
 508 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 509
 510         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 511         (cde_opcodes): Add VCX* instructions.
 512
 513 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 514             Matthew Malcomson  <matthew.malcomson@arm.com>
 515
 516         * arm-dis.c (struct cdeopcode32): New.
 517         (CDE_OPCODE): New macro.
 518         (cde_opcodes): New disassembly table.
 519         (regnames): New option to table.
 520         (cde_coprocs): New global variable.
 521         (print_insn_cde): New
 522         (print_insn_thumb32): Use print_insn_cde.
 523         (parse_arm_disassembler_options): Parse coprocN args.
 524
 525 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         PR gas/25516
 528         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 529         with ISA64.
 530         * i386-opc.h (AMD64): Removed.
 531         (Intel64): Likewose.
 532         (AMD64): New.
 533         (INTEL64): Likewise.
 534         (INTEL64ONLY): Likewise.
 535         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 536         * i386-opc.tbl (Amd64): New.
 537         (Intel64): Likewise.
 538         (Intel64Only): Likewise.
 539         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 540         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 541         * i386-tbl.h: Regenerated.
 542
 543 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 544
 545         PR 25469
 546         * z80-dis.c: Add support for GBZ80 opcodes.
 547
 548 2020-02-04  Alan Modra  <amodra@gmail.com>
 549
 550         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 551
 552 2020-02-03  Alan Modra  <amodra@gmail.com>
 553
 554         * m32c-ibld.c: Regenerate.
 555
 556 2020-02-01  Alan Modra  <amodra@gmail.com>
 557
 558         * frv-ibld.c: Regenerate.
 559
 560 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 563         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 564         (OP_E_memory): Replace xmm_mdq_mode case label by
 565         vex_scalar_w_dq_mode one.
 566         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 567
 568 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 571         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 572         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 573         (intel_operand_size): Drop vex_w_dq_mode case label.
 574
 575 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 576
 577         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 578         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 579
 580 2020-01-30  Alan Modra  <amodra@gmail.com>
 581
 582         * m32c-ibld.c: Regenerate.
 583
 584 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 585
 586         * bpf-opc.c: Regenerate.
 587
 588 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 591         (dis386): Use them to replace C2/C3 table entries.
 592         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 593         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 594         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 595         * i386-tbl.h: Re-generate.
 596
 597 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 600         forms.
 601         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 602         DefaultSize.
 603         * i386-tbl.h: Re-generate.
 604
 605 2020-01-30  Alan Modra  <amodra@gmail.com>
 606
 607         * tic4x-dis.c (tic4x_dp): Make unsigned.
 608
 609 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 610             Jan Beulich  <jbeulich@suse.com>
 611
 612         PR binutils/25445
 613         * i386-dis.c (MOVSXD_Fixup): New function.
 614         (movsxd_mode): New enum.
 615         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 616         (intel_operand_size): Handle movsxd_mode.
 617         (OP_E_register): Likewise.
 618         (OP_G): Likewise.
 619         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 620         register on movsxd.  Add movsxd with 16-bit destination register
 621         for AMD64 and Intel64 ISAs.
 622         * i386-tbl.h: Regenerated.
 623
 624 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 625
 626         PR 25403
 627         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 628         * aarch64-asm-2.c: Regenerate
 629         * aarch64-dis-2.c: Likewise.
 630         * aarch64-opc-2.c: Likewise.
 631
 632 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-opc.tbl (sysret): Drop DefaultSize.
 635         * i386-tbl.h: Re-generate.
 636
 637 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 640         Dword.
 641         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 642         * i386-tbl.h: Re-generate.
 643
 644 2020-01-20  Nick Clifton  <nickc@redhat.com>
 645
 646         * po/de.po: Updated German translation.
 647         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 648         * po/uk.po: Updated Ukranian translation.
 649
 650 2020-01-20  Alan Modra  <amodra@gmail.com>
 651
 652         * hppa-dis.c (fput_const): Remove useless cast.
 653
 654 2020-01-20  Alan Modra  <amodra@gmail.com>
 655
 656         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 657
 658 2020-01-18  Nick Clifton  <nickc@redhat.com>
 659
 660         * configure: Regenerate.
 661         * po/opcodes.pot: Regenerate.
 662
 663 2020-01-18  Nick Clifton  <nickc@redhat.com>
 664
 665         Binutils 2.34 branch created.
 666
 667 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 668
 669         * opintl.h: Fix spelling error (seperate).
 670
 671 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         * i386-opc.tbl: Add {vex} pseudo prefix.
 674         * i386-tbl.h: Regenerated.
 675
 676 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 677
 678         PR 25376
 679         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 680         (neon_opcodes): Likewise.
 681         (select_arm_features): Make sure we enable MVE bits when selecting
 682         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 683         any architecture.
 684
 685 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-opc.tbl: Drop stale comment from XOP section.
 688
 689 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 692         (extractps): Add VexWIG to SSE2AVX forms.
 693         * i386-tbl.h: Re-generate.
 694
 695 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 698         Size64 from and use VexW1 on SSE2AVX forms.
 699         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 700         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 701         * i386-tbl.h: Re-generate.
 702
 703 2020-01-15  Alan Modra  <amodra@gmail.com>
 704
 705         * tic4x-dis.c (tic4x_version): Make unsigned long.
 706         (optab, optab_special, registernames): New file scope vars.
 707         (tic4x_print_register): Set up registernames rather than
 708         malloc'd registertable.
 709         (tic4x_disassemble): Delete optable and optable_special.  Use
 710         optab and optab_special instead.  Throw away old optab,
 711         optab_special and registernames when info->mach changes.
 712
 713 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 714
 715         PR 25377
 716         * z80-dis.c (suffix): Use .db instruction to generate double
 717         prefix.
 718
 719 2020-01-14  Alan Modra  <amodra@gmail.com>
 720
 721         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 722         values to unsigned before shifting.
 723
 724 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 725
 726         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 727         flow instructions.
 728         (print_insn_thumb16, print_insn_thumb32): Likewise.
 729         (print_insn): Initialize the insn info.
 730         * i386-dis.c (print_insn): Initialize the insn info fields, and
 731         detect jumps.
 732
 733 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 734
 735         * arc-opc.c (C_NE): Make it required.
 736
 737 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 738
 739         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 740         reserved register name.
 741
 742 2020-01-13  Alan Modra  <amodra@gmail.com>
 743
 744         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 745         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 746
 747 2020-01-13  Alan Modra  <amodra@gmail.com>
 748
 749         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 750         result of wasm_read_leb128 in a uint64_t and check that bits
 751         are not lost when copying to other locals.  Use uint32_t for
 752         most locals.  Use PRId64 when printing int64_t.
 753
 754 2020-01-13  Alan Modra  <amodra@gmail.com>
 755
 756         * score-dis.c: Formatting.
 757         * score7-dis.c: Formatting.
 758
 759 2020-01-13  Alan Modra  <amodra@gmail.com>
 760
 761         * score-dis.c (print_insn_score48): Use unsigned variables for
 762         unsigned values.  Don't left shift negative values.
 763         (print_insn_score32): Likewise.
 764         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 765
 766 2020-01-13  Alan Modra  <amodra@gmail.com>
 767
 768         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 769
 770 2020-01-13  Alan Modra  <amodra@gmail.com>
 771
 772         * fr30-ibld.c: Regenerate.
 773
 774 2020-01-13  Alan Modra  <amodra@gmail.com>
 775
 776         * xgate-dis.c (print_insn): Don't left shift signed value.
 777         (ripBits): Formatting, use 1u.
 778
 779 2020-01-10  Alan Modra  <amodra@gmail.com>
 780
 781         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 782         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 783
 784 2020-01-10  Alan Modra  <amodra@gmail.com>
 785
 786         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 787         and XRREG value earlier to avoid a shift with negative exponent.
 788         * m10200-dis.c (disassemble): Similarly.
 789
 790 2020-01-09  Nick Clifton  <nickc@redhat.com>
 791
 792         PR 25224
 793         * z80-dis.c (ld_ii_ii): Use correct cast.
 794
 795 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 796
 797         PR 25224
 798         * z80-dis.c (ld_ii_ii): Use character constant when checking
 799         opcode byte value.
 800
 801 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-dis.c (SEP_Fixup): New.
 804         (SEP): Define.
 805         (dis386_twobyte): Use it for sysenter/sysexit.
 806         (enum x86_64_isa): Change amd64 enumerator to value 1.
 807         (OP_J): Compare isa64 against intel64 instead of amd64.
 808         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 809         forms.
 810         * i386-tbl.h: Re-generate.
 811
 812 2020-01-08  Alan Modra  <amodra@gmail.com>
 813
 814         * z8k-dis.c: Include libiberty.h
 815         (instr_data_s): Make max_fetched unsigned.
 816         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 817         Don't exceed byte_info bounds.
 818         (output_instr): Make num_bytes unsigned.
 819         (unpack_instr): Likewise for nibl_count and loop.
 820         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 821         idx unsigned.
 822         * z8k-opc.h: Regenerate.
 823
 824 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 825
 826         * arc-tbl.h (llock): Use 'LLOCK' as class.
 827         (llockd): Likewise.
 828         (scond): Use 'SCOND' as class.
 829         (scondd): Likewise.
 830         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 831         (scondd): Likewise.
 832
 833 2020-01-06  Alan Modra  <amodra@gmail.com>
 834
 835         * m32c-ibld.c: Regenerate.
 836
 837 2020-01-06  Alan Modra  <amodra@gmail.com>
 838
 839         PR 25344
 840         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 841         Peek at next byte to prevent recursion on repeated prefix bytes.
 842         Ensure uninitialised "mybuf" is not accessed.
 843         (print_insn_z80): Don't zero n_fetch and n_used here,..
 844         (print_insn_z80_buf): ..do it here instead.
 845
 846 2020-01-04  Alan Modra  <amodra@gmail.com>
 847
 848         * m32r-ibld.c: Regenerate.
 849
 850 2020-01-04  Alan Modra  <amodra@gmail.com>
 851
 852         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 853
 854 2020-01-04  Alan Modra  <amodra@gmail.com>
 855
 856         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 857
 858 2020-01-04  Alan Modra  <amodra@gmail.com>
 859
 860         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 861
 862 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 863
 864         * aarch64-tbl.h (aarch64_opcode_table): Use
 865         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 866
 867 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 868
 869         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 870         forms of SUDOT and USDOT.
 871
 872 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 873
 874         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 875         uzip{1,2}.
 876         * opcodes/aarch64-dis-2.c: Re-generate.
 877
 878 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 879
 880         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 881         FMMLA encoding.
 882         * opcodes/aarch64-dis-2.c: Re-generate.
 883
 884 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 885
 886         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 887
 888 2020-01-01  Alan Modra  <amodra@gmail.com>
 889
 890         Update year range in copyright notice of all files.
 891
 892 For older changes see ChangeLog-2019
 893 \f
 894 Copyright (C) 2020 Free Software Foundation, Inc.
 895
 896 Copying and distribution of this file, with or without modification,
 897 are permitted in any medium without royalty provided the copyright
 898 notice and this notice are preserved.
 899
 900 Local Variables:
 901 mode: change-log
 902 left-margin: 8
 903 fill-column: 74
 904 version-control: never
 905 End: