opcodes/ChangeLog

   1 2017-07-03  Tristan Gingold  <gingold@adacore.com>
   2
   3         * po/opcodes.pot: Regenerate.
   4
   5 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
   6
   7         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
   8         entries to the MSA ASE instruction block.
   9
  10 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  11             Maciej W. Rozycki  <macro@imgtec.com>
  12
  13         * micromips-opc.c (XPA, XPAVZ): New macros.
  14         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
  15         "mthgc0".
  16
  17 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  18             Maciej W. Rozycki  <macro@imgtec.com>
  19
  20         * micromips-opc.c (I36): New macro.
  21         (micromips_opcodes): Add "eretnc".
  22
  23 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  24             Andrew Bennett  <andrew.bennett@imgtec.com>
  25
  26         * mips-dis.c (mips_calculate_combination_ases): Handle the
  27         ASE_XPA_VIRT flag.
  28         (parse_mips_ase_option): New function.
  29         (parse_mips_dis_option): Factor out ASE option handling to the
  30         new function.  Call `mips_calculate_combination_ases'.
  31         * mips-opc.c (XPAVZ): New macro.
  32         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
  33         "mfhgc0", "mthc0" and "mthgc0".
  34
  35 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
  36
  37         * mips-dis.c (mips_calculate_combination_ases): New function.
  38         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
  39         calculation to the new function.
  40         (set_default_mips_dis_options): Call the new function.
  41
  42 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  43
  44         * arc-dis.c (parse_disassembler_options): Use
  45         FOR_EACH_DISASSEMBLER_OPTION.
  46
  47 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  48
  49         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
  50         disassembler option strings.
  51         (parse_cpu_option): Likewise.
  52
  53 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
  54
  55         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
  56         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
  57         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
  58         (aarch64_feature_dotprod, DOT_INSN): New.
  59         (udot, sdot): New.
  60         * aarch64-dis-2.c: Regenerated.
  61
  62 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
  63
  64         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
  65
  66 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
  67             Matthew Fortune  <matthew.fortune@imgtec.com>
  68             Andrew Bennett  <andrew.bennett@imgtec.com>
  69
  70         * mips-formats.h (INT_BIAS): New macro.
  71         (INT_ADJ): Redefine in INT_BIAS terms.
  72         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  73         (mips_print_save_restore): New function.
  74         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  75         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  76         call.
  77         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  78         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  79         OP_SAVE_RESTORE_LIST handling, factored out from here.
  80         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  81         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  82         (mips_builtin_opcodes): Add "restore" and "save" entries.
  83         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  84         (IAMR2): New macro.
  85         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  86
  87 2017-06-23  Andrew Waterman  <andrew@sifive.com>
  88
  89         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
  90         alias; do not mark SLTI instruction as an alias.
  91
  92 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         * i386-dis.c (RM_0FAE_REG_5): Removed.
  95         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  96         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
  97         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
  98         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
  99         PREFIX_MOD_3_0F01_REG_5_RM_0.
 100         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 101         PREFIX_MOD_3_0FAE_REG_5.
 102         (mod_table): Update MOD_0FAE_REG_5.
 103         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 104         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 105         * i386-tbl.h: Regenerated.
 106
 107 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 108
 109         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 110         * i386-opc.tbl: Likewise.
 111         * i386-tbl.h: Regenerated.
 112
 113 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 116         and "jmp{&|}".
 117         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 118         prefix.
 119
 120 2017-06-19  Nick Clifton  <nickc@redhat.com>
 121
 122         PR binutils/21614
 123         * score-dis.c (score_opcodes): Add sentinel.
 124
 125 2017-06-16  Alan Modra  <amodra@gmail.com>
 126
 127         * rx-decode.c: Regenerate.
 128
 129 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         PR binutils/21594
 132         * i386-dis.c (OP_E_register): Check valid bnd register.
 133         (OP_G): Likewise.
 134
 135 2017-06-15  Nick Clifton  <nickc@redhat.com>
 136
 137         PR binutils/21595
 138         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 139         range value.
 140
 141 2017-06-15  Nick Clifton  <nickc@redhat.com>
 142
 143         PR binutils/21588
 144         * rl78-decode.opc (OP_BUF_LEN): Define.
 145         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 146         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 147         array.
 148         * rl78-decode.c: Regenerate.
 149
 150 2017-06-15  Nick Clifton  <nickc@redhat.com>
 151
 152         PR binutils/21586
 153         * bfin-dis.c (gregs): Clip index to prevent overflow.
 154         (regs): Likewise.
 155         (regs_lo): Likewise.
 156         (regs_hi): Likewise.
 157
 158 2017-06-14  Nick Clifton  <nickc@redhat.com>
 159
 160         PR binutils/21576
 161         * score7-dis.c (score_opcodes): Add sentinel.
 162
 163 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 164
 165         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 166         * arm-dis.c: Likewise.
 167         * ia64-dis.c: Likewise.
 168         * mips-dis.c: Likewise.
 169         * spu-dis.c: Likewise.
 170         * disassemble.h (print_insn_aarch64): New declaration, moved from
 171         include/dis-asm.h.
 172         (print_insn_big_arm, print_insn_big_mips): Likewise.
 173         (print_insn_i386, print_insn_ia64): Likewise.
 174         (print_insn_little_arm, print_insn_little_mips): Likewise.
 175
 176 2017-06-14  Nick Clifton  <nickc@redhat.com>
 177
 178         PR binutils/21587
 179         * rx-decode.opc: Include libiberty.h
 180         (GET_SCALE): New macro - validates access to SCALE array.
 181         (GET_PSCALE): New macro - validates access to PSCALE array.
 182         (DIs, SIs, S2Is, rx_disp): Use new macros.
 183         * rx-decode.c: Regenerate.
 184
 185 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 186
 187         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 188
 189 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 190
 191         * arc-dis.c (enforced_isa_mask): Declare.
 192         (cpu_types): Likewise.
 193         (parse_cpu_option): New function.
 194         (parse_disassembler_options): Use it.
 195         (print_insn_arc): Use enforced_isa_mask.
 196         (print_arc_disassembler_options): Document new options.
 197
 198 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 199
 200         * alpha-dis.c: Include disassemble.h, don't include
 201         dis-asm.h.
 202         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 203         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 204         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 205         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 206         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 207         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 208         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 209         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 210         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 211         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 212         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 213         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 214         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 215         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 216         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 217         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 218         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 219         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 220         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 221         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 222         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 223         * z80-dis.c, z8k-dis.c: Likewise.
 224         * disassemble.h: New file.
 225
 226 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 227
 228         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 229         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 230
 231 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 232
 233         * disassemble.c (disassembler): Add arguments a, big and mach.
 234         Use them.
 235
 236 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         * i386-dis.c (NOTRACK_Fixup): New.
 239         (NOTRACK): Likewise.
 240         (NOTRACK_PREFIX): Likewise.
 241         (last_active_prefix): Likewise.
 242         (reg_table): Use NOTRACK on indirect call and jmp.
 243         (ckprefix): Set last_active_prefix.
 244         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 245         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 246         * i386-opc.h (NoTrackPrefixOk): New.
 247         (i386_opcode_modifier): Add notrackprefixok.
 248         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 249         Add notrack.
 250         * i386-tbl.h: Regenerated.
 251
 252 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 253
 254         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 255         (X_IMM2): Define.
 256         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 257         bfd_mach_sparc_v9m8.
 258         (print_insn_sparc): Handle new operand types.
 259         * sparc-opc.c (MASK_M8): Define.
 260         (v6): Add MASK_M8.
 261         (v6notlet): Likewise.
 262         (v7): Likewise.
 263         (v8): Likewise.
 264         (v9): Likewise.
 265         (v9a): Likewise.
 266         (v9b): Likewise.
 267         (v9c): Likewise.
 268         (v9d): Likewise.
 269         (v9e): Likewise.
 270         (v9v): Likewise.
 271         (v9m): Likewise.
 272         (v9andleon): Likewise.
 273         (m8): Define.
 274         (HWS_VM8): Define.
 275         (HWS2_VM8): Likewise.
 276         (sparc_opcode_archs): Add entry for "m8".
 277         (sparc_opcodes): Add OSA2017 and M8 instructions
 278         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 279         fpx{ll,ra,rl}64x,
 280         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 281         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 282         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 283         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 284         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 285         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 286         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 287         ASI_CORE_SELECT_COMMIT_NHT.
 288
 289 2017-05-18  Alan Modra  <amodra@gmail.com>
 290
 291         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 292         * aarch64-dis.c: Likewise.
 293         * aarch64-gen.c: Likewise.
 294         * aarch64-opc.c: Likewise.
 295
 296 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 297             Matthew Fortune  <matthew.fortune@imgtec.com>
 298
 299         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 300         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 301         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 302         (print_insn_arg) <OP_REG28>: Add handler.
 303         (validate_insn_args) <OP_REG28>: Handle.
 304         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 305         32-bit encoding and 9-bit immediates.
 306         (print_insn_mips16): Handle MIPS16 instructions that require
 307         32-bit encoding and MFC0/MTC0 operand decoding.
 308         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 309         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 310         (RD_C0, WR_C0, E2, E2MT): New macros.
 311         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 312         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 313         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 314         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 315         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 316         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 317         instructions, "swl", "swr", "sync" and its "sync_acquire",
 318         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 319         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 320         regular/extended entries for original MIPS16 ISA revision
 321         instructions whose extended forms are subdecoded in the MIPS16e2
 322         ISA revision: "li", "sll" and "srl".
 323
 324 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 325
 326         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 327         reference in CP0 move operand decoding.
 328
 329 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 330
 331         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 332         type to hexadecimal.
 333         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 334
 335 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 336
 337         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 338         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 339         "sync_rmb" and "sync_wmb" as aliases.
 340         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 341         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 342
 343 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 344
 345         * arc-dis.c (parse_option): Update quarkse_em option..
 346         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 347         QUARKSE1.
 348         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 349
 350 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 351
 352         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 353
 354 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 355
 356         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 357         register.
 358
 359 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 360
 361         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 362         and branches and not synthetic data instructions.
 363
 364 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 365
 366         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 367
 368 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 369
 370         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 371         * arc-opc.c (insert_r13el): New function.
 372         (R13_EL): Define.
 373         * arc-tbl.h: Add new enter/leave variants.
 374
 375 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 376
 377         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 378
 379 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 380
 381         * mips-dis.c (print_mips_disassembler_options): Add
 382         `no-aliases'.
 383
 384 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 385
 386         * mips16-opc.c (AL): New macro.
 387         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 388         of "ld" and "lw" as aliases.
 389
 390 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 391
 392         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 393         arguments.
 394
 395 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 396             Alan Modra  <amodra@gmail.com>
 397
 398         * ppc-opc.c (ELEV): Define.
 399         (vle_opcodes): Add se_rfgi and e_sc.
 400         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 401         for E200Z4.
 402
 403 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 404
 405         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 406
 407 2017-04-21  Nick Clifton  <nickc@redhat.com>
 408
 409         PR binutils/21380
 410         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 411         LD3R and LD4R.
 412
 413 2017-04-13  Alan Modra  <amodra@gmail.com>
 414
 415         * epiphany-desc.c: Regenerate.
 416         * fr30-desc.c: Regenerate.
 417         * frv-desc.c: Regenerate.
 418         * ip2k-desc.c: Regenerate.
 419         * iq2000-desc.c: Regenerate.
 420         * lm32-desc.c: Regenerate.
 421         * m32c-desc.c: Regenerate.
 422         * m32r-desc.c: Regenerate.
 423         * mep-desc.c: Regenerate.
 424         * mt-desc.c: Regenerate.
 425         * or1k-desc.c: Regenerate.
 426         * xc16x-desc.c: Regenerate.
 427         * xstormy16-desc.c: Regenerate.
 428
 429 2017-04-11  Alan Modra  <amodra@gmail.com>
 430
 431         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 432         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 433         PPC_OPCODE_TMR for e6500.
 434         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 435         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 436         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 437         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 438         (PPCHTM): Define as PPC_OPCODE_POWER8.
 439         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 440
 441 2017-04-10  Alan Modra  <amodra@gmail.com>
 442
 443         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 444         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 445         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 446         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 447
 448 2017-04-09  Pip Cet  <pipcet@gmail.com>
 449
 450         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 451         appropriate floating-point precision directly.
 452
 453 2017-04-07  Alan Modra  <amodra@gmail.com>
 454
 455         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 456         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 457         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 458         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 459         vector instructions with E6500 not PPCVEC2.
 460
 461 2017-04-06  Pip Cet  <pipcet@gmail.com>
 462
 463         * Makefile.am: Add wasm32-dis.c.
 464         * configure.ac: Add wasm32-dis.c to wasm32 target.
 465         * disassemble.c: Add wasm32 disassembler code.
 466         * wasm32-dis.c: New file.
 467         * Makefile.in: Regenerate.
 468         * configure: Regenerate.
 469         * po/POTFILES.in: Regenerate.
 470         * po/opcodes.pot: Regenerate.
 471
 472 2017-04-05  Pedro Alves  <palves@redhat.com>
 473
 474         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 475         * arm-dis.c (parse_arm_disassembler_options): Constify.
 476         * ppc-dis.c (powerpc_init_dialect): Constify local.
 477         * vax-dis.c (parse_disassembler_options): Constify.
 478
 479 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 480
 481         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 482         RISCV_GP_SYMBOL.
 483
 484 2017-03-30  Pip Cet  <pipcet@gmail.com>
 485
 486         * configure.ac: Add (empty) bfd_wasm32_arch target.
 487         * configure: Regenerate
 488         * po/opcodes.pot: Regenerate.
 489
 490 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 491
 492         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 493         OSA2015.
 494         * opcodes/sparc-opc.c (asi_table): New ASIs.
 495
 496 2017-03-29  Alan Modra  <amodra@gmail.com>
 497
 498         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 499         "raw" option.
 500         (lookup_powerpc): Don't special case -1 dialect.  Handle
 501         PPC_OPCODE_RAW.
 502         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 503         lookup_powerpc call, pass it on second.
 504
 505 2017-03-27  Alan Modra  <amodra@gmail.com>
 506
 507         PR 21303
 508         * ppc-dis.c (struct ppc_mopt): Comment.
 509         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 510
 511 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 512
 513         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 514         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 515         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 516         (insert_nps_misc_imm_offset): New function.
 517         (extract_nps_misc imm_offset): New function.
 518         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 519         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 520
 521 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 522
 523         * s390-mkopc.c (main): Remove vx2 check.
 524         * s390-opc.txt: Remove vx2 instruction flags.
 525
 526 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 527
 528         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 529         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 530         (insert_nps_imm_offset): New function.
 531         (extract_nps_imm_offset): New function.
 532         (insert_nps_imm_entry): New function.
 533         (extract_nps_imm_entry): New function.
 534
 535 2017-03-17  Alan Modra  <amodra@gmail.com>
 536
 537         PR 21248
 538         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 539         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 540         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 541
 542 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 543
 544         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 545         <c.andi>: Likewise.
 546         <c.addiw> Likewise.
 547
 548 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 549
 550         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 551
 552 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 553
 554         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 555         <srl> Likewise.
 556         <srai> Likewise.
 557         <sra> Likewise.
 558
 559 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * i386-gen.c (opcode_modifiers): Replace S with Load.
 562         * i386-opc.h (S): Removed.
 563         (Load): New.
 564         (i386_opcode_modifier): Replace s with load.
 565         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 566         and {evex}.  Replace S with Load.
 567         * i386-tbl.h: Regenerated.
 568
 569 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 570
 571         * i386-opc.tbl: Use CpuCET on rdsspq.
 572         * i386-tbl.h: Regenerated.
 573
 574 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 575
 576         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 577         <vsx>: Do not use PPC_OPCODE_VSX3;
 578
 579 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 580
 581         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 582
 583 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 584
 585         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 586         (MOD_0F1E_PREFIX_1): Likewise.
 587         (MOD_0F38F5_PREFIX_2): Likewise.
 588         (MOD_0F38F6_PREFIX_0): Likewise.
 589         (RM_0F1E_MOD_3_REG_7): Likewise.
 590         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 591         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 592         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 593         (PREFIX_0F1E): Likewise.
 594         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 595         (PREFIX_0F38F5): Likewise.
 596         (dis386_twobyte): Use PREFIX_0F1E.
 597         (reg_table): Add REG_0F1E_MOD_3.
 598         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 599         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 600         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 601         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 602         (three_byte_table): Use PREFIX_0F38F5.
 603         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 604         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 605         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 606         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 607         PREFIX_MOD_3_0F01_REG_5_RM_2.
 608         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 609         (cpu_flags): Add CpuCET.
 610         * i386-opc.h (CpuCET): New enum.
 611         (CpuUnused): Commented out.
 612         (i386_cpu_flags): Add cpucet.
 613         * i386-opc.tbl: Add Intel CET instructions.
 614         * i386-init.h: Regenerated.
 615         * i386-tbl.h: Likewise.
 616
 617 2017-03-06  Alan Modra  <amodra@gmail.com>
 618
 619         PR 21124
 620         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 621         (extract_raq, extract_ras, extract_rbx): New functions.
 622         (powerpc_operands): Use opposite corresponding insert function.
 623         (Q_MASK): Define.
 624         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 625         register restriction.
 626
 627 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 628
 629         * disassemble.c Include "safe-ctype.h".
 630         (disassemble_init_for_target): Handle s390 init.
 631         (remove_whitespace_and_extra_commas): New function.
 632         (disassembler_options_cmp): Likewise.
 633         * arm-dis.c: Include "libiberty.h".
 634         (NUM_ELEM): Delete.
 635         (regnames): Use long disassembler style names.
 636         Add force-thumb and no-force-thumb options.
 637         (NUM_ARM_REGNAMES): Rename from this...
 638         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 639         (get_arm_regname_num_options): Delete.
 640         (set_arm_regname_option): Likewise.
 641         (get_arm_regnames): Likewise.
 642         (parse_disassembler_options): Likewise.
 643         (parse_arm_disassembler_option): Rename from this...
 644         (parse_arm_disassembler_options): ...to this.  Make static.
 645         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 646         (print_insn): Use parse_arm_disassembler_options.
 647         (disassembler_options_arm): New function.
 648         (print_arm_disassembler_options): Handle updated regnames.
 649         * ppc-dis.c: Include "libiberty.h".
 650         (ppc_opts): Add "32" and "64" entries.
 651         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 652         (powerpc_init_dialect): Add break to switch statement.
 653         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 654         (disassembler_options_powerpc): New function.
 655         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 656         Remove printing of "32" and "64".
 657         * s390-dis.c: Include "libiberty.h".
 658         (init_flag): Remove unneeded variable.
 659         (struct s390_options_t): New structure type.
 660         (options): New structure.
 661         (init_disasm): Rename from this...
 662         (disassemble_init_s390): ...to this.  Add initializations for
 663         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 664         (print_insn_s390): Delete call to init_disasm.
 665         (disassembler_options_s390): New function.
 666         (print_s390_disassembler_options): Print using information from
 667         struct 'options'.
 668         * po/opcodes.pot: Regenerate.
 669
 670 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-dis.c (PCMPESTR_Fixup): New.
 673         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 674         (prefix_table): Use PCMPESTR_Fixup.
 675         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 676         PCMPESTR_Fixup.
 677         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 678         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 679         Split 64-bit and non-64-bit variants.
 680         * opcodes/i386-tbl.h: Re-generate.
 681
 682 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 683
 684         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 685         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 686         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 687         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 688         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 689         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 690         (OP_SVE_V_HSD): New macros.
 691         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 692         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 693         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 694         (aarch64_opcode_table): Add new SVE instructions.
 695         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 696         for rotation operands.  Add new SVE operands.
 697         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 698         (ins_sve_quad_index): Likewise.
 699         (ins_imm_rotate): Split into...
 700         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 701         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 702         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 703         functions.
 704         (aarch64_ins_sve_addr_ri_s4): New function.
 705         (aarch64_ins_sve_quad_index): Likewise.
 706         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 707         * aarch64-asm-2.c: Regenerate.
 708         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 709         (ext_sve_quad_index): Likewise.
 710         (ext_imm_rotate): Split into...
 711         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 712         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 713         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 714         functions.
 715         (aarch64_ext_sve_addr_ri_s4): New function.
 716         (aarch64_ext_sve_quad_index): Likewise.
 717         (aarch64_ext_sve_index): Allow quad indices.
 718         (do_misc_decoding): Likewise.
 719         * aarch64-dis-2.c: Regenerate.
 720         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 721         aarch64_field_kinds.
 722         (OPD_F_OD_MASK): Widen by one bit.
 723         (OPD_F_NO_ZR): Bump accordingly.
 724         (get_operand_field_width): New function.
 725         * aarch64-opc.c (fields): Add new SVE fields.
 726         (operand_general_constraint_met_p): Handle new SVE operands.
 727         (aarch64_print_operand): Likewise.
 728         * aarch64-opc-2.c: Regenerate.
 729
 730 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 731
 732         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 733         (aarch64_feature_compnum): ...this.
 734         (SIMD_V8_3): Replace with...
 735         (COMPNUM): ...this.
 736         (CNUM_INSN): New macro.
 737         (aarch64_opcode_table): Use it for the complex number instructions.
 738
 739 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 742
 743 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 744
 745         Add support for associating SPARC ASIs with an architecture level.
 746         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 747         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 748         decoding of SPARC ASIs.
 749
 750 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 753         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 754
 755 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 756
 757         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 758         1 (instead of to itself). Correct typo.
 759
 760 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 761
 762         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 763         pseudoinstructions.
 764
 765 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 766
 767         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 768         (aarch64_sys_reg_supported_p): Handle them.
 769
 770 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 771
 772         * arc-opc.c (UIMM6_20R): Define.
 773         (SIMM12_20): Use above.
 774         (SIMM12_20R): Define.
 775         (SIMM3_5_S): Use above.
 776         (UIMM7_A32_11R_S): Define.
 777         (UIMM7_9_S): Use above.
 778         (UIMM3_13R_S): Define.
 779         (SIMM11_A32_7_S): Use above.
 780         (SIMM9_8R): Define.
 781         (UIMM10_A32_8_S): Use above.
 782         (UIMM8_8R_S): Define.
 783         (W6): Use above.
 784         (arc_relax_opcodes): Use all above defines.
 785
 786 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 787
 788         * arc-regs.h: Distinguish some of the registers different on
 789         ARC700 and HS38 cpus.
 790
 791 2017-02-14  Alan Modra  <amodra@gmail.com>
 792
 793         PR 21118
 794         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 795         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 796
 797 2017-02-11  Stafford Horne  <shorne@gmail.com>
 798             Alan Modra  <amodra@gmail.com>
 799
 800         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 801         Use insn_bytes_value and insn_int_value directly instead.  Don't
 802         free allocated memory until function exit.
 803
 804 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 805
 806         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 807
 808 2017-02-03  Nick Clifton  <nickc@redhat.com>
 809
 810         PR 21096
 811         * aarch64-opc.c (print_register_list): Ensure that the register
 812         list index will fir into the tb buffer.
 813         (print_register_offset_address): Likewise.
 814         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 815
 816 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 817
 818         PR 21056
 819         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 820         instructions when the previous fetch packet ends with a 32-bit
 821         instruction.
 822
 823 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 824
 825         * pru-opc.c: Remove vague reference to a future GDB port.
 826
 827 2017-01-20  Nick Clifton  <nickc@redhat.com>
 828
 829         * po/ga.po: Updated Irish translation.
 830
 831 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 832
 833         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 834
 835 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 836
 837         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 838         if FETCH_DATA returns 0.
 839         (m68k_scan_mask): Likewise.
 840         (print_insn_m68k): Update code to handle -1 return value.
 841
 842 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 843
 844         * m68k-dis.c (enum print_insn_arg_error): New.
 845         (NEXTBYTE): Replace -3 with
 846         PRINT_INSN_ARG_MEMORY_ERROR.
 847         (NEXTULONG): Likewise.
 848         (NEXTSINGLE): Likewise.
 849         (NEXTDOUBLE): Likewise.
 850         (NEXTDOUBLE): Likewise.
 851         (NEXTPACKED): Likewise.
 852         (FETCH_ARG): Likewise.
 853         (FETCH_DATA): Update comments.
 854         (print_insn_arg): Update comments. Replace magic numbers with
 855         enum.
 856         (match_insn_m68k): Likewise.
 857
 858 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 859
 860         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 861         * i386-dis-evex.h (evex_table): Updated.
 862         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 863         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 864         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 865         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 866         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 867         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 868         * i386-init.h: Regenerate.
 869         * i386-tbl.h: Ditto.
 870
 871 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 872
 873         * msp430-dis.c (msp430_singleoperand): Return -1 if
 874         msp430dis_opcode_signed returns false.
 875         (msp430_doubleoperand): Likewise.
 876         (msp430_branchinstr): Return -1 if
 877         msp430dis_opcode_unsigned returns false.
 878         (msp430x_calla_instr): Likewise.
 879         (print_insn_msp430): Likewise.
 880
 881 2017-01-05  Nick Clifton  <nickc@redhat.com>
 882
 883         PR 20946
 884         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 885         could not be matched.
 886         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 887         NULL.
 888
 889 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 890
 891         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 892         (aarch64_opcode_table): Use RCPC_INSN.
 893
 894 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 895
 896         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 897         extension.
 898         * riscv-opcodes/all-opcodes: Likewise.
 899
 900 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 901
 902         * riscv-dis.c (print_insn_args): Add fall through comment.
 903
 904 2017-01-03  Nick Clifton  <nickc@redhat.com>
 905
 906         * po/sr.po: New Serbian translation.
 907         * configure.ac (ALL_LINGUAS): Add sr.
 908         * configure: Regenerate.
 909
 910 2017-01-02  Alan Modra  <amodra@gmail.com>
 911
 912         * epiphany-desc.h: Regenerate.
 913         * epiphany-opc.h: Regenerate.
 914         * fr30-desc.h: Regenerate.
 915         * fr30-opc.h: Regenerate.
 916         * frv-desc.h: Regenerate.
 917         * frv-opc.h: Regenerate.
 918         * ip2k-desc.h: Regenerate.
 919         * ip2k-opc.h: Regenerate.
 920         * iq2000-desc.h: Regenerate.
 921         * iq2000-opc.h: Regenerate.
 922         * lm32-desc.h: Regenerate.
 923         * lm32-opc.h: Regenerate.
 924         * m32c-desc.h: Regenerate.
 925         * m32c-opc.h: Regenerate.
 926         * m32r-desc.h: Regenerate.
 927         * m32r-opc.h: Regenerate.
 928         * mep-desc.h: Regenerate.
 929         * mep-opc.h: Regenerate.
 930         * mt-desc.h: Regenerate.
 931         * mt-opc.h: Regenerate.
 932         * or1k-desc.h: Regenerate.
 933         * or1k-opc.h: Regenerate.
 934         * xc16x-desc.h: Regenerate.
 935         * xc16x-opc.h: Regenerate.
 936         * xstormy16-desc.h: Regenerate.
 937         * xstormy16-opc.h: Regenerate.
 938
 939 2017-01-02  Alan Modra  <amodra@gmail.com>
 940
 941         Update year range in copyright notice of all files.
 942
 943 For older changes see ChangeLog-2016
 944 \f
 945 Copyright (C) 2017 Free Software Foundation, Inc.
 946
 947 Copying and distribution of this file, with or without modification,
 948 are permitted in any medium without royalty provided the copyright
 949 notice and this notice are preserved.
 950
 951 Local Variables:
 952 mode: change-log
 953 left-margin: 8
 954 fill-column: 74
 955 version-control: never
 956 End: