opcodes/ChangeLog

   1 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (vex_len_table): Update rorxS.
   4
   5 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         AVX Programming Reference (June, 2011)
   8         * i386-dis.c (vex_len_table): Correct rorxS.
   9
  10         * i386-opc.tbl: Correct rorx.
  11         * i386-tbl.h: Regenerated.
  12
  13 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         * tilegx-opc.c (find_opcode): Replace "index" with "i".
  16         * tilepro-opc.c (find_opcode): Likewise.
  17
  18 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
  19
  20         * mips16-opc.c (jalrc, jrc): Move earlier in file.
  21
  22 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
  25         PREFIX_VEX_0F388E.
  26
  27 2011-06-17  Andreas Schwab  <schwab@redhat.com>
  28
  29         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
  30         (MOSTLYCLEANFILES): ... here.
  31         * Makefile.in: Regenerate.
  32
  33 2011-06-14  Alan Modra  <amodra@gmail.com>
  34
  35         * Makefile.in: Regenerate.
  36
  37 2011-06-13  Walter Lee  <walt@tilera.com>
  38
  39         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
  40         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
  41         * Makefile.in: Regenerate.
  42         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
  43         * configure: Regenerate.
  44         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
  45         * po/POTFILES.in: Regenerate.
  46         * tilegx-dis.c: New file.
  47         * tilegx-opc.c: New file.
  48         * tilepro-dis.c: New file.
  49         * tilepro-opc.c: New file.
  50
  51 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         AVX Programming Reference (June, 2011)
  54         * i386-dis.c (XMGatherQ): New.
  55         * i386-dis.c (EXxmm_mb): New.
  56         (EXxmm_mb): Likewise.
  57         (EXxmm_mw): Likewise.
  58         (EXxmm_md): Likewise.
  59         (EXxmm_mq): Likewise.
  60         (EXxmmdw): Likewise.
  61         (EXxmmqd): Likewise.
  62         (VexGatherQ): Likewise.
  63         (MVexVSIBDWpX): Likewise.
  64         (MVexVSIBQWpX): Likewise.
  65         (xmm_mb_mode): Likewise.
  66         (xmm_mw_mode): Likewise.
  67         (xmm_md_mode): Likewise.
  68         (xmm_mq_mode): Likewise.
  69         (xmmdw_mode): Likewise.
  70         (xmmqd_mode): Likewise.
  71         (ymmxmm_mode): Likewise.
  72         (vex_vsib_d_w_dq_mode): Likewise.
  73         (vex_vsib_q_w_dq_mode): Likewise.
  74         (MOD_VEX_0F385A_PREFIX_2): Likewise.
  75         (MOD_VEX_0F388C_PREFIX_2): Likewise.
  76         (MOD_VEX_0F388E_PREFIX_2): Likewise.
  77         (PREFIX_0F3882): Likewise.
  78         (PREFIX_VEX_0F3816): Likewise.
  79         (PREFIX_VEX_0F3836): Likewise.
  80         (PREFIX_VEX_0F3845): Likewise.
  81         (PREFIX_VEX_0F3846): Likewise.
  82         (PREFIX_VEX_0F3847): Likewise.
  83         (PREFIX_VEX_0F3858): Likewise.
  84         (PREFIX_VEX_0F3859): Likewise.
  85         (PREFIX_VEX_0F385A): Likewise.
  86         (PREFIX_VEX_0F3878): Likewise.
  87         (PREFIX_VEX_0F3879): Likewise.
  88         (PREFIX_VEX_0F388C): Likewise.
  89         (PREFIX_VEX_0F388E): Likewise.
  90         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
  91         (PREFIX_VEX_0F38F5): Likewise.
  92         (PREFIX_VEX_0F38F6): Likewise.
  93         (PREFIX_VEX_0F3A00): Likewise.
  94         (PREFIX_VEX_0F3A01): Likewise.
  95         (PREFIX_VEX_0F3A02): Likewise.
  96         (PREFIX_VEX_0F3A38): Likewise.
  97         (PREFIX_VEX_0F3A39): Likewise.
  98         (PREFIX_VEX_0F3A46): Likewise.
  99         (PREFIX_VEX_0F3AF0): Likewise.
 100         (VEX_LEN_0F3816_P_2): Likewise.
 101         (VEX_LEN_0F3819_P_2): Likewise.
 102         (VEX_LEN_0F3836_P_2): Likewise.
 103         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 104         (VEX_LEN_0F38F5_P_0): Likewise.
 105         (VEX_LEN_0F38F5_P_1): Likewise.
 106         (VEX_LEN_0F38F5_P_3): Likewise.
 107         (VEX_LEN_0F38F6_P_3): Likewise.
 108         (VEX_LEN_0F38F7_P_1): Likewise.
 109         (VEX_LEN_0F38F7_P_2): Likewise.
 110         (VEX_LEN_0F38F7_P_3): Likewise.
 111         (VEX_LEN_0F3A00_P_2): Likewise.
 112         (VEX_LEN_0F3A01_P_2): Likewise.
 113         (VEX_LEN_0F3A38_P_2): Likewise.
 114         (VEX_LEN_0F3A39_P_2): Likewise.
 115         (VEX_LEN_0F3A46_P_2): Likewise.
 116         (VEX_LEN_0F3AF0_P_3): Likewise.
 117         (VEX_W_0F3816_P_2): Likewise.
 118         (VEX_W_0F3818_P_2): Likewise.
 119         (VEX_W_0F3819_P_2): Likewise.
 120         (VEX_W_0F3836_P_2): Likewise.
 121         (VEX_W_0F3846_P_2): Likewise.
 122         (VEX_W_0F3858_P_2): Likewise.
 123         (VEX_W_0F3859_P_2): Likewise.
 124         (VEX_W_0F385A_P_2_M_0): Likewise.
 125         (VEX_W_0F3878_P_2): Likewise.
 126         (VEX_W_0F3879_P_2): Likewise.
 127         (VEX_W_0F3A00_P_2): Likewise.
 128         (VEX_W_0F3A01_P_2): Likewise.
 129         (VEX_W_0F3A02_P_2): Likewise.
 130         (VEX_W_0F3A38_P_2): Likewise.
 131         (VEX_W_0F3A39_P_2): Likewise.
 132         (VEX_W_0F3A46_P_2): Likewise.
 133         (MOD_VEX_0F3818_PREFIX_2): Removed.
 134         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 135         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 136         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 137         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 138         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 139         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 140         (VEX_LEN_0F3A0E_P_2): Likewise.
 141         (VEX_LEN_0F3A0F_P_2): Likewise.
 142         (VEX_LEN_0F3A42_P_2): Likewise.
 143         (VEX_LEN_0F3A4C_P_2): Likewise.
 144         (VEX_W_0F3818_P_2_M_0): Likewise.
 145         (VEX_W_0F3819_P_2_M_0): Likewise.
 146         (prefix_table): Updated.
 147         (three_byte_table): Likewise.
 148         (vex_table): Likewise.
 149         (vex_len_table): Likewise.
 150         (vex_w_table): Likewise.
 151         (mod_table): Likewise.
 152         (putop): Handle "LW".
 153         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 154         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 155         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 156         (OP_EX): Likewise.
 157         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 158         vex_vsib_q_w_dq_mode.
 159         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 160         (OP_VEX): Likewise.
 161
 162         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 163         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 164         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 165         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 166         (opcode_modifiers): Add VecSIB.
 167
 168         * i386-opc.h (CpuAVX2): New.
 169         (CpuBMI2): Likewise.
 170         (CpuLZCNT): Likewise.
 171         (CpuINVPCID): Likewise.
 172         (VecSIB128): Likewise.
 173         (VecSIB256): Likewise.
 174         (VecSIB): Likewise.
 175         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 176         (i386_opcode_modifier): Add vecsib.
 177
 178         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 179         * i386-init.h: Regenerated.
 180         * i386-tbl.h: Likewise.
 181
 182 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 183
 184         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 185         * i386-init.h: Regenerated.
 186
 187 2011-06-03  Nick Clifton  <nickc@redhat.com>
 188
 189         PR binutils/12752
 190         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 191         computing address offsets.
 192         (print_arm_address): Likewise.
 193         (print_insn_arm): Likewise.
 194         (print_insn_thumb16): Likewise.
 195         (print_insn_thumb32): Likewise.
 196
 197 2011-06-02  Jie Zhang <jie@codesourcery.com>
 198             Nathan Sidwell <nathan@codesourcery.com>
 199             Maciej Rozycki <macro@codesourcery.com>
 200
 201         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 202         as address offset.
 203         (print_arm_address): Likewise. Elide positive #0 appropriately.
 204         (print_insn_arm): Likewise.
 205
 206 2011-06-02  Nick Clifton  <nickc@redhat.com>
 207
 208         PR gas/12752
 209         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 210         passed to print_address_func.
 211
 212 2011-06-02  Nick Clifton  <nickc@redhat.com>
 213
 214         * arm-dis.c: Fix spelling mistakes.
 215         * op/opcodes.pot: Regenerate.
 216
 217 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 218
 219         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 220         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 221         * s390-opc.txt: Fix cxr instruction type.
 222
 223 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 224
 225         * s390-opc.c: Add new instruction types marking register pair
 226         operands.
 227         * s390-opc.txt: Match instructions having register pair operands
 228         to the new instruction types.
 229
 230 2011-05-19  Nick Clifton  <nickc@redhat.com>
 231
 232         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 233         operands.
 234
 235 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 236
 237         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 238         * i386-init.h: Regenerated.
 239
 240 2011-04-27  Nick Clifton  <nickc@redhat.com>
 241
 242         * po/da.po: Updated Danish translation.
 243
 244 2011-04-26  Anton Blanchard  <anton@samba.org>
 245
 246         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 247
 248 2011-04-21  DJ Delorie  <dj@redhat.com>
 249
 250         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 251         * rx-decode.c: Regenerate.
 252
 253 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-init.h: Regenerated.
 256
 257 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 258
 259         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 260         from bdver1 flags.
 261
 262 2011-04-13  Nick Clifton  <nickc@redhat.com>
 263
 264         * v850-dis.c (disassemble): Always print a closing square brace if
 265         an opening square brace was printed.
 266
 267 2011-04-12  Nick Clifton  <nickc@redhat.com>
 268
 269         PR binutils/12534
 270         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 271         patterns.
 272         (print_insn_thumb32): Handle %L.
 273
 274 2011-04-11  Julian Brown  <julian@codesourcery.com>
 275
 276         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 277         (print_insn_thumb32): Add APSR bitmask support.
 278
 279 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 280
 281         * arm-dis.c (print_insn): init vars moved into private_data structure.
 282
 283 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 284
 285         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 286
 287 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 288
 289         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 290         post-increment to support LPM Z+ instruction. Add support for 'E'
 291         constraint for DES instruction.
 292         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 293
 294 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 295
 296         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 297
 298 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 299
 300         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 301         Use branch types instead.
 302         (print_insn): Likewise.
 303
 304 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 305
 306         * mips-opc.c (mips_builtin_opcodes): Correct register use
 307         annotation of "alnv.ps".
 308
 309 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 310
 311         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 312
 313 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 314
 315         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 316
 317 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 318
 319         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 320
 321 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 322
 323         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 324         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 325         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 326         exception, end_of_registers, msize, memory, bfd_mach.
 327         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 328         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 329         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 330         (get_allreg): Change to new defines.  Fallback to abort().
 331
 332 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 333
 334         * bfin-dis.c: Add whitespace/parenthesis where needed.
 335
 336 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 337
 338         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 339         than 7.
 340
 341 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 342
 343         * configure: Regenerate.
 344
 345 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 346
 347         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 348
 349 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 350
 351         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 352         dregs only when P is set, and dregs_lo otherwise.
 353
 354 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 355
 356         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 357
 358 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 359
 360         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 361
 362 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 363
 364         * bfin-dis.c (machine_registers): Delete REG_GP.
 365         (reg_names): Delete "GP".
 366         (decode_allregs): Change REG_GP to REG_LASTREG.
 367
 368 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 371         M_IH, M_IU): Delete.
 372
 373 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 374
 375         * bfin-dis.c (reg_names): Add const.
 376         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 377         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 378         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 379         decode_counters, decode_allregs): Likewise.
 380
 381 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 382
 383         * i386-dis.c (OP_J): Parenthesize expression to prevent
 384         truncated addresses.
 385         (print_insn): Fix indentation off-by-one.
 386
 387 2011-02-01  Nick Clifton  <nickc@redhat.com>
 388
 389         * po/da.po: Updated Danish translation.
 390
 391 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 392
 393         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 394
 395 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * i386-dis.c (sIbT): New.
 398         (b_T_mode): Likewise.
 399         (dis386): Replace sIb with sIbT on "pushT".
 400         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 401         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 402
 403 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 404
 405         * i386-init.h: Regenerated.
 406         * i386-tbl.h: Regenerated
 407
 408 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 409
 410         * i386-dis.c (REG_XOP_TBM_01): New.
 411         (REG_XOP_TBM_02): New.
 412         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 413         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 414         entries, and add bextr instruction.
 415
 416         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 417         (cpu_flags): Add CpuTBM.
 418
 419         * i386-opc.h (CpuTBM) New.
 420         (i386_cpu_flags): Add bit cputbm.
 421
 422         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 423         blcs, blsfill, blsic, t1mskc, and tzmsk.
 424
 425 2011-01-12  DJ Delorie  <dj@redhat.com>
 426
 427         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 428
 429 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 430
 431         * mips-dis.c (print_insn_args): Adjust the value to print the real
 432         offset for "+c" argument.
 433
 434 2011-01-10  Nick Clifton  <nickc@redhat.com>
 435
 436         * po/da.po: Updated Danish translation.
 437
 438 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 439
 440         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 441
 442 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-dis.c (REG_VEX_38F3): New.
 445         (PREFIX_0FBC): Likewise.
 446         (PREFIX_VEX_38F2): Likewise.
 447         (PREFIX_VEX_38F3_REG_1): Likewise.
 448         (PREFIX_VEX_38F3_REG_2): Likewise.
 449         (PREFIX_VEX_38F3_REG_3): Likewise.
 450         (PREFIX_VEX_38F7): Likewise.
 451         (VEX_LEN_38F2_P_0): Likewise.
 452         (VEX_LEN_38F3_R_1_P_0): Likewise.
 453         (VEX_LEN_38F3_R_2_P_0): Likewise.
 454         (VEX_LEN_38F3_R_3_P_0): Likewise.
 455         (VEX_LEN_38F7_P_0): Likewise.
 456         (dis386_twobyte): Use PREFIX_0FBC.
 457         (reg_table): Add REG_VEX_38F3.
 458         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 459         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 460         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 461         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 462         PREFIX_VEX_38F7.
 463         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 464         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 465         VEX_LEN_38F7_P_0.
 466
 467         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 468         (cpu_flags): Add CpuBMI.
 469
 470         * i386-opc.h (CpuBMI): New.
 471         (i386_cpu_flags): Add cpubmi.
 472
 473         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 474         * i386-init.h: Regenerated.
 475         * i386-tbl.h: Likewise.
 476
 477 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 478
 479         * i386-dis.c (VexGdq): New.
 480         (OP_VEX): Handle dq_mode.
 481
 482 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 483
 484         * i386-gen.c (process_copyright): Update copyright to 2011.
 485
 486 For older changes see ChangeLog-2010
 487 \f
 488 Local Variables:
 489 mode: change-log
 490 left-margin: 8
 491 fill-column: 74
 492 version-control: never
 493 End: