opcodes/ChangeLog

   1 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
   2
   3         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
   4          to the address and set as symbol address for LDS/ STS immediate operands.
   5
   6 2016-06-07  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
   9         cpu for "vle" to e500.
  10         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
  11         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
  12         (PPCNONE): Delete, substitute throughout.
  13         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
  14         except for major opcode 4 and 31.
  15         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
  16
  17 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
  18
  19         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
  20         ARM_EXT_RAS in relevant entries.
  21
  22 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
  23
  24         PR binutils/20196
  25         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
  26         opcodes for E6500.
  27
  28 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         PR binutis/18386
  31         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
  32         (indir_v_mode): New.
  33         Add comments for '&'.
  34         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
  35         (putop): Handle '&'.
  36         (intel_operand_size): Handle indir_v_mode.
  37         (OP_E_register): Likewise.
  38         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
  39         64-bit indirect call/jmp for AMD64.
  40         * i386-tbl.h: Regenerated
  41
  42 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
  43
  44         * arc-dis.c (struct arc_operand_iterator): New structure.
  45         (find_format_from_table): All the old content from find_format,
  46         with some minor adjustments, and parameter renaming.
  47         (find_format_long_instructions): New function.
  48         (find_format): Rewritten.
  49         (arc_insn_length): Add LSB parameter.
  50         (extract_operand_value): New function.
  51         (operand_iterator_next): New function.
  52         (print_insn_arc): Use new functions to find opcode, and iterator
  53         over operands.
  54         * arc-opc.c (insert_nps_3bit_dst_short): New function.
  55         (extract_nps_3bit_dst_short): New function.
  56         (insert_nps_3bit_src2_short): New function.
  57         (extract_nps_3bit_src2_short): New function.
  58         (insert_nps_bitop1_size): New function.
  59         (extract_nps_bitop1_size): New function.
  60         (insert_nps_bitop2_size): New function.
  61         (extract_nps_bitop2_size): New function.
  62         (insert_nps_bitop_mod4_msb): New function.
  63         (extract_nps_bitop_mod4_msb): New function.
  64         (insert_nps_bitop_mod4_lsb): New function.
  65         (extract_nps_bitop_mod4_lsb): New function.
  66         (insert_nps_bitop_dst_pos3_pos4): New function.
  67         (extract_nps_bitop_dst_pos3_pos4): New function.
  68         (insert_nps_bitop_ins_ext): New function.
  69         (extract_nps_bitop_ins_ext): New function.
  70         (arc_operands): Add new operands.
  71         (arc_long_opcodes): New global array.
  72         (arc_num_long_opcodes): New global.
  73         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
  74
  75 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  76
  77         * nds32-asm.h: Add extern "C".
  78         * sh-opc.h: Likewise.
  79
  80 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
  81
  82         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
  83         0,b,limm to the rflt instruction.
  84
  85 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  86
  87         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
  88         constant.
  89
  90 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         PR gas/20145
  93         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
  94         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
  95         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
  96         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
  97         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
  98         * i386-init.h: Regenerated.
  99
 100 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         PR gas/20145
 103         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 104         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 105         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 106         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 107         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 108         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 109         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 110         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 111         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 112         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 113         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 114         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 115         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 116         CpuRegMask for AVX512.
 117         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 118         and CpuRegMask.
 119         (set_bitfield_from_cpu_flag_init): New function.
 120         (set_bitfield): Remove const on f.  Call
 121         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 122         * i386-opc.h (CpuRegMMX): New.
 123         (CpuRegXMM): Likewise.
 124         (CpuRegYMM): Likewise.
 125         (CpuRegZMM): Likewise.
 126         (CpuRegMask): Likewise.
 127         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 128         and cpuregmask.
 129         * i386-init.h: Regenerated.
 130         * i386-tbl.h: Likewise.
 131
 132 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 133
 134         PR gas/20154
 135         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 136         (opcode_modifiers): Add AMD64 and Intel64.
 137         (main): Properly verify CpuMax.
 138         * i386-opc.h (CpuAMD64): Removed.
 139         (CpuIntel64): Likewise.
 140         (CpuMax): Set to CpuNo64.
 141         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 142         (AMD64): New.
 143         (Intel64): Likewise.
 144         (i386_opcode_modifier): Add amd64 and intel64.
 145         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 146         on call and jmp.
 147         * i386-init.h: Regenerated.
 148         * i386-tbl.h: Likewise.
 149
 150 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 151
 152         PR gas/20154
 153         * i386-gen.c (main): Fail if CpuMax is incorrect.
 154         * i386-opc.h (CpuMax): Set to CpuIntel64.
 155         * i386-tbl.h: Regenerated.
 156
 157 2016-05-27  Nick Clifton  <nickc@redhat.com>
 158
 159         PR target/20150
 160         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 161         (msp430dis_opcode_unsigned): New function.
 162         (msp430dis_opcode_signed): New function.
 163         (msp430_singleoperand): Use the new opcode reading functions.
 164         Only disassenmble bytes if they were successfully read.
 165         (msp430_doubleoperand): Likewise.
 166         (msp430_branchinstr): Likewise.
 167         (msp430x_callx_instr): Likewise.
 168         (print_insn_msp430): Check that it is safe to read bytes before
 169         attempting disassembly.  Use the new opcode reading functions.
 170
 171 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 172
 173         * ppc-opc.c (CY): New define.  Document it.
 174         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 175
 176 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 177
 178         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 179         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 180         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 181         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 182         CPU_ANY_AVX_FLAGS.
 183         * i386-init.h: Regenerated.
 184
 185 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 186
 187         PR gas/20141
 188         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 189         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 190         * i386-init.h: Regenerated.
 191
 192 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 195         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 196         * i386-init.h: Regenerated.
 197
 198 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 199
 200         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 201         information.
 202         (print_insn_arc): Set insn_type information.
 203         * arc-opc.c (C_CC): Add F_CLASS_COND.
 204         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 205         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 206         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 207         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 208         (brne, brne_s, jeq_s, jne_s): Likewise.
 209
 210 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 211
 212         * arc-tbl.h (neg): New instruction variant.
 213
 214 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 215
 216         * arc-dis.c (find_format, find_format, get_auxreg)
 217         (print_insn_arc): Changed.
 218         * arc-ext.h (INSERT_XOP): Likewise.
 219
 220 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 221
 222         * tic54x-dis.c (sprint_mmr): Adjust.
 223         * tic54x-opc.c: Likewise.
 224
 225 2016-05-19  Alan Modra  <amodra@gmail.com>
 226
 227         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 228
 229 2016-05-19  Alan Modra  <amodra@gmail.com>
 230
 231         * ppc-opc.c: Formatting.
 232         (NSISIGNOPT): Define.
 233         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 234
 235 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 236
 237         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 238         replacing references to `micromips_ase' throughout.
 239         (_print_insn_mips): Don't use file-level microMIPS annotation to
 240         determine the disassembly mode with the symbol table.
 241
 242 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 243
 244         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 245
 246 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 247
 248         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 249         mips64r6.
 250         * mips-opc.c (D34): New macro.
 251         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 252
 253 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 254
 255         * i386-dis.c (prefix_table): Add RDPID instruction.
 256         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 257         (cpu_flags): Add RDPID bitfield.
 258         * i386-opc.h (enum): Add RDPID element.
 259         (i386_cpu_flags): Add RDPID field.
 260         * i386-opc.tbl: Add RDPID instruction.
 261         * i386-init.h: Regenerate.
 262         * i386-tbl.h: Regenerate.
 263
 264 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 265
 266         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 267         branch type of a symbol.
 268         (print_insn): Likewise.
 269
 270 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 271
 272         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 273         Mainline Security Extensions instructions.
 274         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 275         Extensions instructions.
 276         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 277         instructions.
 278         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 279         special registers.
 280
 281 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 282
 283         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 284
 285 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 286
 287         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 288         (arcExtMap_genOpcode): Likewise.
 289         * arc-opc.c (arg_32bit_rc): Define new variable.
 290         (arg_32bit_u6): Likewise.
 291         (arg_32bit_limm): Likewise.
 292
 293 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 294
 295         * aarch64-gen.c (VERIFIER): Define.
 296         * aarch64-opc.c (VERIFIER): Define.
 297         (verify_ldpsw): Use static linkage.
 298         * aarch64-opc.h (verify_ldpsw): Remove.
 299         * aarch64-tbl.h: Use VERIFIER for verifiers.
 300
 301 2016-04-28  Nick Clifton  <nickc@redhat.com>
 302
 303         PR target/19722
 304         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 305         * aarch64-opc.c (verify_ldpsw): New function.
 306         * aarch64-opc.h (verify_ldpsw): New prototype.
 307         * aarch64-tbl.h: Add initialiser for verifier field.
 308         (LDPSW): Set verifier to verify_ldpsw.
 309
 310 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 311
 312         PR binutils/19983
 313         PR binutils/19984
 314         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 315         smaller than address size.
 316
 317 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 318
 319         * alpha-dis.c: Regenerate.
 320         * crx-dis.c: Likewise.
 321         * disassemble.c: Likewise.
 322         * epiphany-opc.c: Likewise.
 323         * fr30-opc.c: Likewise.
 324         * frv-opc.c: Likewise.
 325         * ip2k-opc.c: Likewise.
 326         * iq2000-opc.c: Likewise.
 327         * lm32-opc.c: Likewise.
 328         * lm32-opinst.c: Likewise.
 329         * m32c-opc.c: Likewise.
 330         * m32r-opc.c: Likewise.
 331         * m32r-opinst.c: Likewise.
 332         * mep-opc.c: Likewise.
 333         * mt-opc.c: Likewise.
 334         * or1k-opc.c: Likewise.
 335         * or1k-opinst.c: Likewise.
 336         * tic80-opc.c: Likewise.
 337         * xc16x-opc.c: Likewise.
 338         * xstormy16-opc.c: Likewise.
 339
 340 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 341
 342         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 343         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 344         calcsd, and calcxd instructions.
 345         * arc-opc.c (insert_nps_bitop_size): Delete.
 346         (extract_nps_bitop_size): Delete.
 347         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 348         (extract_nps_qcmp_m3): Define.
 349         (extract_nps_qcmp_m2): Define.
 350         (extract_nps_qcmp_m1): Define.
 351         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 352         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 353         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 354         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 355         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 356         NPS_QCMP_M3.
 357
 358 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 359
 360         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 361
 362 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 363
 364         * Makefile.in: Regenerated with automake 1.11.6.
 365         * aclocal.m4: Likewise.
 366
 367 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 368
 369         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 370         instructions.
 371         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 372         (extract_nps_cmem_uimm16): New function.
 373         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 374
 375 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 376
 377         * arc-dis.c (arc_insn_length): New function.
 378         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 379         (find_format): Change insnLen parameter to unsigned.
 380
 381 2016-04-13  Nick Clifton  <nickc@redhat.com>
 382
 383         PR target/19937
 384         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 385         the LD.B and LD.BU instructions.
 386
 387 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 388
 389         * arc-dis.c (find_format): Check for extension flags.
 390         (print_flags): New function.
 391         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 392         .extAuxRegister.
 393         * arc-ext.c (arcExtMap_coreRegName): Use
 394         LAST_EXTENSION_CORE_REGISTER.
 395         (arcExtMap_coreReadWrite): Likewise.
 396         (dump_ARC_extmap): Update printing.
 397         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 398         (arc_aux_regs): Add cpu field.
 399         * arc-regs.h: Add cpu field, lower case name aux registers.
 400
 401 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 402
 403         * arc-tbl.h: Add rtsc, sleep with no arguments.
 404
 405 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 406
 407         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 408         Initialize.
 409         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 410         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 411         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 412         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 413         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 414         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 415         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 416         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 417         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 418         (arc_opcode arc_opcodes): Null terminate the array.
 419         (arc_num_opcodes): Remove.
 420         * arc-ext.h (INSERT_XOP): Define.
 421         (extInstruction_t): Likewise.
 422         (arcExtMap_instName): Delete.
 423         (arcExtMap_insn): New function.
 424         (arcExtMap_genOpcode): Likewise.
 425         * arc-ext.c (ExtInstruction): Remove.
 426         (create_map): Zero initialize instruction fields.
 427         (arcExtMap_instName): Remove.
 428         (arcExtMap_insn): New function.
 429         (dump_ARC_extmap): More info while debuging.
 430         (arcExtMap_genOpcode): New function.
 431         * arc-dis.c (find_format): New function.
 432         (print_insn_arc): Use find_format.
 433         (arc_get_disassembler): Enable dump_ARC_extmap only when
 434         debugging.
 435
 436 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 437
 438         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 439         instruction bits out.
 440
 441 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 442
 443         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 444         * arc-opc.c (arc_flag_operands): Add new flags.
 445         (arc_flag_classes): Add new classes.
 446
 447 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 448
 449         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 450
 451 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 452
 453         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 454         encode1, rflt, crc16, and crc32 instructions.
 455         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 456         (arc_flag_classes): Add C_NPS_R.
 457         (insert_nps_bitop_size_2b): New function.
 458         (extract_nps_bitop_size_2b): Likewise.
 459         (insert_nps_bitop_uimm8): Likewise.
 460         (extract_nps_bitop_uimm8): Likewise.
 461         (arc_operands): Add new operand entries.
 462
 463 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 464
 465         * arc-regs.h: Add a new subclass field.  Add double assist
 466         accumulator register values.
 467         * arc-tbl.h: Use DPA subclass to mark the double assist
 468         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 469         * arc-opc.c (RSP): Define instead of SP.
 470         (arc_aux_regs): Add the subclass field.
 471
 472 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 473
 474         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 475
 476 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 477
 478         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 479         NPS_R_SRC1.
 480
 481 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 482
 483         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 484         issues.  No functional changes.
 485
 486 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 487
 488         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 489         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 490         (RTT): Remove duplicate.
 491         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 492         (PCT_CONFIG*): Remove.
 493         (D1L, D1H, D2H, D2L): Define.
 494
 495 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 496
 497         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 498
 499 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 500
 501         * arc-tbl.h (invld07): Remove.
 502         * arc-ext-tbl.h: New file.
 503         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 504         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 505
 506 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 507
 508         Fix -Wstack-usage warnings.
 509         * aarch64-dis.c (print_operands): Substitute size.
 510         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 511
 512 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 513
 514         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 515         to get a proper diagnostic when an invalid ASR register is used.
 516
 517 2016-03-22  Nick Clifton  <nickc@redhat.com>
 518
 519         * configure: Regenerate.
 520
 521 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 522
 523         * arc-nps400-tbl.h: New file.
 524         * arc-opc.c: Add top level comment.
 525         (insert_nps_3bit_dst): New function.
 526         (extract_nps_3bit_dst): New function.
 527         (insert_nps_3bit_src2): New function.
 528         (extract_nps_3bit_src2): New function.
 529         (insert_nps_bitop_size): New function.
 530         (extract_nps_bitop_size): New function.
 531         (arc_flag_operands): Add nps400 entries.
 532         (arc_flag_classes): Add nps400 entries.
 533         (arc_operands): Add nps400 entries.
 534         (arc_opcodes): Add nps400 include.
 535
 536 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 537
 538         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 539         the new class enum values.
 540
 541 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 542
 543         * arc-dis.c (print_insn_arc): Handle nps400.
 544
 545 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 546
 547         * arc-opc.c (BASE): Delete.
 548
 549 2016-03-18  Nick Clifton  <nickc@redhat.com>
 550
 551         PR target/19721
 552         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 553         of MOV insn that aliases an ORR insn.
 554
 555 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 556
 557         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 558
 559 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 560
 561         * mcore-opc.h: Add const qualifiers.
 562         * microblaze-opc.h (struct op_code_struct): Likewise.
 563         * sh-opc.h: Likewise.
 564         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 565         (tic4x_print_op): Likewise.
 566
 567 2016-03-02  Alan Modra  <amodra@gmail.com>
 568
 569         * or1k-desc.h: Regenerate.
 570         * fr30-ibld.c: Regenerate.
 571         * rl78-decode.c: Regenerate.
 572
 573 2016-03-01  Nick Clifton  <nickc@redhat.com>
 574
 575         PR target/19747
 576         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 577
 578 2016-02-24  Renlin Li  <renlin.li@arm.com>
 579
 580         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 581         (print_insn_coprocessor): Support fp16 instructions.
 582
 583 2016-02-24  Renlin Li  <renlin.li@arm.com>
 584
 585         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 586         vminnm, vrint(mpna).
 587
 588 2016-02-24  Renlin Li  <renlin.li@arm.com>
 589
 590         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 591         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 592
 593 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * i386-dis.c (print_insn): Parenthesize expression to prevent
 596         truncated addresses.
 597         (OP_J): Likewise.
 598
 599 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 600             Janek van Oirschot  <jvanoirs@synopsys.com>
 601
 602         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 603         variable.
 604
 605 2016-02-04  Nick Clifton  <nickc@redhat.com>
 606
 607         PR target/19561
 608         * msp430-dis.c (print_insn_msp430): Add a special case for
 609         decoding an RRC instruction with the ZC bit set in the extension
 610         word.
 611
 612 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 613
 614         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 615         * epiphany-ibld.c: Regenerate.
 616         * fr30-ibld.c: Regenerate.
 617         * frv-ibld.c: Regenerate.
 618         * ip2k-ibld.c: Regenerate.
 619         * iq2000-ibld.c: Regenerate.
 620         * lm32-ibld.c: Regenerate.
 621         * m32c-ibld.c: Regenerate.
 622         * m32r-ibld.c: Regenerate.
 623         * mep-ibld.c: Regenerate.
 624         * mt-ibld.c: Regenerate.
 625         * or1k-ibld.c: Regenerate.
 626         * xc16x-ibld.c: Regenerate.
 627         * xstormy16-ibld.c: Regenerate.
 628
 629 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 630
 631         * epiphany-dis.c: Regenerated from latest cpu files.
 632
 633 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 634
 635         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 636         test bit.
 637
 638 2016-01-25  Renlin Li  <renlin.li@arm.com>
 639
 640         * arm-dis.c (mapping_symbol_for_insn): New function.
 641         (find_ifthen_state): Call mapping_symbol_for_insn().
 642
 643 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 644
 645         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 646         of MSR UAO immediate operand.
 647
 648 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 649
 650         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 651         instruction support.
 652
 653 2016-01-17  Alan Modra  <amodra@gmail.com>
 654
 655         * configure: Regenerate.
 656
 657 2016-01-14  Nick Clifton  <nickc@redhat.com>
 658
 659         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 660         instructions that can support stack pointer operations.
 661         * rl78-decode.c: Regenerate.
 662         * rl78-dis.c: Fix display of stack pointer in MOVW based
 663         instructions.
 664
 665 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 666
 667         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 668         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 669         erxtatus_el1 and erxaddr_el1.
 670
 671 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 672
 673         * arm-dis.c (arm_opcodes): Add "esb".
 674         (thumb_opcodes): Likewise.
 675
 676 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 677
 678         * ppc-opc.c <xscmpnedp>: Delete.
 679         <xvcmpnedp>: Likewise.
 680         <xvcmpnedp.>: Likewise.
 681         <xvcmpnesp>: Likewise.
 682         <xvcmpnesp.>: Likewise.
 683
 684 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 685
 686         PR gas/13050
 687         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 688         addition to ISA_A.
 689
 690 2016-01-01  Alan Modra  <amodra@gmail.com>
 691
 692         Update year range in copyright notice of all files.
 693
 694 For older changes see ChangeLog-2015
 695 \f
 696 Copyright (C) 2016 Free Software Foundation, Inc.
 697
 698 Copying and distribution of this file, with or without modification,
 699 are permitted in any medium without royalty provided the copyright
 700 notice and this notice are preserved.
 701
 702 Local Variables:
 703 mode: change-log
 704 left-margin: 8
 705 fill-column: 74
 706 version-control: never
 707 End: