opcodes/ChangeLog

   1 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
   4         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
   5         feature test.
   6
   7 2015-11-23  Tristan Gingold  <gingold@adacore.com>
   8
   9         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
  10
  11 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
  12
  13         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
  14         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
  15         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
  16         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
  17         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
  18         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
  19         cnthv_ctl_el2, cnthv_cval_el2.
  20         (aarch64_sys_reg_supported_p): Update for the new system
  21         registers.
  22
  23 2015-11-20  Nick Clifton  <nickc@redhat.com>
  24
  25         PR binutils/19224
  26         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
  27
  28 2015-11-20  Nick Clifton  <nickc@redhat.com>
  29
  30         * po/zh_CN.po: Updated simplified Chinese translation.
  31
  32 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
  33
  34         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
  35         of MSR PAN immediate operand.
  36
  37 2015-11-16  Nick Clifton  <nickc@redhat.com>
  38
  39         * rx-dis.c (condition_names): Replace always and never with
  40         invalid, since the always/never conditions can never be legal.
  41
  42 2015-11-13  Tristan Gingold  <gingold@adacore.com>
  43
  44         * configure: Regenerate.
  45
  46 2015-11-11  Alan Modra  <amodra@gmail.com>
  47             Peter Bergner <bergner@vnet.ibm.com>
  48
  49         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
  50         Add PPC_OPCODE_VSX3 to the vsx entry.
  51         (powerpc_init_dialect): Set default dialect to power9.
  52         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
  53         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
  54         extract_l1 insert_xtq6, extract_xtq6): New static functions.
  55         (insert_esync): Test for illegal L operand value.
  56         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
  57         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
  58         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
  59         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
  60         PPCVSX3): New defines.
  61         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
  62         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
  63         <mcrxr>: Use XBFRARB_MASK.
  64         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
  65         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
  66         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
  67         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
  68         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
  69         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
  70         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
  71         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
  72         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
  73         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
  74         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
  75         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
  76         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
  77         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
  78         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
  79         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
  80         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
  81         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
  82         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
  83         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
  84         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
  85         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
  86         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
  87         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
  88         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
  89         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
  90         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
  91         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
  92         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
  93         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
  94         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
  95         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
  96
  97 2015-11-02  Nick Clifton  <nickc@redhat.com>
  98
  99         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 100         instructions.
 101         * rx-decode.c: Regenerate.
 102
 103 2015-11-02  Nick Clifton  <nickc@redhat.com>
 104
 105         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 106         type to RX_Operand_Zero_Indirect.
 107         * rx-decode.c: Regenerate.
 108         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 109
 110 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 111
 112         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 113         noaliases_p.  Update comments.  Pass noaliases_p rather than
 114         no_aliases to aarch64_opcode_decode.
 115         (print_insn_aarch64_word): Pass no_aliases to
 116         aarch64_decode_insn.
 117
 118 2015-10-27  Vinay  <Vinay.G@kpit.com>
 119
 120         PR binutils/19159
 121         * rl78-decode.opc (MOV): Added offset to DE register in index
 122         addressing mode.
 123         * rl78-decode.c: Regenerate.
 124
 125 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 126
 127         PR binutils/19158
 128         * rl78-decode.opc: Add 's' print operator to instructions that
 129         access system registers.
 130         * rl78-decode.c: Regenerate.
 131         * rl78-dis.c (print_insn_rl78_common): Decode all system
 132         registers.
 133
 134 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 135
 136         PR binutils/19157
 137         * rl78-decode.opc: Add 'a' print operator to mov instructions
 138         using stack pointer plus index addressing.
 139         * rl78-decode.c: Regenerate.
 140
 141 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 142
 143         * s390-opc.c: Fix comment.
 144         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 145         trtt to RRF_U0RER since the second parameter does not need to be a
 146         register pair.
 147
 148 2015-10-08  Nick Clifton  <nickc@redhat.com>
 149
 150         * arc-dis.c (print_insn_arc): Initiallise insn array.
 151
 152 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 153
 154         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 155         'name' rather than 'template'.
 156         * aarch64-opc.c (aarch64_print_operand): Likewise.
 157
 158 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 159
 160         * arc-dis.c: Revamped file for ARC support
 161         * arc-dis.h: Likewise.
 162         * arc-ext.c: Likewise.
 163         * arc-ext.h: Likewise.
 164         * arc-opc.c: Likewise.
 165         * arc-fxi.h: New file.
 166         * arc-regs.h: Likewise.
 167         * arc-tbl.h: Likewise.
 168
 169 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 170
 171         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 172         argument insn type to aarch64_insn.  Rename to ...
 173         (aarch64_decode_insn): ... it.
 174         (print_insn_aarch64_word): Caller updated.
 175
 176 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 177
 178         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 179         (print_insn_aarch64_word): Caller updated.
 180
 181 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 182
 183         * s390-mkopc.c (main): Parse htm and vx flag.
 184         * s390-opc.txt: Mark instructions from the hardware transactional
 185         memory and vector facilities with the "htm"/"vx" flag.
 186
 187 2015-09-28  Nick Clifton  <nickc@redhat.com>
 188
 189         * po/de.po: Updated German translation.
 190
 191 2015-09-28  Tom Rix  <tom@bumblecow.com>
 192
 193         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 194
 195 2015-09-23  Nick Clifton  <nickc@redhat.com>
 196
 197         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 198         function.
 199         * tic30-dis.c (print_branch): Likewise.
 200         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 201         value before left shifting.
 202         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 203         * hppa-dis.c (print_insn_hppa): Likewise.
 204         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 205         array.
 206         * msp430-dis.c (msp430_singleoperand): Likewise.
 207         (msp430_doubleoperand): Likewise.
 208         (print_insn_msp430): Likewise.
 209         * nds32-asm.c (parse_operand): Likewise.
 210         * sh-opc.h (MASK): Likewise.
 211         * v850-dis.c (get_operand_value): Likewise.
 212
 213 2015-09-22  Nick Clifton  <nickc@redhat.com>
 214
 215         * rx-decode.opc (bwl): Use RX_Bad_Size.
 216         (sbwl): Likewise.
 217         (ubwl): Likewise.  Rename to ubw.
 218         (uBWL): Rename to uBW.
 219         Replace all references to uBWL with uBW.
 220         * rx-decode.c: Regenerate.
 221         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 222         (opsize_names): Likewise.
 223         (print_insn_rx): Detect and report RX_Bad_Size.
 224
 225 2015-09-22  Anton Blanchard  <anton@samba.org>
 226
 227         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 228
 229 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 230
 231         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 232         %pmcdper.
 233
 234 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 235
 236         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 237
 238 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 239
 240         PR binutils/18257
 241         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 242         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 243         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 244         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 245         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 246         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 247         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 248         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 249         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 250         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 251         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 252         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 253         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 254         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 255         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 256         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 257         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 258         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 259         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 260         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 261         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 262         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 263         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 264         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 265         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 266         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 267         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 268         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 269         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 270         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 271         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 272         (vex_w_table): Replace terminals with MOD_TABLE entries for
 273         most of mask instructions.
 274
 275 2015-08-17  Alan Modra  <amodra@gmail.com>
 276
 277         * cgen.sh: Trim trailing space from cgen output.
 278         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 279         (print_dis_table): Likewise.
 280         * opc2c.c (dump_lines): Likewise.
 281         (orig_filename): Warning fix.
 282         * ia64-asmtab.c: Regenerate.
 283
 284 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 285
 286         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 287         and higher with ARM instruction set will now mark the 26-bit
 288         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 289         (arm_opcodes): Fix for unpredictable nop being recognized as a
 290         teq.
 291
 292 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 293
 294         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 295         based on 'or' is first.
 296         * mips-opc.c (mips_builtin_opcodes): Ditto.
 297
 298 2015-08-11  Nick Clifton  <nickc@redhat.com>
 299
 300         PR 18800
 301         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 302         instruction.
 303
 304 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 305
 306         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 307
 308 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 309
 310         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 311         * i386-init.h: Regenerated.
 312
 313 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         PR binutils/13571
 316         * i386-dis.c (MOD_0FC3): New.
 317         (PREFIX_0FC3): Renamed to ...
 318         (PREFIX_MOD_0_0FC3): This.
 319         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 320         (prefix_table): Replace Ma with Ev on movntiS.
 321         (mod_table): Add MOD_0FC3.
 322
 323 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         * configure: Regenerated.
 326
 327 2015-07-23  Alan Modra  <amodra@gmail.com>
 328
 329         PR 18708
 330         * i386-dis.c (get64): Avoid signed integer overflow.
 331
 332 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 333
 334         PR binutils/18631
 335         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 336         "EXEvexHalfBcstXmmq" for the second operand.
 337         (EVEX_W_0F79_P_2): Likewise.
 338         (EVEX_W_0F7A_P_2): Likewise.
 339         (EVEX_W_0F7B_P_2): Likewise.
 340
 341 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 342
 343         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 344         float bitfield format.
 345         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 346         quarter float bitfield format.
 347
 348 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 349
 350         * configure: Regenerated.
 351
 352 2015-07-03  Alan Modra  <amodra@gmail.com>
 353
 354         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 355         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 356         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 357
 358 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 359             Cesar Philippidis  <cesar@codesourcery.com>
 360
 361         * nios2-dis.c (nios2_extract_opcode): New.
 362         (nios2_disassembler_state): New.
 363         (nios2_find_opcode_hash): Use mach parameter to select correct
 364         disassembler state.
 365         (nios2_print_insn_arg): Extend to support new R2 argument letters
 366         and formats.
 367         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 368         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 369         (NIOS2_NUM_OPCODES): Rename to...
 370         (NIOS2_NUM_R1_OPCODES): This.
 371         (nios2_r2_opcodes): New.
 372         (NIOS2_NUM_R2_OPCODES): New.
 373         (nios2_num_r2_opcodes): New.
 374         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 375         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 376         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 377         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 378         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 379
 380 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 381
 382         * i386-dis.c (OP_Mwaitx): New.
 383         (rm_table): Add monitorx/mwaitx.
 384         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 385         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 386         (operand_type_init): Add CpuMWAITX.
 387         * i386-opc.h (CpuMWAITX): New.
 388         (i386_cpu_flags): Add cpumwaitx.
 389         * i386-opc.tbl: Add monitorx and mwaitx.
 390         * i386-init.h: Regenerated.
 391         * i386-tbl.h: Likewise.
 392
 393 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 394
 395         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 396         (insert_esync): New function.
 397         (LS, WC): Use insert_ls.
 398         (ESYNC): Use insert_esync.
 399
 400 2015-06-22  Nick Clifton  <nickc@redhat.com>
 401
 402         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 403         requested region lies beyond it.
 404         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 405         looking for 32-bit insns.
 406         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 407         data.
 408         * sh-dis.c (print_insn_sh): Likewise.
 409         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 410         blocks of instructions.
 411         * vax-dis.c (print_insn_vax): Check that the requested address
 412         does not clash with the stop_vma.
 413
 414 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 415
 416         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 417         * ppc-opc.c (FXM4): Add non-zero optional value.
 418         (TBR): Likewise.
 419         (SXL): Likewise.
 420         (insert_fxm): Handle new default operand value.
 421         (extract_fxm): Likewise.
 422         (insert_tbr): Likewise.
 423         (extract_tbr): Likewise.
 424
 425 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 426
 427         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 428
 429 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 430
 431         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 432
 433 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 434
 435         * ppc-opc.c: Add comment accidentally removed by old commit.
 436         (MTMSRD_L): Delete.
 437
 438 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 439
 440         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 441
 442 2015-06-04  Nick Clifton  <nickc@redhat.com>
 443
 444         PR 18474
 445         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 446
 447 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 448
 449         * arm-dis.c (arm_opcodes): Add "setpan".
 450         (thumb_opcodes): Add "setpan".
 451
 452 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 453
 454         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 455         macros.
 456
 457 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 458
 459         * aarch64-tbl.h (aarch64_feature_rdma): New.
 460         (RDMA): New.
 461         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 462         * aarch64-asm-2.c: Regenerate.
 463         * aarch64-dis-2.c: Regenerate.
 464         * aarch64-opc-2.c: Regenerate.
 465
 466 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 467
 468         * aarch64-tbl.h (aarch64_feature_lor): New.
 469         (LOR): New.
 470         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 471         "stllrb", "stllrh".
 472         * aarch64-asm-2.c: Regenerate.
 473         * aarch64-dis-2.c: Regenerate.
 474         * aarch64-opc-2.c: Regenerate.
 475
 476 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 477
 478         * aarch64-opc.c (F_ARCHEXT): New.
 479         (aarch64_sys_regs): Add "pan".
 480         (aarch64_sys_reg_supported_p): New.
 481         (aarch64_pstatefields): Add "pan".
 482         (aarch64_pstatefield_supported_p): New.
 483
 484 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-tbl.h: Regenerate.
 487
 488 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-dis.c (print_insn): Swap rounding mode specifier and
 491         general purpose register in Intel mode.
 492
 493 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 496         * i386-tbl.h: Regenerate.
 497
 498 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 501         * i386-init.h: Regenerated.
 502
 503 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         PR binutis/18386
 506         * i386-dis.c: Add comments for '@'.
 507         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 508         (enum x86_64_isa): New.
 509         (isa64): Likewise.
 510         (print_i386_disassembler_options): Add amd64 and intel64.
 511         (print_insn): Handle amd64 and intel64.
 512         (putop): Handle '@'.
 513         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 514         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 515         * i386-opc.h (AMD64): New.
 516         (CpuIntel64): Likewise.
 517         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 518         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 519         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 520         * i386-init.h: Regenerated.
 521         * i386-tbl.h: Likewise.
 522
 523 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 524
 525         * ppc-opc.c (IH) New define.
 526         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 527         <tlbie>: Add RS operand for POWER7.
 528         <slbia>: Add IH operand for POWER6.
 529
 530 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 533         direct branch.
 534         (jmp): Likewise.
 535         * i386-tbl.h: Regenerated.
 536
 537 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 538
 539         * configure.ac: Support bfd_iamcu_arch.
 540         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 541         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 542         CPU_IAMCU_COMPAT_FLAGS.
 543         (cpu_flags): Add CpuIAMCU.
 544         * i386-opc.h (CpuIAMCU): New.
 545         (i386_cpu_flags): Add cpuiamcu.
 546         * configure: Regenerated.
 547         * i386-init.h: Likewise.
 548         * i386-tbl.h: Likewise.
 549
 550 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 551
 552         PR binutis/18386
 553         * i386-dis.c (X86_64_E8): New.
 554         (X86_64_E9): Likewise.
 555         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 556         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 557         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 558         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 559         (putop): Handle '^'.
 560         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 561         REX_W.
 562
 563 2015-04-30  DJ Delorie  <dj@redhat.com>
 564
 565         * disassemble.c (disassembler): Choose suitable disassembler based
 566         on E_ABI.
 567         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 568         it to decode mul/div insns.
 569         * rl78-decode.c: Regenerate.
 570         * rl78-dis.c (print_insn_rl78): Rename to...
 571         (print_insn_rl78_common): ...this, take ISA parameter.
 572         (print_insn_rl78): New.
 573         (print_insn_rl78_g10): New.
 574         (print_insn_rl78_g13): New.
 575         (print_insn_rl78_g14): New.
 576         (rl78_get_disassembler): New.
 577
 578 2015-04-29  Nick Clifton  <nickc@redhat.com>
 579
 580         * po/fr.po: Updated French translation.
 581
 582 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 583
 584         * ppc-opc.c (DCBT_EO): New define.
 585         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 586         <lharx>: Likewise.
 587         <stbcx.>: Likewise.
 588         <sthcx.>: Likewise.
 589         <waitrsv>: Do not enable for POWER7 and later.
 590         <waitimpl>: Likewise.
 591         <dcbt>: Default to the two operand form of the instruction for all
 592         "old" cpus.  For "new" cpus, use the operand ordering that matches
 593         whether the cpu is server or embedded.
 594         <dcbtst>: Likewise.
 595
 596 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 597
 598         * s390-opc.c: New instruction type VV0UU2.
 599         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 600         and WFC.
 601
 602 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 605         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 606         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 607         (vfpclasspd, vfpclassps): Add %XZ.
 608
 609 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 610
 611         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 612         (PREFIX_UD_REPZ): Likewise.
 613         (PREFIX_UD_REPNZ): Likewise.
 614         (PREFIX_UD_DATA): Likewise.
 615         (PREFIX_UD_ADDR): Likewise.
 616         (PREFIX_UD_LOCK): Likewise.
 617
 618 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * i386-dis.c (prefix_requirement): Removed.
 621         (print_insn): Don't set prefix_requirement.  Check
 622         dp->prefix_requirement instead of prefix_requirement.
 623
 624 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 625
 626         PR binutils/17898
 627         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 628         (PREFIX_MOD_0_0FC7_REG_6): This.
 629         (PREFIX_MOD_3_0FC7_REG_6): New.
 630         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 631         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 632         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 633         PREFIX_MOD_3_0FC7_REG_7.
 634         (mod_table): Replace PREFIX_0FC7_REG_6 with
 635         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 636         PREFIX_MOD_3_0FC7_REG_7.
 637
 638 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 641         (PREFIX_MANDATORY_REPNZ): Likewise.
 642         (PREFIX_MANDATORY_DATA): Likewise.
 643         (PREFIX_MANDATORY_ADDR): Likewise.
 644         (PREFIX_MANDATORY_LOCK): Likewise.
 645         (PREFIX_MANDATORY): Likewise.
 646         (PREFIX_UD_SHIFT): Set to 8
 647         (PREFIX_UD_REPZ): Updated.
 648         (PREFIX_UD_REPNZ): Likewise.
 649         (PREFIX_UD_DATA): Likewise.
 650         (PREFIX_UD_ADDR): Likewise.
 651         (PREFIX_UD_LOCK): Likewise.
 652         (PREFIX_IGNORED_SHIFT): New.
 653         (PREFIX_IGNORED_REPZ): Likewise.
 654         (PREFIX_IGNORED_REPNZ): Likewise.
 655         (PREFIX_IGNORED_DATA): Likewise.
 656         (PREFIX_IGNORED_ADDR): Likewise.
 657         (PREFIX_IGNORED_LOCK): Likewise.
 658         (PREFIX_OPCODE): Likewise.
 659         (PREFIX_IGNORED): Likewise.
 660         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 661         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 662         (three_byte_table): Likewise.
 663         (mod_table): Likewise.
 664         (mandatory_prefix): Renamed to ...
 665         (prefix_requirement): This.
 666         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 667         Update PREFIX_90 entry.
 668         (get_valid_dis386): Check prefix_requirement to see if a prefix
 669         should be ignored.
 670         (print_insn): Replace mandatory_prefix with prefix_requirement.
 671
 672 2015-04-15  Renlin Li  <renlin.li@arm.com>
 673
 674         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 675         use it for ssat and ssat16.
 676         (print_insn_thumb32): Add handle case for 'D' control code.
 677
 678 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 679             H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 682         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 683         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 684         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 685         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 686         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 687         Fill prefix_requirement field.
 688         (struct dis386): Add prefix_requirement field.
 689         (dis386): Fill prefix_requirement field.
 690         (dis386_twobyte): Ditto.
 691         (twobyte_has_mandatory_prefix_: Remove.
 692         (reg_table): Fill prefix_requirement field.
 693         (prefix_table): Ditto.
 694         (x86_64_table): Ditto.
 695         (three_byte_table): Ditto.
 696         (xop_table): Ditto.
 697         (vex_table): Ditto.
 698         (vex_len_table): Ditto.
 699         (vex_w_table): Ditto.
 700         (mod_table): Ditto.
 701         (bad_opcode): Ditto.
 702         (print_insn): Use prefix_requirement.
 703         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 704         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 705         (float_reg): Ditto.
 706
 707 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 708
 709         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 710
 711 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 712
 713         * Makefile.in: Regenerated.
 714
 715 2015-03-25  Anton Blanchard  <anton@samba.org>
 716
 717         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 718         powerpc_opcd_indices and vle_opcd_indices once.
 719
 720 2015-03-25  Anton Blanchard  <anton@samba.org>
 721
 722         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 723
 724 2015-03-24  Terry Guo  <terry.guo@arm.com>
 725
 726         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 727         (opcode16): Likewise.
 728         (coprocessor_opcodes): Replace bit with feature struct.
 729         (neon_opcodes): Likewise.
 730         (arm_opcodes): Likewise.
 731         (thumb_opcodes): Likewise.
 732         (thumb32_opcodes): Likewise.
 733         (print_insn_coprocessor): Likewise.
 734         (print_insn_arm): Likewise.
 735         (select_arm_features): Follow new feature struct.
 736
 737 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 738
 739         * i386-dis.c (rm_table): Add clzero.
 740         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 741         Add CPU_CLZERO_FLAGS.
 742         (cpu_flags): Add CpuCLZERO.
 743         * i386-opc.h: Add CpuCLZERO.
 744         * i386-opc.tbl: Add clzero.
 745         * i386-init.h: Re-generated.
 746         * i386-tbl.h: Re-generated.
 747
 748 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 749
 750         * mips-opc.c (decode_mips_operand): Fix constraint issues
 751         with u and y operands.
 752
 753 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 754
 755         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 756
 757 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 758
 759         * s390-opc.c: Add new IBM z13 instructions.
 760         * s390-opc.txt: Likewise.
 761
 762 2015-03-10  Renlin Li  <renlin.li@arm.com>
 763
 764         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 765         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 766         related alias.
 767         * aarch64-asm-2.c: Regenerate.
 768         * aarch64-dis-2.c: Likewise.
 769         * aarch64-opc-2.c: Likewise.
 770
 771 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 772
 773         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 774
 775 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 776
 777         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 778         arch_sh_up.
 779         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 780         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 781
 782 2015-02-23  Vinay  <Vinay.G@kpit.com>
 783
 784         * rl78-decode.opc (MOV): Added space between two operands for
 785         'mov' instruction in index addressing mode.
 786         * rl78-decode.c: Regenerate.
 787
 788 2015-02-19  Pedro Alves  <palves@redhat.com>
 789
 790         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 791
 792 2015-02-10  Pedro Alves  <palves@redhat.com>
 793             Tom Tromey  <tromey@redhat.com>
 794
 795         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 796         microblaze_and, microblaze_xor.
 797         * microblaze-opc.h (opcodes): Adjust.
 798
 799 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 800
 801         * Makefile.am: Add FT32 files.
 802         * configure.ac: Handle FT32.
 803         * disassemble.c (disassembler): Call print_insn_ft32.
 804         * ft32-dis.c: New file.
 805         * ft32-opc.c: New file.
 806         * Makefile.in: Regenerate.
 807         * configure: Regenerate.
 808         * po/POTFILES.in: Regenerate.
 809
 810 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 811
 812         * nds32-asm.c (keyword_sr): Add new system registers.
 813
 814 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 815
 816         * s390-dis.c (s390_extract_operand): Support vector register
 817         operands.
 818         (s390_print_insn_with_opcode): Support new operands types and add
 819         new handling of optional operands.
 820         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 821         and include opcode/s390.h instead.
 822         (struct op_struct): New field `flags'.
 823         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 824         (dumpTable): Dump flags.
 825         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 826         string.
 827         * s390-opc.c: Add new operands types, instruction formats, and
 828         instruction masks.
 829         (s390_opformats): Add new formats for .insn.
 830         * s390-opc.txt: Add new instructions.
 831
 832 2015-01-01  Alan Modra  <amodra@gmail.com>
 833
 834         Update year range in copyright notice of all files.
 835
 836 For older changes see ChangeLog-2014
 837 \f
 838 Copyright (C) 2015 Free Software Foundation, Inc.
 839
 840 Copying and distribution of this file, with or without modification,
 841 are permitted in any medium without royalty provided the copyright
 842 notice and this notice are preserved.
 843
 844 Local Variables:
 845 mode: change-log
 846 left-margin: 8
 847 fill-column: 74
 848 version-control: never
 849 End: