opcodes/ChangeLog

   1 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
   2
   3         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
   4         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
   5         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
   6         (QL_STLW, QL_STLX): New.
   7
   8 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
   9
  10         * aarch64-asm.h (ins_addr_offset): New.
  11         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
  12         (aarch64_ins_addr_offset): New.
  13         * aarch64-asm-2.c: Regenerate.
  14         * aarch64-dis.h (ext_addr_offset): New.
  15         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
  16         (aarch64_ext_addr_offset): New.
  17         * aarch64-dis-2.c: Regenerate.
  18         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
  19         FLD_imm4_2 and FLD_SM3_imm2.
  20         * aarch64-opc.c (fields): Add FLD_imm6_2,
  21         FLD_imm4_2 and FLD_SM3_imm2.
  22         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
  23         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
  24         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
  25         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
  26         * aarch64-tbl.h
  27         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
  28
  29 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
  30
  31         * aarch64-tbl.h
  32         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
  33         (aarch64_feature_sm4, aarch64_feature_sha3): New.
  34         (aarch64_feature_fp_16_v8_2): New.
  35         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
  36         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
  37         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
  38
  39 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
  40
  41         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
  42         (aarch64_feature_sha2, aarch64_feature_aes): New.
  43         (SHA2, AES): New.
  44         (AES_INSN, SHA2_INSN): New.
  45         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
  46         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
  47          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
  48         Change to SHA2_INS.
  49
  50 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
  51             Tamar Christina <tamar.christina@arm.com>
  52
  53         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
  54         FP16 instructions, including vfmal.f16 and vfmsl.f16.
  55
  56 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
  57
  58         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
  59
  60 2017-11-07  Alan Modra  <amodra@gmail.com>
  61
  62         * opintl.h: Formatting, comment fixes.
  63         (gettext, ngettext): Redefine when ENABLE_NLS.
  64         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
  65         (_): Define using gettext.
  66         (textdomain, bindtextdomain): Use safer "do nothing".
  67
  68 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  69
  70         * arc-dis.c (print_hex): New variable.
  71         (parse_option): Check for hex option.
  72         (print_insn_arc): Use hexadecimal representation for short
  73         immediate values when requested.
  74         (print_arc_disassembler_options): Add hex option to the list.
  75
  76 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  77
  78         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
  79         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
  80         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
  81         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
  82         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
  83         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
  84         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
  85         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
  86         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
  87         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
  88         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
  89         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
  90         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
  91         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
  92         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
  93         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
  94         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
  95         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
  96         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
  97         Changed opcodes.
  98         (prealloc, prefetch*): Place them before ld instruction.
  99         * arc-opc.c (skip_this_opcode): Add ARITH class.
 100
 101 2017-10-25  Alan Modra  <amodra@gmail.com>
 102
 103         PR 22348
 104         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 105         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 106         (imm4flag, size_changed): Likewise.
 107         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 108         (words, allWords, processing_argument_number): Likewise.
 109         (cst4flag, size_changed): Likewise.
 110         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 111         (crx_cst4_maps): Rename from cst4_maps.
 112         (crx_no_op_insn): Rename from no_op_insn.
 113
 114 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 115
 116         * riscv-opc.c (match_c_addi16sp) : New function.
 117         (match_c_addi4spn): New function.
 118         (match_c_lui): Don't allow 0-immediate encodings.
 119         (riscv_opcodes) <addi>: Use the above functions.
 120         <add>: Likewise.
 121         <c.addi4spn>: Likewise.
 122         <c.addi16sp>: Likewise.
 123
 124 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 125
 126         * i386-init.h: Regenerate
 127         * i386-tbl.h: Likewise
 128
 129 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 130
 131         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 132         (enum): Add EVEX_W_0F3854_P_2.
 133         * i386-dis-evex.h (evex_table): Updated.
 134         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 135         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 136         (cpu_flags): Add CpuAVX512_BITALG.
 137         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 138         (i386_cpu_flags): Add cpuavx512_bitalg..
 139         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 140         * i386-init.h: Regenerate.
 141         * i386-tbl.h: Likewise.
 142
 143 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 144
 145         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 146         * i386-dis-evex.h (evex_table): Updated.
 147         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 148         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 149         (cpu_flags): Add CpuAVX512_VNNI.
 150         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 151         (i386_cpu_flags): Add cpuavx512_vnni.
 152         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 153         * i386-init.h: Regenerate.
 154         * i386-tbl.h: Likewise.
 155
 156 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 157
 158         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 159         (enum): Remove VEX_LEN_0F3A44_P_2.
 160         (vex_len_table): Ditto.
 161         (enum): Remove VEX_W_0F3A44_P_2.
 162         (vew_w_table): Ditto.
 163         (prefix_table): Adjust instructions (see prefixes above).
 164         * i386-dis-evex.h (evex_table):
 165         Add new instructions (see prefixes above).
 166         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 167         (bitfield_cpu_flags): Ditto.
 168         * i386-opc.h (enum): Ditto.
 169         (i386_cpu_flags): Ditto.
 170         (CpuUnused): Comment out to avoid zero-width field problem.
 171         * i386-opc.tbl (vpclmulqdq): New instruction.
 172         * i386-init.h: Regenerate.
 173         * i386-tbl.h: Ditto.
 174
 175 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 176
 177         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 178         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 179         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 180         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 181         (vex_len_table): Ditto.
 182         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 183         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 184         (vew_w_table): Ditto.
 185         (prefix_table): Adjust instructions (see prefixes above).
 186         * i386-dis-evex.h (evex_table):
 187         Add new instructions (see prefixes above).
 188         * i386-gen.c (cpu_flag_init): Add VAES.
 189         (bitfield_cpu_flags): Ditto.
 190         * i386-opc.h (enum): Ditto.
 191         (i386_cpu_flags): Ditto.
 192         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 193         * i386-init.h: Regenerate.
 194         * i386-tbl.h: Ditto.
 195
 196 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 197
 198         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 199         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 200         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 201         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 202         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 203         (prefix_table): Updated (see prefixes above).
 204         (three_byte_table): Likewise.
 205         (vex_w_table): Likewise.
 206         * i386-dis-evex.h: Likewise.
 207         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 208         (cpu_flags): Add CpuGFNI.
 209         * i386-opc.h (enum): Add CpuGFNI.
 210         (i386_cpu_flags): Add cpugfni.
 211         * i386-opc.tbl: Add Intel GFNI instructions.
 212         * i386-init.h: Regenerate.
 213         * i386-tbl.h: Likewise.
 214
 215 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 216
 217         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 218         Define EXbScalar and EXwScalar for OP_EX.
 219         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 220         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 221         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 222         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 223         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 224         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 225         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 226         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 227         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 228         (OP_E_memory): Likewise.
 229         * i386-dis-evex.h: Updated.
 230         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 231         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 232         (cpu_flags): Add CpuAVX512_VBMI2.
 233         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 234         (i386_cpu_flags): Add cpuavx512_vbmi2.
 235         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 236         * i386-init.h: Regenerate.
 237         * i386-tbl.h: Likewise.
 238
 239 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 240
 241         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 242
 243 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 244
 245         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 246         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 247         K15. Add jmpix pattern.
 248
 249 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 250
 251         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 252
 253 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 254
 255         * s390-opc.c (INSTR_SI_RD): New macro.
 256         (INSTR_S_RD): Adjust example instruction.
 257         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 258         SI_RD.
 259
 260 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 261
 262         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 263         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 264         VLE multimple load/store instructions. Old e_ldm* variants are
 265         kept as aliases.
 266         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 267
 268 2017-09-27  Nick Clifton  <nickc@redhat.com>
 269
 270         PR 22179
 271         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 272         names for the fmv.x.s and fmv.s.x instructions respectively.
 273
 274 2017-09-26  do  <do@nerilex.org>
 275
 276         PR 22123
 277         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 278         be used on CPUs that have emacs support.
 279
 280 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 281
 282         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 283
 284 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 285
 286         * nds32-asm.c: Rename __BIT() to N32_BIT().
 287         * nds32-asm.h: Likewise.
 288         * nds32-dis.c: Likewise.
 289
 290 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386-dis.c (last_active_prefix): Removed.
 293         (ckprefix): Don't set last_active_prefix.
 294         (NOTRACK_Fixup): Don't check last_active_prefix.
 295
 296 2017-08-31  Nick Clifton  <nickc@redhat.com>
 297
 298         * po/fr.po: Updated French translation.
 299
 300 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 301
 302         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 303         fields.
 304
 305 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 306             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 307
 308         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 309         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 310         New entries efs2 and spe2.
 311         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 312         (SPE2_OPCD_SEGS): New macro.
 313         (spe2_opcd_indices): New.
 314         (disassemble_init_powerpc): Handle SPE2 opcodes.
 315         (lookup_spe2): New function.
 316         (print_insn_powerpc): call lookup_spe2.
 317         * ppc-opc.c (insert_evuimm1_ex0): New function.
 318         (extract_evuimm1_ex0): Likewise.
 319         (insert_evuimm_lt8): Likewise.
 320         (extract_evuimm_lt8): Likewise.
 321         (insert_off_spe2): Likewise.
 322         (extract_off_spe2): Likewise.
 323         (insert_Ddd): Likewise.
 324         (extract_Ddd): Likewise.
 325         (DD): New operand.
 326         (EVUIMM_LT8): Likewise.
 327         (EVUIMM_LT16): Adjust.
 328         (MMMM): New operand.
 329         (EVUIMM_1): Likewise.
 330         (EVUIMM_1_EX0): Likewise.
 331         (EVUIMM_2): Adjust.
 332         (NNN): New operand.
 333         (VX_OFF_SPE2): Likewise.
 334         (BBB): Likewise.
 335         (DDD): Likewise.
 336         (VX_MASK_DDD): New mask.
 337         (HH): New operand.
 338         (VX_RA_CONST): New macro.
 339         (VX_RA_CONST_MASK): Likewise.
 340         (VX_RB_CONST): Likewise.
 341         (VX_RB_CONST_MASK): Likewise.
 342         (VX_OFF_SPE2_MASK): Likewise.
 343         (VX_SPE_CRFD): Likewise.
 344         (VX_SPE_CRFD_MASK VX): Likewise.
 345         (VX_SPE2_CLR): Likewise.
 346         (VX_SPE2_CLR_MASK): Likewise.
 347         (VX_SPE2_SPLATB): Likewise.
 348         (VX_SPE2_SPLATB_MASK): Likewise.
 349         (VX_SPE2_OCTET): Likewise.
 350         (VX_SPE2_OCTET_MASK): Likewise.
 351         (VX_SPE2_DDHH): Likewise.
 352         (VX_SPE2_DDHH_MASK): Likewise.
 353         (VX_SPE2_HH): Likewise.
 354         (VX_SPE2_HH_MASK): Likewise.
 355         (VX_SPE2_EVMAR): Likewise.
 356         (VX_SPE2_EVMAR_MASK): Likewise.
 357         (PPCSPE2): Likewise.
 358         (PPCEFS2): Likewise.
 359         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 360         (powerpc_macros): Map old SPE instructions have new names
 361         with the same opcodes. Add SPE2 instructions which just are
 362         mapped to SPE2.
 363         (spe2_opcodes): Add SPE2 opcodes.
 364
 365 2017-08-23  Alan Modra  <amodra@gmail.com>
 366
 367         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 368         extract functions earlier, deleting forward declarations.
 369         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 370         RA_MASK.
 371
 372 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 373
 374         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 375
 376 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 377             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 378
 379         * ppc-opc.c (insert_evuimm2_ex0): New function.
 380         (extract_evuimm2_ex0): Likewise.
 381         (insert_evuimm4_ex0): Likewise.
 382         (extract_evuimm4_ex0): Likewise.
 383         (insert_evuimm8_ex0): Likewise.
 384         (extract_evuimm8_ex0): Likewise.
 385         (insert_evuimm_lt16): Likewise.
 386         (extract_evuimm_lt16): Likewise.
 387         (insert_rD_rS_even): Likewise.
 388         (extract_rD_rS_even): Likewise.
 389         (insert_off_lsp): Likewise.
 390         (extract_off_lsp): Likewise.
 391         (RD_EVEN): New operand.
 392         (RS_EVEN): Likewise.
 393         (RSQ): Adjust.
 394         (EVUIMM_LT16): New operand.
 395         (HTM_SI): Adjust.
 396         (EVUIMM_2_EX0): New operand.
 397         (EVUIMM_4): Adjust.
 398         (EVUIMM_4_EX0): New operand.
 399         (EVUIMM_8): Adjust.
 400         (EVUIMM_8_EX0): New operand.
 401         (WS): Adjust.
 402         (VX_OFF): New operand.
 403         (VX_LSP): New macro.
 404         (VX_LSP_MASK): Likewise.
 405         (VX_LSP_OFF_MASK): Likewise.
 406         (PPC_OPCODE_LSP): Likewise.
 407         (vle_opcodes): Add LSP opcodes.
 408         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 409
 410 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 411
 412         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 413         register operands in CRC instructions.
 414         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 415         comments.
 416
 417 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 418
 419         * disassemble.c (disassembler): Mark big and mach with
 420         ATTRIBUTE_UNUSED.
 421
 422 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 423
 424         * disassemble.c (disassembler): Remove arch/mach/endian
 425         assertions.
 426
 427 2017-07-25  Nick Clifton  <nickc@redhat.com>
 428
 429         PR 21739
 430         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 431         message.
 432         (insert_r0): Likewise.
 433         (insert_r1): Likewise.
 434         (insert_r2): Likewise.
 435         (insert_r3): Likewise.
 436         (insert_sp): Likewise.
 437         (insert_gp): Likewise.
 438         (insert_pcl): Likewise.
 439         (insert_blink): Likewise.
 440         (insert_ilink1): Likewise.
 441         (insert_ilink2): Likewise.
 442         (insert_ras): Likewise.
 443         (insert_rbs): Likewise.
 444         (insert_rcs): Likewise.
 445         (insert_simm3s): Likewise.
 446         (insert_rrange): Likewise.
 447         (insert_r13el): Likewise.
 448         (insert_fpel): Likewise.
 449         (insert_blinkel): Likewise.
 450         (insert_pclel): Likewise.
 451         (insert_nps_bitop_size_2b): Likewise.
 452         (insert_nps_imm_offset): Likewise.
 453         (insert_nps_imm_entry): Likewise.
 454         (insert_nps_size_16bit): Likewise.
 455         (insert_nps_##NAME##_pos): Likewise.
 456         (insert_nps_##NAME): Likewise.
 457         (insert_nps_bitop_ins_ext): Likewise.
 458         (insert_nps_##NAME): Likewise.
 459         (insert_nps_min_hofs): Likewise.
 460         (insert_nps_##NAME): Likewise.
 461         (insert_nps_rbdouble_64): Likewise.
 462         (insert_nps_misc_imm_offset): Likewise.
 463         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 464         option description.
 465
 466 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 467             Jiong Wang  <jiong.wang@arm.com>
 468
 469         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 470         correct the print.
 471         * aarch64-dis-2.c: Regenerated.
 472
 473 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 474
 475         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 476         table.
 477
 478 2017-07-20  Nick Clifton  <nickc@redhat.com>
 479
 480         * po/de.po: Updated German translation.
 481
 482 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 483
 484         * arc-regs.h (sec_stat): New aux register.
 485         (aux_kernel_sp): Likewise.
 486         (aux_sec_u_sp): Likewise.
 487         (aux_sec_k_sp): Likewise.
 488         (sec_vecbase_build): Likewise.
 489         (nsc_table_top): Likewise.
 490         (nsc_table_base): Likewise.
 491         (ersec_stat): Likewise.
 492         (aux_sec_except): Likewise.
 493
 494 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 495
 496         * arc-opc.c (extract_uimm12_20): New function.
 497         (UIMM12_20): New operand.
 498         (SIMM3_5_S): Adjust.
 499         * arc-tbl.h (sjli): Add new instruction.
 500
 501 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 502             John Eric Martin  <John.Martin@emmicro-us.com>
 503
 504         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 505         (UIMM3_23): Adjust accordingly.
 506         * arc-regs.h: Add/correct jli_base register.
 507         * arc-tbl.h (jli_s): Likewise.
 508
 509 2017-07-18  Nick Clifton  <nickc@redhat.com>
 510
 511         PR 21775
 512         * aarch64-opc.c: Fix spelling typos.
 513         * i386-dis.c: Likewise.
 514
 515 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 516
 517         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 518         max_addr_offset and octets variables to size_t.
 519
 520 2017-07-12  Alan Modra  <amodra@gmail.com>
 521
 522         * po/da.po: Update from translationproject.org/latest/opcodes/.
 523         * po/de.po: Likewise.
 524         * po/es.po: Likewise.
 525         * po/fi.po: Likewise.
 526         * po/fr.po: Likewise.
 527         * po/id.po: Likewise.
 528         * po/it.po: Likewise.
 529         * po/nl.po: Likewise.
 530         * po/pt_BR.po: Likewise.
 531         * po/ro.po: Likewise.
 532         * po/sv.po: Likewise.
 533         * po/tr.po: Likewise.
 534         * po/uk.po: Likewise.
 535         * po/vi.po: Likewise.
 536         * po/zh_CN.po: Likewise.
 537
 538 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 539             Alan Modra  <amodra@gmail.com>
 540
 541         * cgen.sh: Mark generated files read-only.
 542         * epiphany-asm.c: Regenerate.
 543         * epiphany-desc.c: Regenerate.
 544         * epiphany-desc.h: Regenerate.
 545         * epiphany-dis.c: Regenerate.
 546         * epiphany-ibld.c: Regenerate.
 547         * epiphany-opc.c: Regenerate.
 548         * epiphany-opc.h: Regenerate.
 549         * fr30-asm.c: Regenerate.
 550         * fr30-desc.c: Regenerate.
 551         * fr30-desc.h: Regenerate.
 552         * fr30-dis.c: Regenerate.
 553         * fr30-ibld.c: Regenerate.
 554         * fr30-opc.c: Regenerate.
 555         * fr30-opc.h: Regenerate.
 556         * frv-asm.c: Regenerate.
 557         * frv-desc.c: Regenerate.
 558         * frv-desc.h: Regenerate.
 559         * frv-dis.c: Regenerate.
 560         * frv-ibld.c: Regenerate.
 561         * frv-opc.c: Regenerate.
 562         * frv-opc.h: Regenerate.
 563         * ip2k-asm.c: Regenerate.
 564         * ip2k-desc.c: Regenerate.
 565         * ip2k-desc.h: Regenerate.
 566         * ip2k-dis.c: Regenerate.
 567         * ip2k-ibld.c: Regenerate.
 568         * ip2k-opc.c: Regenerate.
 569         * ip2k-opc.h: Regenerate.
 570         * iq2000-asm.c: Regenerate.
 571         * iq2000-desc.c: Regenerate.
 572         * iq2000-desc.h: Regenerate.
 573         * iq2000-dis.c: Regenerate.
 574         * iq2000-ibld.c: Regenerate.
 575         * iq2000-opc.c: Regenerate.
 576         * iq2000-opc.h: Regenerate.
 577         * lm32-asm.c: Regenerate.
 578         * lm32-desc.c: Regenerate.
 579         * lm32-desc.h: Regenerate.
 580         * lm32-dis.c: Regenerate.
 581         * lm32-ibld.c: Regenerate.
 582         * lm32-opc.c: Regenerate.
 583         * lm32-opc.h: Regenerate.
 584         * lm32-opinst.c: Regenerate.
 585         * m32c-asm.c: Regenerate.
 586         * m32c-desc.c: Regenerate.
 587         * m32c-desc.h: Regenerate.
 588         * m32c-dis.c: Regenerate.
 589         * m32c-ibld.c: Regenerate.
 590         * m32c-opc.c: Regenerate.
 591         * m32c-opc.h: Regenerate.
 592         * m32r-asm.c: Regenerate.
 593         * m32r-desc.c: Regenerate.
 594         * m32r-desc.h: Regenerate.
 595         * m32r-dis.c: Regenerate.
 596         * m32r-ibld.c: Regenerate.
 597         * m32r-opc.c: Regenerate.
 598         * m32r-opc.h: Regenerate.
 599         * m32r-opinst.c: Regenerate.
 600         * mep-asm.c: Regenerate.
 601         * mep-desc.c: Regenerate.
 602         * mep-desc.h: Regenerate.
 603         * mep-dis.c: Regenerate.
 604         * mep-ibld.c: Regenerate.
 605         * mep-opc.c: Regenerate.
 606         * mep-opc.h: Regenerate.
 607         * mt-asm.c: Regenerate.
 608         * mt-desc.c: Regenerate.
 609         * mt-desc.h: Regenerate.
 610         * mt-dis.c: Regenerate.
 611         * mt-ibld.c: Regenerate.
 612         * mt-opc.c: Regenerate.
 613         * mt-opc.h: Regenerate.
 614         * or1k-asm.c: Regenerate.
 615         * or1k-desc.c: Regenerate.
 616         * or1k-desc.h: Regenerate.
 617         * or1k-dis.c: Regenerate.
 618         * or1k-ibld.c: Regenerate.
 619         * or1k-opc.c: Regenerate.
 620         * or1k-opc.h: Regenerate.
 621         * or1k-opinst.c: Regenerate.
 622         * xc16x-asm.c: Regenerate.
 623         * xc16x-desc.c: Regenerate.
 624         * xc16x-desc.h: Regenerate.
 625         * xc16x-dis.c: Regenerate.
 626         * xc16x-ibld.c: Regenerate.
 627         * xc16x-opc.c: Regenerate.
 628         * xc16x-opc.h: Regenerate.
 629         * xstormy16-asm.c: Regenerate.
 630         * xstormy16-desc.c: Regenerate.
 631         * xstormy16-desc.h: Regenerate.
 632         * xstormy16-dis.c: Regenerate.
 633         * xstormy16-ibld.c: Regenerate.
 634         * xstormy16-opc.c: Regenerate.
 635         * xstormy16-opc.h: Regenerate.
 636
 637 2017-07-07  Alan Modra  <amodra@gmail.com>
 638
 639         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 640         * m32c-dis.c: Regenerate.
 641         * mep-dis.c: Regenerate.
 642
 643 2017-07-05  Borislav Petkov  <bp@suse.de>
 644
 645         * i386-dis.c: Enable ModRM.reg /6 aliases.
 646
 647 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 648
 649         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 650         with vmrs and vmsr.
 651
 652 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 653
 654         * configure: Regenerate.
 655
 656 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 657
 658         * po/opcodes.pot: Regenerate.
 659
 660 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 661
 662         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 663         entries to the MSA ASE instruction block.
 664
 665 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 666             Maciej W. Rozycki  <macro@imgtec.com>
 667
 668         * micromips-opc.c (XPA, XPAVZ): New macros.
 669         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 670         "mthgc0".
 671
 672 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 673             Maciej W. Rozycki  <macro@imgtec.com>
 674
 675         * micromips-opc.c (I36): New macro.
 676         (micromips_opcodes): Add "eretnc".
 677
 678 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 679             Andrew Bennett  <andrew.bennett@imgtec.com>
 680
 681         * mips-dis.c (mips_calculate_combination_ases): Handle the
 682         ASE_XPA_VIRT flag.
 683         (parse_mips_ase_option): New function.
 684         (parse_mips_dis_option): Factor out ASE option handling to the
 685         new function.  Call `mips_calculate_combination_ases'.
 686         * mips-opc.c (XPAVZ): New macro.
 687         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 688         "mfhgc0", "mthc0" and "mthgc0".
 689
 690 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 691
 692         * mips-dis.c (mips_calculate_combination_ases): New function.
 693         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 694         calculation to the new function.
 695         (set_default_mips_dis_options): Call the new function.
 696
 697 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 698
 699         * arc-dis.c (parse_disassembler_options): Use
 700         FOR_EACH_DISASSEMBLER_OPTION.
 701
 702 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 703
 704         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 705         disassembler option strings.
 706         (parse_cpu_option): Likewise.
 707
 708 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 709
 710         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 711         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 712         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 713         (aarch64_feature_dotprod, DOT_INSN): New.
 714         (udot, sdot): New.
 715         * aarch64-dis-2.c: Regenerated.
 716
 717 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 718
 719         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 720
 721 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 722             Matthew Fortune  <matthew.fortune@imgtec.com>
 723             Andrew Bennett  <andrew.bennett@imgtec.com>
 724
 725         * mips-formats.h (INT_BIAS): New macro.
 726         (INT_ADJ): Redefine in INT_BIAS terms.
 727         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 728         (mips_print_save_restore): New function.
 729         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 730         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 731         call.
 732         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 733         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 734         OP_SAVE_RESTORE_LIST handling, factored out from here.
 735         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 736         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 737         (mips_builtin_opcodes): Add "restore" and "save" entries.
 738         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 739         (IAMR2): New macro.
 740         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 741
 742 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 743
 744         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 745         alias; do not mark SLTI instruction as an alias.
 746
 747 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-dis.c (RM_0FAE_REG_5): Removed.
 750         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 751         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 752         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 753         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 754         PREFIX_MOD_3_0F01_REG_5_RM_0.
 755         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 756         PREFIX_MOD_3_0FAE_REG_5.
 757         (mod_table): Update MOD_0FAE_REG_5.
 758         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 759         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 760         * i386-tbl.h: Regenerated.
 761
 762 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 763
 764         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 765         * i386-opc.tbl: Likewise.
 766         * i386-tbl.h: Regenerated.
 767
 768 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 771         and "jmp{&|}".
 772         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 773         prefix.
 774
 775 2017-06-19  Nick Clifton  <nickc@redhat.com>
 776
 777         PR binutils/21614
 778         * score-dis.c (score_opcodes): Add sentinel.
 779
 780 2017-06-16  Alan Modra  <amodra@gmail.com>
 781
 782         * rx-decode.c: Regenerate.
 783
 784 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 785
 786         PR binutils/21594
 787         * i386-dis.c (OP_E_register): Check valid bnd register.
 788         (OP_G): Likewise.
 789
 790 2017-06-15  Nick Clifton  <nickc@redhat.com>
 791
 792         PR binutils/21595
 793         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 794         range value.
 795
 796 2017-06-15  Nick Clifton  <nickc@redhat.com>
 797
 798         PR binutils/21588
 799         * rl78-decode.opc (OP_BUF_LEN): Define.
 800         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 801         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 802         array.
 803         * rl78-decode.c: Regenerate.
 804
 805 2017-06-15  Nick Clifton  <nickc@redhat.com>
 806
 807         PR binutils/21586
 808         * bfin-dis.c (gregs): Clip index to prevent overflow.
 809         (regs): Likewise.
 810         (regs_lo): Likewise.
 811         (regs_hi): Likewise.
 812
 813 2017-06-14  Nick Clifton  <nickc@redhat.com>
 814
 815         PR binutils/21576
 816         * score7-dis.c (score_opcodes): Add sentinel.
 817
 818 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 819
 820         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 821         * arm-dis.c: Likewise.
 822         * ia64-dis.c: Likewise.
 823         * mips-dis.c: Likewise.
 824         * spu-dis.c: Likewise.
 825         * disassemble.h (print_insn_aarch64): New declaration, moved from
 826         include/dis-asm.h.
 827         (print_insn_big_arm, print_insn_big_mips): Likewise.
 828         (print_insn_i386, print_insn_ia64): Likewise.
 829         (print_insn_little_arm, print_insn_little_mips): Likewise.
 830
 831 2017-06-14  Nick Clifton  <nickc@redhat.com>
 832
 833         PR binutils/21587
 834         * rx-decode.opc: Include libiberty.h
 835         (GET_SCALE): New macro - validates access to SCALE array.
 836         (GET_PSCALE): New macro - validates access to PSCALE array.
 837         (DIs, SIs, S2Is, rx_disp): Use new macros.
 838         * rx-decode.c: Regenerate.
 839
 840 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 841
 842         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 843
 844 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 845
 846         * arc-dis.c (enforced_isa_mask): Declare.
 847         (cpu_types): Likewise.
 848         (parse_cpu_option): New function.
 849         (parse_disassembler_options): Use it.
 850         (print_insn_arc): Use enforced_isa_mask.
 851         (print_arc_disassembler_options): Document new options.
 852
 853 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 854
 855         * alpha-dis.c: Include disassemble.h, don't include
 856         dis-asm.h.
 857         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 858         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 859         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 860         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 861         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 862         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 863         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 864         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 865         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 866         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 867         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 868         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 869         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 870         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 871         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 872         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 873         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 874         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 875         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 876         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 877         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 878         * z80-dis.c, z8k-dis.c: Likewise.
 879         * disassemble.h: New file.
 880
 881 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 882
 883         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 884         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 885
 886 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 887
 888         * disassemble.c (disassembler): Add arguments a, big and mach.
 889         Use them.
 890
 891 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 892
 893         * i386-dis.c (NOTRACK_Fixup): New.
 894         (NOTRACK): Likewise.
 895         (NOTRACK_PREFIX): Likewise.
 896         (last_active_prefix): Likewise.
 897         (reg_table): Use NOTRACK on indirect call and jmp.
 898         (ckprefix): Set last_active_prefix.
 899         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 900         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 901         * i386-opc.h (NoTrackPrefixOk): New.
 902         (i386_opcode_modifier): Add notrackprefixok.
 903         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 904         Add notrack.
 905         * i386-tbl.h: Regenerated.
 906
 907 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 908
 909         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 910         (X_IMM2): Define.
 911         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 912         bfd_mach_sparc_v9m8.
 913         (print_insn_sparc): Handle new operand types.
 914         * sparc-opc.c (MASK_M8): Define.
 915         (v6): Add MASK_M8.
 916         (v6notlet): Likewise.
 917         (v7): Likewise.
 918         (v8): Likewise.
 919         (v9): Likewise.
 920         (v9a): Likewise.
 921         (v9b): Likewise.
 922         (v9c): Likewise.
 923         (v9d): Likewise.
 924         (v9e): Likewise.
 925         (v9v): Likewise.
 926         (v9m): Likewise.
 927         (v9andleon): Likewise.
 928         (m8): Define.
 929         (HWS_VM8): Define.
 930         (HWS2_VM8): Likewise.
 931         (sparc_opcode_archs): Add entry for "m8".
 932         (sparc_opcodes): Add OSA2017 and M8 instructions
 933         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 934         fpx{ll,ra,rl}64x,
 935         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 936         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 937         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 938         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 939         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 940         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 941         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 942         ASI_CORE_SELECT_COMMIT_NHT.
 943
 944 2017-05-18  Alan Modra  <amodra@gmail.com>
 945
 946         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 947         * aarch64-dis.c: Likewise.
 948         * aarch64-gen.c: Likewise.
 949         * aarch64-opc.c: Likewise.
 950
 951 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 952             Matthew Fortune  <matthew.fortune@imgtec.com>
 953
 954         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 955         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 956         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 957         (print_insn_arg) <OP_REG28>: Add handler.
 958         (validate_insn_args) <OP_REG28>: Handle.
 959         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 960         32-bit encoding and 9-bit immediates.
 961         (print_insn_mips16): Handle MIPS16 instructions that require
 962         32-bit encoding and MFC0/MTC0 operand decoding.
 963         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 964         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 965         (RD_C0, WR_C0, E2, E2MT): New macros.
 966         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 967         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 968         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 969         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 970         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 971         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 972         instructions, "swl", "swr", "sync" and its "sync_acquire",
 973         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 974         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 975         regular/extended entries for original MIPS16 ISA revision
 976         instructions whose extended forms are subdecoded in the MIPS16e2
 977         ISA revision: "li", "sll" and "srl".
 978
 979 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 980
 981         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 982         reference in CP0 move operand decoding.
 983
 984 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 985
 986         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 987         type to hexadecimal.
 988         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 989
 990 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 991
 992         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 993         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 994         "sync_rmb" and "sync_wmb" as aliases.
 995         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 996         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 997
 998 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 999
1000         * arc-dis.c (parse_option): Update quarkse_em option..
1001         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1002         QUARKSE1.
1003         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1004
1005 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1006
1007         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1008
1009 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1010
1011         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1012         register.
1013
1014 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1015
1016         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1017         and branches and not synthetic data instructions.
1018
1019 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1020
1021         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1022
1023 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1024
1025         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1026         * arc-opc.c (insert_r13el): New function.
1027         (R13_EL): Define.
1028         * arc-tbl.h: Add new enter/leave variants.
1029
1030 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1031
1032         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1033
1034 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1035
1036         * mips-dis.c (print_mips_disassembler_options): Add
1037         `no-aliases'.
1038
1039 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1040
1041         * mips16-opc.c (AL): New macro.
1042         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1043         of "ld" and "lw" as aliases.
1044
1045 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1046
1047         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1048         arguments.
1049
1050 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1051             Alan Modra  <amodra@gmail.com>
1052
1053         * ppc-opc.c (ELEV): Define.
1054         (vle_opcodes): Add se_rfgi and e_sc.
1055         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1056         for E200Z4.
1057
1058 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1059
1060         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1061
1062 2017-04-21  Nick Clifton  <nickc@redhat.com>
1063
1064         PR binutils/21380
1065         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1066         LD3R and LD4R.
1067
1068 2017-04-13  Alan Modra  <amodra@gmail.com>
1069
1070         * epiphany-desc.c: Regenerate.
1071         * fr30-desc.c: Regenerate.
1072         * frv-desc.c: Regenerate.
1073         * ip2k-desc.c: Regenerate.
1074         * iq2000-desc.c: Regenerate.
1075         * lm32-desc.c: Regenerate.
1076         * m32c-desc.c: Regenerate.
1077         * m32r-desc.c: Regenerate.
1078         * mep-desc.c: Regenerate.
1079         * mt-desc.c: Regenerate.
1080         * or1k-desc.c: Regenerate.
1081         * xc16x-desc.c: Regenerate.
1082         * xstormy16-desc.c: Regenerate.
1083
1084 2017-04-11  Alan Modra  <amodra@gmail.com>
1085
1086         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1087         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1088         PPC_OPCODE_TMR for e6500.
1089         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1090         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1091         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1092         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1093         (PPCHTM): Define as PPC_OPCODE_POWER8.
1094         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1095
1096 2017-04-10  Alan Modra  <amodra@gmail.com>
1097
1098         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1099         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1100         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1101         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1102
1103 2017-04-09  Pip Cet  <pipcet@gmail.com>
1104
1105         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1106         appropriate floating-point precision directly.
1107
1108 2017-04-07  Alan Modra  <amodra@gmail.com>
1109
1110         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1111         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1112         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1113         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1114         vector instructions with E6500 not PPCVEC2.
1115
1116 2017-04-06  Pip Cet  <pipcet@gmail.com>
1117
1118         * Makefile.am: Add wasm32-dis.c.
1119         * configure.ac: Add wasm32-dis.c to wasm32 target.
1120         * disassemble.c: Add wasm32 disassembler code.
1121         * wasm32-dis.c: New file.
1122         * Makefile.in: Regenerate.
1123         * configure: Regenerate.
1124         * po/POTFILES.in: Regenerate.
1125         * po/opcodes.pot: Regenerate.
1126
1127 2017-04-05  Pedro Alves  <palves@redhat.com>
1128
1129         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1130         * arm-dis.c (parse_arm_disassembler_options): Constify.
1131         * ppc-dis.c (powerpc_init_dialect): Constify local.
1132         * vax-dis.c (parse_disassembler_options): Constify.
1133
1134 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1135
1136         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1137         RISCV_GP_SYMBOL.
1138
1139 2017-03-30  Pip Cet  <pipcet@gmail.com>
1140
1141         * configure.ac: Add (empty) bfd_wasm32_arch target.
1142         * configure: Regenerate
1143         * po/opcodes.pot: Regenerate.
1144
1145 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1146
1147         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1148         OSA2015.
1149         * opcodes/sparc-opc.c (asi_table): New ASIs.
1150
1151 2017-03-29  Alan Modra  <amodra@gmail.com>
1152
1153         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1154         "raw" option.
1155         (lookup_powerpc): Don't special case -1 dialect.  Handle
1156         PPC_OPCODE_RAW.
1157         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1158         lookup_powerpc call, pass it on second.
1159
1160 2017-03-27  Alan Modra  <amodra@gmail.com>
1161
1162         PR 21303
1163         * ppc-dis.c (struct ppc_mopt): Comment.
1164         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1165
1166 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1167
1168         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1169         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1170         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1171         (insert_nps_misc_imm_offset): New function.
1172         (extract_nps_misc imm_offset): New function.
1173         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1174         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1175
1176 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1177
1178         * s390-mkopc.c (main): Remove vx2 check.
1179         * s390-opc.txt: Remove vx2 instruction flags.
1180
1181 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1182
1183         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1184         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1185         (insert_nps_imm_offset): New function.
1186         (extract_nps_imm_offset): New function.
1187         (insert_nps_imm_entry): New function.
1188         (extract_nps_imm_entry): New function.
1189
1190 2017-03-17  Alan Modra  <amodra@gmail.com>
1191
1192         PR 21248
1193         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1194         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1195         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1196
1197 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1198
1199         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1200         <c.andi>: Likewise.
1201         <c.addiw> Likewise.
1202
1203 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1204
1205         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1206
1207 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1208
1209         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1210         <srl> Likewise.
1211         <srai> Likewise.
1212         <sra> Likewise.
1213
1214 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1215
1216         * i386-gen.c (opcode_modifiers): Replace S with Load.
1217         * i386-opc.h (S): Removed.
1218         (Load): New.
1219         (i386_opcode_modifier): Replace s with load.
1220         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1221         and {evex}.  Replace S with Load.
1222         * i386-tbl.h: Regenerated.
1223
1224 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1225
1226         * i386-opc.tbl: Use CpuCET on rdsspq.
1227         * i386-tbl.h: Regenerated.
1228
1229 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1230
1231         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1232         <vsx>: Do not use PPC_OPCODE_VSX3;
1233
1234 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1235
1236         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1237
1238 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1239
1240         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1241         (MOD_0F1E_PREFIX_1): Likewise.
1242         (MOD_0F38F5_PREFIX_2): Likewise.
1243         (MOD_0F38F6_PREFIX_0): Likewise.
1244         (RM_0F1E_MOD_3_REG_7): Likewise.
1245         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1246         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1247         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1248         (PREFIX_0F1E): Likewise.
1249         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1250         (PREFIX_0F38F5): Likewise.
1251         (dis386_twobyte): Use PREFIX_0F1E.
1252         (reg_table): Add REG_0F1E_MOD_3.
1253         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1254         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1255         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1256         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1257         (three_byte_table): Use PREFIX_0F38F5.
1258         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1259         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1260         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1261         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1262         PREFIX_MOD_3_0F01_REG_5_RM_2.
1263         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1264         (cpu_flags): Add CpuCET.
1265         * i386-opc.h (CpuCET): New enum.
1266         (CpuUnused): Commented out.
1267         (i386_cpu_flags): Add cpucet.
1268         * i386-opc.tbl: Add Intel CET instructions.
1269         * i386-init.h: Regenerated.
1270         * i386-tbl.h: Likewise.
1271
1272 2017-03-06  Alan Modra  <amodra@gmail.com>
1273
1274         PR 21124
1275         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1276         (extract_raq, extract_ras, extract_rbx): New functions.
1277         (powerpc_operands): Use opposite corresponding insert function.
1278         (Q_MASK): Define.
1279         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1280         register restriction.
1281
1282 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1283
1284         * disassemble.c Include "safe-ctype.h".
1285         (disassemble_init_for_target): Handle s390 init.
1286         (remove_whitespace_and_extra_commas): New function.
1287         (disassembler_options_cmp): Likewise.
1288         * arm-dis.c: Include "libiberty.h".
1289         (NUM_ELEM): Delete.
1290         (regnames): Use long disassembler style names.
1291         Add force-thumb and no-force-thumb options.
1292         (NUM_ARM_REGNAMES): Rename from this...
1293         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1294         (get_arm_regname_num_options): Delete.
1295         (set_arm_regname_option): Likewise.
1296         (get_arm_regnames): Likewise.
1297         (parse_disassembler_options): Likewise.
1298         (parse_arm_disassembler_option): Rename from this...
1299         (parse_arm_disassembler_options): ...to this.  Make static.
1300         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1301         (print_insn): Use parse_arm_disassembler_options.
1302         (disassembler_options_arm): New function.
1303         (print_arm_disassembler_options): Handle updated regnames.
1304         * ppc-dis.c: Include "libiberty.h".
1305         (ppc_opts): Add "32" and "64" entries.
1306         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1307         (powerpc_init_dialect): Add break to switch statement.
1308         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1309         (disassembler_options_powerpc): New function.
1310         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1311         Remove printing of "32" and "64".
1312         * s390-dis.c: Include "libiberty.h".
1313         (init_flag): Remove unneeded variable.
1314         (struct s390_options_t): New structure type.
1315         (options): New structure.
1316         (init_disasm): Rename from this...
1317         (disassemble_init_s390): ...to this.  Add initializations for
1318         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1319         (print_insn_s390): Delete call to init_disasm.
1320         (disassembler_options_s390): New function.
1321         (print_s390_disassembler_options): Print using information from
1322         struct 'options'.
1323         * po/opcodes.pot: Regenerate.
1324
1325 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1326
1327         * i386-dis.c (PCMPESTR_Fixup): New.
1328         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1329         (prefix_table): Use PCMPESTR_Fixup.
1330         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1331         PCMPESTR_Fixup.
1332         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1333         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1334         Split 64-bit and non-64-bit variants.
1335         * opcodes/i386-tbl.h: Re-generate.
1336
1337 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1338
1339         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1340         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1341         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1342         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1343         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1344         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1345         (OP_SVE_V_HSD): New macros.
1346         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1347         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1348         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1349         (aarch64_opcode_table): Add new SVE instructions.
1350         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1351         for rotation operands.  Add new SVE operands.
1352         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1353         (ins_sve_quad_index): Likewise.
1354         (ins_imm_rotate): Split into...
1355         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1356         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1357         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1358         functions.
1359         (aarch64_ins_sve_addr_ri_s4): New function.
1360         (aarch64_ins_sve_quad_index): Likewise.
1361         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1362         * aarch64-asm-2.c: Regenerate.
1363         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1364         (ext_sve_quad_index): Likewise.
1365         (ext_imm_rotate): Split into...
1366         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1367         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1368         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1369         functions.
1370         (aarch64_ext_sve_addr_ri_s4): New function.
1371         (aarch64_ext_sve_quad_index): Likewise.
1372         (aarch64_ext_sve_index): Allow quad indices.
1373         (do_misc_decoding): Likewise.
1374         * aarch64-dis-2.c: Regenerate.
1375         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1376         aarch64_field_kinds.
1377         (OPD_F_OD_MASK): Widen by one bit.
1378         (OPD_F_NO_ZR): Bump accordingly.
1379         (get_operand_field_width): New function.
1380         * aarch64-opc.c (fields): Add new SVE fields.
1381         (operand_general_constraint_met_p): Handle new SVE operands.
1382         (aarch64_print_operand): Likewise.
1383         * aarch64-opc-2.c: Regenerate.
1384
1385 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1386
1387         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1388         (aarch64_feature_compnum): ...this.
1389         (SIMD_V8_3): Replace with...
1390         (COMPNUM): ...this.
1391         (CNUM_INSN): New macro.
1392         (aarch64_opcode_table): Use it for the complex number instructions.
1393
1394 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1395
1396         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1397
1398 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1399
1400         Add support for associating SPARC ASIs with an architecture level.
1401         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1402         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1403         decoding of SPARC ASIs.
1404
1405 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1406
1407         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1408         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1409
1410 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1411
1412         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1413         1 (instead of to itself). Correct typo.
1414
1415 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1416
1417         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1418         pseudoinstructions.
1419
1420 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1421
1422         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1423         (aarch64_sys_reg_supported_p): Handle them.
1424
1425 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1426
1427         * arc-opc.c (UIMM6_20R): Define.
1428         (SIMM12_20): Use above.
1429         (SIMM12_20R): Define.
1430         (SIMM3_5_S): Use above.
1431         (UIMM7_A32_11R_S): Define.
1432         (UIMM7_9_S): Use above.
1433         (UIMM3_13R_S): Define.
1434         (SIMM11_A32_7_S): Use above.
1435         (SIMM9_8R): Define.
1436         (UIMM10_A32_8_S): Use above.
1437         (UIMM8_8R_S): Define.
1438         (W6): Use above.
1439         (arc_relax_opcodes): Use all above defines.
1440
1441 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1442
1443         * arc-regs.h: Distinguish some of the registers different on
1444         ARC700 and HS38 cpus.
1445
1446 2017-02-14  Alan Modra  <amodra@gmail.com>
1447
1448         PR 21118
1449         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1450         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1451
1452 2017-02-11  Stafford Horne  <shorne@gmail.com>
1453             Alan Modra  <amodra@gmail.com>
1454
1455         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1456         Use insn_bytes_value and insn_int_value directly instead.  Don't
1457         free allocated memory until function exit.
1458
1459 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1460
1461         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1462
1463 2017-02-03  Nick Clifton  <nickc@redhat.com>
1464
1465         PR 21096
1466         * aarch64-opc.c (print_register_list): Ensure that the register
1467         list index will fir into the tb buffer.
1468         (print_register_offset_address): Likewise.
1469         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1470
1471 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1472
1473         PR 21056
1474         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1475         instructions when the previous fetch packet ends with a 32-bit
1476         instruction.
1477
1478 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1479
1480         * pru-opc.c: Remove vague reference to a future GDB port.
1481
1482 2017-01-20  Nick Clifton  <nickc@redhat.com>
1483
1484         * po/ga.po: Updated Irish translation.
1485
1486 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1487
1488         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1489
1490 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1491
1492         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1493         if FETCH_DATA returns 0.
1494         (m68k_scan_mask): Likewise.
1495         (print_insn_m68k): Update code to handle -1 return value.
1496
1497 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1498
1499         * m68k-dis.c (enum print_insn_arg_error): New.
1500         (NEXTBYTE): Replace -3 with
1501         PRINT_INSN_ARG_MEMORY_ERROR.
1502         (NEXTULONG): Likewise.
1503         (NEXTSINGLE): Likewise.
1504         (NEXTDOUBLE): Likewise.
1505         (NEXTDOUBLE): Likewise.
1506         (NEXTPACKED): Likewise.
1507         (FETCH_ARG): Likewise.
1508         (FETCH_DATA): Update comments.
1509         (print_insn_arg): Update comments. Replace magic numbers with
1510         enum.
1511         (match_insn_m68k): Likewise.
1512
1513 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1514
1515         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1516         * i386-dis-evex.h (evex_table): Updated.
1517         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1518         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1519         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1520         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1521         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1522         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1523         * i386-init.h: Regenerate.
1524         * i386-tbl.h: Ditto.
1525
1526 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1527
1528         * msp430-dis.c (msp430_singleoperand): Return -1 if
1529         msp430dis_opcode_signed returns false.
1530         (msp430_doubleoperand): Likewise.
1531         (msp430_branchinstr): Return -1 if
1532         msp430dis_opcode_unsigned returns false.
1533         (msp430x_calla_instr): Likewise.
1534         (print_insn_msp430): Likewise.
1535
1536 2017-01-05  Nick Clifton  <nickc@redhat.com>
1537
1538         PR 20946
1539         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1540         could not be matched.
1541         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1542         NULL.
1543
1544 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1545
1546         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1547         (aarch64_opcode_table): Use RCPC_INSN.
1548
1549 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1550
1551         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1552         extension.
1553         * riscv-opcodes/all-opcodes: Likewise.
1554
1555 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1556
1557         * riscv-dis.c (print_insn_args): Add fall through comment.
1558
1559 2017-01-03  Nick Clifton  <nickc@redhat.com>
1560
1561         * po/sr.po: New Serbian translation.
1562         * configure.ac (ALL_LINGUAS): Add sr.
1563         * configure: Regenerate.
1564
1565 2017-01-02  Alan Modra  <amodra@gmail.com>
1566
1567         * epiphany-desc.h: Regenerate.
1568         * epiphany-opc.h: Regenerate.
1569         * fr30-desc.h: Regenerate.
1570         * fr30-opc.h: Regenerate.
1571         * frv-desc.h: Regenerate.
1572         * frv-opc.h: Regenerate.
1573         * ip2k-desc.h: Regenerate.
1574         * ip2k-opc.h: Regenerate.
1575         * iq2000-desc.h: Regenerate.
1576         * iq2000-opc.h: Regenerate.
1577         * lm32-desc.h: Regenerate.
1578         * lm32-opc.h: Regenerate.
1579         * m32c-desc.h: Regenerate.
1580         * m32c-opc.h: Regenerate.
1581         * m32r-desc.h: Regenerate.
1582         * m32r-opc.h: Regenerate.
1583         * mep-desc.h: Regenerate.
1584         * mep-opc.h: Regenerate.
1585         * mt-desc.h: Regenerate.
1586         * mt-opc.h: Regenerate.
1587         * or1k-desc.h: Regenerate.
1588         * or1k-opc.h: Regenerate.
1589         * xc16x-desc.h: Regenerate.
1590         * xc16x-opc.h: Regenerate.
1591         * xstormy16-desc.h: Regenerate.
1592         * xstormy16-opc.h: Regenerate.
1593
1594 2017-01-02  Alan Modra  <amodra@gmail.com>
1595
1596         Update year range in copyright notice of all files.
1597
1598 For older changes see ChangeLog-2016
1599 \f
1600 Copyright (C) 2017 Free Software Foundation, Inc.
1601
1602 Copying and distribution of this file, with or without modification,
1603 are permitted in any medium without royalty provided the copyright
1604 notice and this notice are preserved.
1605
1606 Local Variables:
1607 mode: change-log
1608 left-margin: 8
1609 fill-column: 74
1610 version-control: never
1611 End: