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x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2017-12-18 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
4 RegZMM.
5 (opcode_modifiers): Drop FirstXmm0.
6 (operand_types): Replace RegXMM, RegYMM, and RegZMM with just
7 RegSIMD.
8 * i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
9 (struct i386_opcode_modifier): Drop firstxmm0.
10 (enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
11 just RegSIMD. Extend comment.
12 (union i386_operand_type): Replace regxmm, regymm, and regzmm
13 with just regsimd.
14 * i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
15 Acc|Xmmword.
16 * i386-reg.tbl (xmm0): Add Acc.
17 * i386-init.h, i386-tbl.h: Re-generate.
18
19 2017-12-18 Jan Beulich <jbeulich@suse.com>
20
21 * i386-gen.c (operand_type_shorthands): Add FloatAcc and
22 FloatReg.
23 (operand_types): Drop FloatAcc and FloatReg.
24 * i386-opc.h (enum of operand types): Likewise. Extend comment.
25 (union i386_operand_type): Drop floatacc and floatreg.
26 * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
27 * i386-init.h, i386-tbl.h: Re-generate.
28
29 2017-12-18 Jan Beulich <jbeulich@suse.com>
30
31 * i386-gen.c (operand_type_shorthands): New.
32 (opcode_modifiers): Replace Reg<N> with just Reg.
33 (set_bitfield_from_cpu_flag_init): Rename to
34 set_bitfield_from_shorthand. Drop value parameter. Process
35 operand_type_shorthands.
36 (set_bitfield): Adjust call accordingly.
37 * i386-opc.h (enum of operand types): Replace Reg<N> with just
38 Reg.
39 (union i386_operand_type): Replace reg<N> with just reg.
40 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
41 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
42 separate register and memory forms.
43 * i386-reg.tbl (al): Drop Byte.
44 (ax): Drop Word.
45 (eax): Drop Dword.
46 (rax): Drop Qword.
47 * i386-init.h, i386-tbl.h: Re-generate.
48
49 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
50
51 * disassemble.c (disassemble_init_for_target): Don't put PRU
52 between powerpc and rs6000 cases.
53
54 2017-12-15 Jan Beulich <jbeulich@suse.com>
55
56 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
57 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
58 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
59 stos, sub, test, xor): Drop CheckRegSize from variants not
60 allowing for two (or more) register operands.
61 * i386-tbl.h: Re-generate.
62
63 2017-12-13 Jim Wilson <jimw@sifive.com>
64
65 PR 22599
66 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
67
68 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
69
70 * disassemble.c: Enable disassembler_needs_relocs for PRU.
71
72 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
73 Renlin Li <renlin.li@arm.com>
74
75 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
76 (get_sym_code_type): Here.
77
78 2017-12-03 Alan Modra <amodra@gmail.com>
79
80 * ppc-opc.c (extract_li20): Rewrite.
81
82 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
83
84 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
85 (operand_value_powerpc): Update return and argument type.
86 <value, top>: Update type.
87 (skip_optional_operands): Update argument type.
88 (lookup_powerpc): Likewise.
89 (lookup_vle): Likewise.
90 <table_opcd, table_mask, insn2>: Update type.
91 (lookup_spe2): Update argument type.
92 <table_opcd, table_mask, insn2>: Update type.
93 (print_insn_powerpc) <insn, value>: Update type.
94 Use PPC_INT_FMT for printing instructions and operands.
95 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
96 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
97 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
98 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
99 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
100 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
101 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
102 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
103 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
104 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
105 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
106 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
107 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
108 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
109 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
110 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
111 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
112 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
113 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
114 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
115 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
116 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
117 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
118 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
119 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
120 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
121 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
122 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
123 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
124 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
125 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
126 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
127 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
128 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
129 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
130 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
131 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
132
133 2017-11-29 Jan Beulich <jbeulich@suse.com>
134
135 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
136 New.
137 (output_cpu_flags): Update active_cpu_flags.
138 (process_i386_opcode_modifier): Update active_isstring.
139 (output_operand_type): Rename "macro" parameter to "stage",
140 changing its type.
141 (process_i386_operand_type): Likewise. Track presence of
142 BaseIndex and emit DispN accordingly.
143 (output_i386_opcode, process_i386_registers,
144 process_i386_initializers): Adjust calls to
145 process_i386_operand_type() for its changed parameter type.
146 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
147 all insns operands having BaseIndex set.
148 * i386-tbl.h: Re-generate.
149
150 2017-11-29 Jan Beulich <jbeulich@suse.com>
151
152 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
153 entry.
154 (operand_types): Remove Vec_Disp8 entry.
155 * i386-opc.h (Vec_Disp8): Delete.
156 (union i386_operand_type): Remove vec_disp8.
157 (i386-opc.tbl): Remove Vec_Disp8.
158 * i386-init.h, i386-tbl.h: Re-generate.
159
160 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
161
162 * po/Make-in (datadir): Define as @datadir@.
163 (localedir): Define as @localedir@.
164 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
165
166 2017-11-27 Nick Clifton <nickc@redhat.com>
167
168 * po/zh_CN.po: Updated simplified Chinese translation.
169
170 2017-11-24 Jan Beulich <jbeulich@suse.com>
171
172 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
173 "df" groups.
174
175 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
176
177 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
178 * i386-tbl.h: Regenerate.
179
180 2017-11-23 Jan Beulich <jbeulich@suse.com>
181
182 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
183 the 16-bit addressing case.
184
185 2017-11-23 Jan Beulich <jbeulich@suse.com>
186
187 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
188 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
189 * i386-opc.tbl (ud1, ud2b): Add operands.
190 (ud0): New.
191 * i386-tbl.h: Re-generate.
192
193 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
194
195 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
196 * i386-tbl.h: Regenerate.
197
198 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
199
200 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
201 * i386-tbl.h: Regenerate.
202
203 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
204
205 *arc-opc (insert_rhv2): Check h-regs range.
206
207 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
208
209 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
210 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
211
212 2017-11-16 Tamar Christina <tamar.christina@arm.com>
213
214 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
215 and AARCH64_FEATURE_F16.
216
217 2017-11-16 Tamar Christina <tamar.christina@arm.com>
218
219 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
220 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
221 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
222 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
223 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
224 (ldapur, ldapursw, stlur): New.
225 * aarch64-dis-2.c: Regenerate.
226
227 2017-11-16 Jan Beulich <jbeulich@suse.com>
228
229 (get_valid_dis386): Never flag bad opcode when
230 vex.register_specifier is beyond 7. Always store all four
231 bits of it. Move 16-/32-bit override in EVEX handling after
232 all to be overridden bits have been set.
233 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
234 Use rex to determine GPR register set.
235 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
236 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
237
238 2017-11-15 Jan Beulich <jbeulich@suse.com>
239
240 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
241 determine GPR register set.
242
243 2017-11-15 Jan Beulich <jbeulich@suse.com>
244
245 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
246 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
247 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
248 pass.
249 (OP_REG_VexI4): Drop low 4 bits check.
250
251 2017-11-15 Jan Beulich <jbeulich@suse.com>
252
253 * i386-reg.tbl (axl): Remove Acc and Byte.
254 * i386-tbl.h: Re-generate.
255
256 2017-11-14 Jan Beulich <jbeulich@suse.com>
257
258 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
259 (vex_len_table): Use VPCOM.
260
261 2017-11-14 Jan Beulich <jbeulich@suse.com>
262
263 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
264 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
265 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
266 vpcmpw): Move up.
267 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
268 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
269 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
270 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
271 vpcmpnltuw): New.
272 * i386-tbl.h: Re-generate.
273
274 2017-11-14 Jan Beulich <jbeulich@suse.com>
275
276 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
277 smov, ssca, stos, ssto, xlat): Drop Disp*.
278 * i386-tbl.h: Re-generate.
279
280 2017-11-13 Jan Beulich <jbeulich@suse.com>
281
282 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
283 xsaveopt64): Add No_qSuf.
284 * i386-tbl.h: Re-generate.
285
286 2017-11-09 Tamar Christina <tamar.christina@arm.com>
287
288 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
289 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
290 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
291 sder32_el2, vncr_el2.
292 (aarch64_sys_reg_supported_p): Likewise.
293 (aarch64_pstatefields): Add dit register.
294 (aarch64_pstatefield_supported_p): Likewise.
295 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
296 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
297 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
298 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
299 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
300 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
301 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
302
303 2017-11-09 Tamar Christina <tamar.christina@arm.com>
304
305 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
306 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
307 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
308 (QL_STLW, QL_STLX): New.
309
310 2017-11-09 Tamar Christina <tamar.christina@arm.com>
311
312 * aarch64-asm.h (ins_addr_offset): New.
313 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
314 (aarch64_ins_addr_offset): New.
315 * aarch64-asm-2.c: Regenerate.
316 * aarch64-dis.h (ext_addr_offset): New.
317 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
318 (aarch64_ext_addr_offset): New.
319 * aarch64-dis-2.c: Regenerate.
320 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
321 FLD_imm4_2 and FLD_SM3_imm2.
322 * aarch64-opc.c (fields): Add FLD_imm6_2,
323 FLD_imm4_2 and FLD_SM3_imm2.
324 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
325 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
326 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
327 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
328 * aarch64-tbl.h
329 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
330
331 2017-11-09 Tamar Christina <tamar.christina@arm.com>
332
333 * aarch64-tbl.h
334 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
335 (aarch64_feature_sm4, aarch64_feature_sha3): New.
336 (aarch64_feature_fp_16_v8_2): New.
337 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
338 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
339 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
340
341 2017-11-08 Tamar Christina <tamar.christina@arm.com>
342
343 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
344 (aarch64_feature_sha2, aarch64_feature_aes): New.
345 (SHA2, AES): New.
346 (AES_INSN, SHA2_INSN): New.
347 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
348 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
349 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
350 Change to SHA2_INS.
351
352 2017-11-08 Jiong Wang <jiong.wang@arm.com>
353 Tamar Christina <tamar.christina@arm.com>
354
355 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
356 FP16 instructions, including vfmal.f16 and vfmsl.f16.
357
358 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
359
360 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
361
362 2017-11-07 Alan Modra <amodra@gmail.com>
363
364 * opintl.h: Formatting, comment fixes.
365 (gettext, ngettext): Redefine when ENABLE_NLS.
366 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
367 (_): Define using gettext.
368 (textdomain, bindtextdomain): Use safer "do nothing".
369
370 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
371
372 * arc-dis.c (print_hex): New variable.
373 (parse_option): Check for hex option.
374 (print_insn_arc): Use hexadecimal representation for short
375 immediate values when requested.
376 (print_arc_disassembler_options): Add hex option to the list.
377
378 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
379
380 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
381 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
382 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
383 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
384 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
385 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
386 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
387 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
388 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
389 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
390 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
391 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
392 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
393 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
394 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
395 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
396 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
397 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
398 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
399 Changed opcodes.
400 (prealloc, prefetch*): Place them before ld instruction.
401 * arc-opc.c (skip_this_opcode): Add ARITH class.
402
403 2017-10-25 Alan Modra <amodra@gmail.com>
404
405 PR 22348
406 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
407 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
408 (imm4flag, size_changed): Likewise.
409 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
410 (words, allWords, processing_argument_number): Likewise.
411 (cst4flag, size_changed): Likewise.
412 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
413 (crx_cst4_maps): Rename from cst4_maps.
414 (crx_no_op_insn): Rename from no_op_insn.
415
416 2017-10-24 Andrew Waterman <andrew@sifive.com>
417
418 * riscv-opc.c (match_c_addi16sp) : New function.
419 (match_c_addi4spn): New function.
420 (match_c_lui): Don't allow 0-immediate encodings.
421 (riscv_opcodes) <addi>: Use the above functions.
422 <add>: Likewise.
423 <c.addi4spn>: Likewise.
424 <c.addi16sp>: Likewise.
425
426 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
427
428 * i386-init.h: Regenerate
429 * i386-tbl.h: Likewise
430
431 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
432
433 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
434 (enum): Add EVEX_W_0F3854_P_2.
435 * i386-dis-evex.h (evex_table): Updated.
436 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
437 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
438 (cpu_flags): Add CpuAVX512_BITALG.
439 * i386-opc.h (enum): Add CpuAVX512_BITALG.
440 (i386_cpu_flags): Add cpuavx512_bitalg..
441 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
442 * i386-init.h: Regenerate.
443 * i386-tbl.h: Likewise.
444
445 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
446
447 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
448 * i386-dis-evex.h (evex_table): Updated.
449 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
450 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
451 (cpu_flags): Add CpuAVX512_VNNI.
452 * i386-opc.h (enum): Add CpuAVX512_VNNI.
453 (i386_cpu_flags): Add cpuavx512_vnni.
454 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
455 * i386-init.h: Regenerate.
456 * i386-tbl.h: Likewise.
457
458 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
459
460 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
461 (enum): Remove VEX_LEN_0F3A44_P_2.
462 (vex_len_table): Ditto.
463 (enum): Remove VEX_W_0F3A44_P_2.
464 (vew_w_table): Ditto.
465 (prefix_table): Adjust instructions (see prefixes above).
466 * i386-dis-evex.h (evex_table):
467 Add new instructions (see prefixes above).
468 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
469 (bitfield_cpu_flags): Ditto.
470 * i386-opc.h (enum): Ditto.
471 (i386_cpu_flags): Ditto.
472 (CpuUnused): Comment out to avoid zero-width field problem.
473 * i386-opc.tbl (vpclmulqdq): New instruction.
474 * i386-init.h: Regenerate.
475 * i386-tbl.h: Ditto.
476
477 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
478
479 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
480 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
481 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
482 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
483 (vex_len_table): Ditto.
484 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
485 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
486 (vew_w_table): Ditto.
487 (prefix_table): Adjust instructions (see prefixes above).
488 * i386-dis-evex.h (evex_table):
489 Add new instructions (see prefixes above).
490 * i386-gen.c (cpu_flag_init): Add VAES.
491 (bitfield_cpu_flags): Ditto.
492 * i386-opc.h (enum): Ditto.
493 (i386_cpu_flags): Ditto.
494 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
495 * i386-init.h: Regenerate.
496 * i386-tbl.h: Ditto.
497
498 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
499
500 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
501 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
502 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
503 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
504 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
505 (prefix_table): Updated (see prefixes above).
506 (three_byte_table): Likewise.
507 (vex_w_table): Likewise.
508 * i386-dis-evex.h: Likewise.
509 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
510 (cpu_flags): Add CpuGFNI.
511 * i386-opc.h (enum): Add CpuGFNI.
512 (i386_cpu_flags): Add cpugfni.
513 * i386-opc.tbl: Add Intel GFNI instructions.
514 * i386-init.h: Regenerate.
515 * i386-tbl.h: Likewise.
516
517 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
518
519 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
520 Define EXbScalar and EXwScalar for OP_EX.
521 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
522 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
523 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
524 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
525 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
526 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
527 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
528 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
529 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
530 (OP_E_memory): Likewise.
531 * i386-dis-evex.h: Updated.
532 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
533 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
534 (cpu_flags): Add CpuAVX512_VBMI2.
535 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
536 (i386_cpu_flags): Add cpuavx512_vbmi2.
537 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
538 * i386-init.h: Regenerate.
539 * i386-tbl.h: Likewise.
540
541 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
542
543 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
544
545 2017-10-12 James Bowman <james.bowman@ftdichip.com>
546
547 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
548 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
549 K15. Add jmpix pattern.
550
551 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
552
553 * s390-opc.txt (prno, tpei, irbm): New instructions added.
554
555 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
556
557 * s390-opc.c (INSTR_SI_RD): New macro.
558 (INSTR_S_RD): Adjust example instruction.
559 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
560 SI_RD.
561
562 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
563
564 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
565 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
566 VLE multimple load/store instructions. Old e_ldm* variants are
567 kept as aliases.
568 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
569
570 2017-09-27 Nick Clifton <nickc@redhat.com>
571
572 PR 22179
573 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
574 names for the fmv.x.s and fmv.s.x instructions respectively.
575
576 2017-09-26 do <do@nerilex.org>
577
578 PR 22123
579 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
580 be used on CPUs that have emacs support.
581
582 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
583
584 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
585
586 2017-09-09 Kamil Rytarowski <n54@gmx.com>
587
588 * nds32-asm.c: Rename __BIT() to N32_BIT().
589 * nds32-asm.h: Likewise.
590 * nds32-dis.c: Likewise.
591
592 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
593
594 * i386-dis.c (last_active_prefix): Removed.
595 (ckprefix): Don't set last_active_prefix.
596 (NOTRACK_Fixup): Don't check last_active_prefix.
597
598 2017-08-31 Nick Clifton <nickc@redhat.com>
599
600 * po/fr.po: Updated French translation.
601
602 2017-08-31 James Bowman <james.bowman@ftdichip.com>
603
604 * ft32-dis.c (print_insn_ft32): Correct display of non-address
605 fields.
606
607 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
608 Edmar Wienskoski <edmar.wienskoski@nxp.com>
609
610 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
611 PPC_OPCODE_EFS2 flag to "e200z4" entry.
612 New entries efs2 and spe2.
613 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
614 (SPE2_OPCD_SEGS): New macro.
615 (spe2_opcd_indices): New.
616 (disassemble_init_powerpc): Handle SPE2 opcodes.
617 (lookup_spe2): New function.
618 (print_insn_powerpc): call lookup_spe2.
619 * ppc-opc.c (insert_evuimm1_ex0): New function.
620 (extract_evuimm1_ex0): Likewise.
621 (insert_evuimm_lt8): Likewise.
622 (extract_evuimm_lt8): Likewise.
623 (insert_off_spe2): Likewise.
624 (extract_off_spe2): Likewise.
625 (insert_Ddd): Likewise.
626 (extract_Ddd): Likewise.
627 (DD): New operand.
628 (EVUIMM_LT8): Likewise.
629 (EVUIMM_LT16): Adjust.
630 (MMMM): New operand.
631 (EVUIMM_1): Likewise.
632 (EVUIMM_1_EX0): Likewise.
633 (EVUIMM_2): Adjust.
634 (NNN): New operand.
635 (VX_OFF_SPE2): Likewise.
636 (BBB): Likewise.
637 (DDD): Likewise.
638 (VX_MASK_DDD): New mask.
639 (HH): New operand.
640 (VX_RA_CONST): New macro.
641 (VX_RA_CONST_MASK): Likewise.
642 (VX_RB_CONST): Likewise.
643 (VX_RB_CONST_MASK): Likewise.
644 (VX_OFF_SPE2_MASK): Likewise.
645 (VX_SPE_CRFD): Likewise.
646 (VX_SPE_CRFD_MASK VX): Likewise.
647 (VX_SPE2_CLR): Likewise.
648 (VX_SPE2_CLR_MASK): Likewise.
649 (VX_SPE2_SPLATB): Likewise.
650 (VX_SPE2_SPLATB_MASK): Likewise.
651 (VX_SPE2_OCTET): Likewise.
652 (VX_SPE2_OCTET_MASK): Likewise.
653 (VX_SPE2_DDHH): Likewise.
654 (VX_SPE2_DDHH_MASK): Likewise.
655 (VX_SPE2_HH): Likewise.
656 (VX_SPE2_HH_MASK): Likewise.
657 (VX_SPE2_EVMAR): Likewise.
658 (VX_SPE2_EVMAR_MASK): Likewise.
659 (PPCSPE2): Likewise.
660 (PPCEFS2): Likewise.
661 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
662 (powerpc_macros): Map old SPE instructions have new names
663 with the same opcodes. Add SPE2 instructions which just are
664 mapped to SPE2.
665 (spe2_opcodes): Add SPE2 opcodes.
666
667 2017-08-23 Alan Modra <amodra@gmail.com>
668
669 * ppc-opc.c: Formatting and comment fixes. Move insert and
670 extract functions earlier, deleting forward declarations.
671 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
672 RA_MASK.
673
674 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
675
676 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
677
678 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
679 Edmar Wienskoski <edmar.wienskoski@nxp.com>
680
681 * ppc-opc.c (insert_evuimm2_ex0): New function.
682 (extract_evuimm2_ex0): Likewise.
683 (insert_evuimm4_ex0): Likewise.
684 (extract_evuimm4_ex0): Likewise.
685 (insert_evuimm8_ex0): Likewise.
686 (extract_evuimm8_ex0): Likewise.
687 (insert_evuimm_lt16): Likewise.
688 (extract_evuimm_lt16): Likewise.
689 (insert_rD_rS_even): Likewise.
690 (extract_rD_rS_even): Likewise.
691 (insert_off_lsp): Likewise.
692 (extract_off_lsp): Likewise.
693 (RD_EVEN): New operand.
694 (RS_EVEN): Likewise.
695 (RSQ): Adjust.
696 (EVUIMM_LT16): New operand.
697 (HTM_SI): Adjust.
698 (EVUIMM_2_EX0): New operand.
699 (EVUIMM_4): Adjust.
700 (EVUIMM_4_EX0): New operand.
701 (EVUIMM_8): Adjust.
702 (EVUIMM_8_EX0): New operand.
703 (WS): Adjust.
704 (VX_OFF): New operand.
705 (VX_LSP): New macro.
706 (VX_LSP_MASK): Likewise.
707 (VX_LSP_OFF_MASK): Likewise.
708 (PPC_OPCODE_LSP): Likewise.
709 (vle_opcodes): Add LSP opcodes.
710 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
711
712 2017-08-09 Jiong Wang <jiong.wang@arm.com>
713
714 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
715 register operands in CRC instructions.
716 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
717 comments.
718
719 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
720
721 * disassemble.c (disassembler): Mark big and mach with
722 ATTRIBUTE_UNUSED.
723
724 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
725
726 * disassemble.c (disassembler): Remove arch/mach/endian
727 assertions.
728
729 2017-07-25 Nick Clifton <nickc@redhat.com>
730
731 PR 21739
732 * arc-opc.c (insert_rhv2): Use lower case first letter in error
733 message.
734 (insert_r0): Likewise.
735 (insert_r1): Likewise.
736 (insert_r2): Likewise.
737 (insert_r3): Likewise.
738 (insert_sp): Likewise.
739 (insert_gp): Likewise.
740 (insert_pcl): Likewise.
741 (insert_blink): Likewise.
742 (insert_ilink1): Likewise.
743 (insert_ilink2): Likewise.
744 (insert_ras): Likewise.
745 (insert_rbs): Likewise.
746 (insert_rcs): Likewise.
747 (insert_simm3s): Likewise.
748 (insert_rrange): Likewise.
749 (insert_r13el): Likewise.
750 (insert_fpel): Likewise.
751 (insert_blinkel): Likewise.
752 (insert_pclel): Likewise.
753 (insert_nps_bitop_size_2b): Likewise.
754 (insert_nps_imm_offset): Likewise.
755 (insert_nps_imm_entry): Likewise.
756 (insert_nps_size_16bit): Likewise.
757 (insert_nps_##NAME##_pos): Likewise.
758 (insert_nps_##NAME): Likewise.
759 (insert_nps_bitop_ins_ext): Likewise.
760 (insert_nps_##NAME): Likewise.
761 (insert_nps_min_hofs): Likewise.
762 (insert_nps_##NAME): Likewise.
763 (insert_nps_rbdouble_64): Likewise.
764 (insert_nps_misc_imm_offset): Likewise.
765 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
766 option description.
767
768 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
769 Jiong Wang <jiong.wang@arm.com>
770
771 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
772 correct the print.
773 * aarch64-dis-2.c: Regenerated.
774
775 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
776
777 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
778 table.
779
780 2017-07-20 Nick Clifton <nickc@redhat.com>
781
782 * po/de.po: Updated German translation.
783
784 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
785
786 * arc-regs.h (sec_stat): New aux register.
787 (aux_kernel_sp): Likewise.
788 (aux_sec_u_sp): Likewise.
789 (aux_sec_k_sp): Likewise.
790 (sec_vecbase_build): Likewise.
791 (nsc_table_top): Likewise.
792 (nsc_table_base): Likewise.
793 (ersec_stat): Likewise.
794 (aux_sec_except): Likewise.
795
796 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
797
798 * arc-opc.c (extract_uimm12_20): New function.
799 (UIMM12_20): New operand.
800 (SIMM3_5_S): Adjust.
801 * arc-tbl.h (sjli): Add new instruction.
802
803 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
804 John Eric Martin <John.Martin@emmicro-us.com>
805
806 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
807 (UIMM3_23): Adjust accordingly.
808 * arc-regs.h: Add/correct jli_base register.
809 * arc-tbl.h (jli_s): Likewise.
810
811 2017-07-18 Nick Clifton <nickc@redhat.com>
812
813 PR 21775
814 * aarch64-opc.c: Fix spelling typos.
815 * i386-dis.c: Likewise.
816
817 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
818
819 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
820 max_addr_offset and octets variables to size_t.
821
822 2017-07-12 Alan Modra <amodra@gmail.com>
823
824 * po/da.po: Update from translationproject.org/latest/opcodes/.
825 * po/de.po: Likewise.
826 * po/es.po: Likewise.
827 * po/fi.po: Likewise.
828 * po/fr.po: Likewise.
829 * po/id.po: Likewise.
830 * po/it.po: Likewise.
831 * po/nl.po: Likewise.
832 * po/pt_BR.po: Likewise.
833 * po/ro.po: Likewise.
834 * po/sv.po: Likewise.
835 * po/tr.po: Likewise.
836 * po/uk.po: Likewise.
837 * po/vi.po: Likewise.
838 * po/zh_CN.po: Likewise.
839
840 2017-07-11 Yao Qi <yao.qi@linaro.org>
841 Alan Modra <amodra@gmail.com>
842
843 * cgen.sh: Mark generated files read-only.
844 * epiphany-asm.c: Regenerate.
845 * epiphany-desc.c: Regenerate.
846 * epiphany-desc.h: Regenerate.
847 * epiphany-dis.c: Regenerate.
848 * epiphany-ibld.c: Regenerate.
849 * epiphany-opc.c: Regenerate.
850 * epiphany-opc.h: Regenerate.
851 * fr30-asm.c: Regenerate.
852 * fr30-desc.c: Regenerate.
853 * fr30-desc.h: Regenerate.
854 * fr30-dis.c: Regenerate.
855 * fr30-ibld.c: Regenerate.
856 * fr30-opc.c: Regenerate.
857 * fr30-opc.h: Regenerate.
858 * frv-asm.c: Regenerate.
859 * frv-desc.c: Regenerate.
860 * frv-desc.h: Regenerate.
861 * frv-dis.c: Regenerate.
862 * frv-ibld.c: Regenerate.
863 * frv-opc.c: Regenerate.
864 * frv-opc.h: Regenerate.
865 * ip2k-asm.c: Regenerate.
866 * ip2k-desc.c: Regenerate.
867 * ip2k-desc.h: Regenerate.
868 * ip2k-dis.c: Regenerate.
869 * ip2k-ibld.c: Regenerate.
870 * ip2k-opc.c: Regenerate.
871 * ip2k-opc.h: Regenerate.
872 * iq2000-asm.c: Regenerate.
873 * iq2000-desc.c: Regenerate.
874 * iq2000-desc.h: Regenerate.
875 * iq2000-dis.c: Regenerate.
876 * iq2000-ibld.c: Regenerate.
877 * iq2000-opc.c: Regenerate.
878 * iq2000-opc.h: Regenerate.
879 * lm32-asm.c: Regenerate.
880 * lm32-desc.c: Regenerate.
881 * lm32-desc.h: Regenerate.
882 * lm32-dis.c: Regenerate.
883 * lm32-ibld.c: Regenerate.
884 * lm32-opc.c: Regenerate.
885 * lm32-opc.h: Regenerate.
886 * lm32-opinst.c: Regenerate.
887 * m32c-asm.c: Regenerate.
888 * m32c-desc.c: Regenerate.
889 * m32c-desc.h: Regenerate.
890 * m32c-dis.c: Regenerate.
891 * m32c-ibld.c: Regenerate.
892 * m32c-opc.c: Regenerate.
893 * m32c-opc.h: Regenerate.
894 * m32r-asm.c: Regenerate.
895 * m32r-desc.c: Regenerate.
896 * m32r-desc.h: Regenerate.
897 * m32r-dis.c: Regenerate.
898 * m32r-ibld.c: Regenerate.
899 * m32r-opc.c: Regenerate.
900 * m32r-opc.h: Regenerate.
901 * m32r-opinst.c: Regenerate.
902 * mep-asm.c: Regenerate.
903 * mep-desc.c: Regenerate.
904 * mep-desc.h: Regenerate.
905 * mep-dis.c: Regenerate.
906 * mep-ibld.c: Regenerate.
907 * mep-opc.c: Regenerate.
908 * mep-opc.h: Regenerate.
909 * mt-asm.c: Regenerate.
910 * mt-desc.c: Regenerate.
911 * mt-desc.h: Regenerate.
912 * mt-dis.c: Regenerate.
913 * mt-ibld.c: Regenerate.
914 * mt-opc.c: Regenerate.
915 * mt-opc.h: Regenerate.
916 * or1k-asm.c: Regenerate.
917 * or1k-desc.c: Regenerate.
918 * or1k-desc.h: Regenerate.
919 * or1k-dis.c: Regenerate.
920 * or1k-ibld.c: Regenerate.
921 * or1k-opc.c: Regenerate.
922 * or1k-opc.h: Regenerate.
923 * or1k-opinst.c: Regenerate.
924 * xc16x-asm.c: Regenerate.
925 * xc16x-desc.c: Regenerate.
926 * xc16x-desc.h: Regenerate.
927 * xc16x-dis.c: Regenerate.
928 * xc16x-ibld.c: Regenerate.
929 * xc16x-opc.c: Regenerate.
930 * xc16x-opc.h: Regenerate.
931 * xstormy16-asm.c: Regenerate.
932 * xstormy16-desc.c: Regenerate.
933 * xstormy16-desc.h: Regenerate.
934 * xstormy16-dis.c: Regenerate.
935 * xstormy16-ibld.c: Regenerate.
936 * xstormy16-opc.c: Regenerate.
937 * xstormy16-opc.h: Regenerate.
938
939 2017-07-07 Alan Modra <amodra@gmail.com>
940
941 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
942 * m32c-dis.c: Regenerate.
943 * mep-dis.c: Regenerate.
944
945 2017-07-05 Borislav Petkov <bp@suse.de>
946
947 * i386-dis.c: Enable ModRM.reg /6 aliases.
948
949 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
950
951 * opcodes/arm-dis.c: Support MVFR2 in disassembly
952 with vmrs and vmsr.
953
954 2017-07-04 Tristan Gingold <gingold@adacore.com>
955
956 * configure: Regenerate.
957
958 2017-07-03 Tristan Gingold <gingold@adacore.com>
959
960 * po/opcodes.pot: Regenerate.
961
962 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
963
964 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
965 entries to the MSA ASE instruction block.
966
967 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
968 Maciej W. Rozycki <macro@imgtec.com>
969
970 * micromips-opc.c (XPA, XPAVZ): New macros.
971 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
972 "mthgc0".
973
974 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
975 Maciej W. Rozycki <macro@imgtec.com>
976
977 * micromips-opc.c (I36): New macro.
978 (micromips_opcodes): Add "eretnc".
979
980 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
981 Andrew Bennett <andrew.bennett@imgtec.com>
982
983 * mips-dis.c (mips_calculate_combination_ases): Handle the
984 ASE_XPA_VIRT flag.
985 (parse_mips_ase_option): New function.
986 (parse_mips_dis_option): Factor out ASE option handling to the
987 new function. Call `mips_calculate_combination_ases'.
988 * mips-opc.c (XPAVZ): New macro.
989 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
990 "mfhgc0", "mthc0" and "mthgc0".
991
992 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
993
994 * mips-dis.c (mips_calculate_combination_ases): New function.
995 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
996 calculation to the new function.
997 (set_default_mips_dis_options): Call the new function.
998
999 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1000
1001 * arc-dis.c (parse_disassembler_options): Use
1002 FOR_EACH_DISASSEMBLER_OPTION.
1003
1004 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1005
1006 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
1007 disassembler option strings.
1008 (parse_cpu_option): Likewise.
1009
1010 2017-06-28 Tamar Christina <tamar.christina@arm.com>
1011
1012 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
1013 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
1014 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
1015 (aarch64_feature_dotprod, DOT_INSN): New.
1016 (udot, sdot): New.
1017 * aarch64-dis-2.c: Regenerated.
1018
1019 2017-06-28 Jiong Wang <jiong.wang@arm.com>
1020
1021 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1022
1023 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
1024 Matthew Fortune <matthew.fortune@imgtec.com>
1025 Andrew Bennett <andrew.bennett@imgtec.com>
1026
1027 * mips-formats.h (INT_BIAS): New macro.
1028 (INT_ADJ): Redefine in INT_BIAS terms.
1029 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1030 (mips_print_save_restore): New function.
1031 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1032 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1033 call.
1034 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1035 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1036 OP_SAVE_RESTORE_LIST handling, factored out from here.
1037 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1038 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1039 (mips_builtin_opcodes): Add "restore" and "save" entries.
1040 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1041 (IAMR2): New macro.
1042 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1043
1044 2017-06-23 Andrew Waterman <andrew@sifive.com>
1045
1046 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1047 alias; do not mark SLTI instruction as an alias.
1048
1049 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1050
1051 * i386-dis.c (RM_0FAE_REG_5): Removed.
1052 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1053 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1054 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1055 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1056 PREFIX_MOD_3_0F01_REG_5_RM_0.
1057 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1058 PREFIX_MOD_3_0FAE_REG_5.
1059 (mod_table): Update MOD_0FAE_REG_5.
1060 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1061 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1062 * i386-tbl.h: Regenerated.
1063
1064 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1065
1066 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1067 * i386-opc.tbl: Likewise.
1068 * i386-tbl.h: Regenerated.
1069
1070 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1071
1072 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1073 and "jmp{&|}".
1074 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1075 prefix.
1076
1077 2017-06-19 Nick Clifton <nickc@redhat.com>
1078
1079 PR binutils/21614
1080 * score-dis.c (score_opcodes): Add sentinel.
1081
1082 2017-06-16 Alan Modra <amodra@gmail.com>
1083
1084 * rx-decode.c: Regenerate.
1085
1086 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1087
1088 PR binutils/21594
1089 * i386-dis.c (OP_E_register): Check valid bnd register.
1090 (OP_G): Likewise.
1091
1092 2017-06-15 Nick Clifton <nickc@redhat.com>
1093
1094 PR binutils/21595
1095 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1096 range value.
1097
1098 2017-06-15 Nick Clifton <nickc@redhat.com>
1099
1100 PR binutils/21588
1101 * rl78-decode.opc (OP_BUF_LEN): Define.
1102 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1103 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1104 array.
1105 * rl78-decode.c: Regenerate.
1106
1107 2017-06-15 Nick Clifton <nickc@redhat.com>
1108
1109 PR binutils/21586
1110 * bfin-dis.c (gregs): Clip index to prevent overflow.
1111 (regs): Likewise.
1112 (regs_lo): Likewise.
1113 (regs_hi): Likewise.
1114
1115 2017-06-14 Nick Clifton <nickc@redhat.com>
1116
1117 PR binutils/21576
1118 * score7-dis.c (score_opcodes): Add sentinel.
1119
1120 2017-06-14 Yao Qi <yao.qi@linaro.org>
1121
1122 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1123 * arm-dis.c: Likewise.
1124 * ia64-dis.c: Likewise.
1125 * mips-dis.c: Likewise.
1126 * spu-dis.c: Likewise.
1127 * disassemble.h (print_insn_aarch64): New declaration, moved from
1128 include/dis-asm.h.
1129 (print_insn_big_arm, print_insn_big_mips): Likewise.
1130 (print_insn_i386, print_insn_ia64): Likewise.
1131 (print_insn_little_arm, print_insn_little_mips): Likewise.
1132
1133 2017-06-14 Nick Clifton <nickc@redhat.com>
1134
1135 PR binutils/21587
1136 * rx-decode.opc: Include libiberty.h
1137 (GET_SCALE): New macro - validates access to SCALE array.
1138 (GET_PSCALE): New macro - validates access to PSCALE array.
1139 (DIs, SIs, S2Is, rx_disp): Use new macros.
1140 * rx-decode.c: Regenerate.
1141
1142 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1143
1144 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1145
1146 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1147
1148 * arc-dis.c (enforced_isa_mask): Declare.
1149 (cpu_types): Likewise.
1150 (parse_cpu_option): New function.
1151 (parse_disassembler_options): Use it.
1152 (print_insn_arc): Use enforced_isa_mask.
1153 (print_arc_disassembler_options): Document new options.
1154
1155 2017-05-24 Yao Qi <yao.qi@linaro.org>
1156
1157 * alpha-dis.c: Include disassemble.h, don't include
1158 dis-asm.h.
1159 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1160 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1161 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1162 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1163 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1164 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1165 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1166 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1167 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1168 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1169 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1170 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1171 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1172 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1173 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1174 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1175 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1176 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1177 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1178 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1179 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1180 * z80-dis.c, z8k-dis.c: Likewise.
1181 * disassemble.h: New file.
1182
1183 2017-05-24 Yao Qi <yao.qi@linaro.org>
1184
1185 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1186 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1187
1188 2017-05-24 Yao Qi <yao.qi@linaro.org>
1189
1190 * disassemble.c (disassembler): Add arguments a, big and mach.
1191 Use them.
1192
1193 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1194
1195 * i386-dis.c (NOTRACK_Fixup): New.
1196 (NOTRACK): Likewise.
1197 (NOTRACK_PREFIX): Likewise.
1198 (last_active_prefix): Likewise.
1199 (reg_table): Use NOTRACK on indirect call and jmp.
1200 (ckprefix): Set last_active_prefix.
1201 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1202 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1203 * i386-opc.h (NoTrackPrefixOk): New.
1204 (i386_opcode_modifier): Add notrackprefixok.
1205 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1206 Add notrack.
1207 * i386-tbl.h: Regenerated.
1208
1209 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1210
1211 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1212 (X_IMM2): Define.
1213 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1214 bfd_mach_sparc_v9m8.
1215 (print_insn_sparc): Handle new operand types.
1216 * sparc-opc.c (MASK_M8): Define.
1217 (v6): Add MASK_M8.
1218 (v6notlet): Likewise.
1219 (v7): Likewise.
1220 (v8): Likewise.
1221 (v9): Likewise.
1222 (v9a): Likewise.
1223 (v9b): Likewise.
1224 (v9c): Likewise.
1225 (v9d): Likewise.
1226 (v9e): Likewise.
1227 (v9v): Likewise.
1228 (v9m): Likewise.
1229 (v9andleon): Likewise.
1230 (m8): Define.
1231 (HWS_VM8): Define.
1232 (HWS2_VM8): Likewise.
1233 (sparc_opcode_archs): Add entry for "m8".
1234 (sparc_opcodes): Add OSA2017 and M8 instructions
1235 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1236 fpx{ll,ra,rl}64x,
1237 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1238 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1239 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1240 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1241 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1242 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1243 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1244 ASI_CORE_SELECT_COMMIT_NHT.
1245
1246 2017-05-18 Alan Modra <amodra@gmail.com>
1247
1248 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1249 * aarch64-dis.c: Likewise.
1250 * aarch64-gen.c: Likewise.
1251 * aarch64-opc.c: Likewise.
1252
1253 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1254 Matthew Fortune <matthew.fortune@imgtec.com>
1255
1256 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1257 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1258 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1259 (print_insn_arg) <OP_REG28>: Add handler.
1260 (validate_insn_args) <OP_REG28>: Handle.
1261 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1262 32-bit encoding and 9-bit immediates.
1263 (print_insn_mips16): Handle MIPS16 instructions that require
1264 32-bit encoding and MFC0/MTC0 operand decoding.
1265 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1266 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1267 (RD_C0, WR_C0, E2, E2MT): New macros.
1268 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1269 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1270 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1271 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1272 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1273 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1274 instructions, "swl", "swr", "sync" and its "sync_acquire",
1275 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1276 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1277 regular/extended entries for original MIPS16 ISA revision
1278 instructions whose extended forms are subdecoded in the MIPS16e2
1279 ISA revision: "li", "sll" and "srl".
1280
1281 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1282
1283 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1284 reference in CP0 move operand decoding.
1285
1286 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1287
1288 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1289 type to hexadecimal.
1290 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1291
1292 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1293
1294 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1295 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1296 "sync_rmb" and "sync_wmb" as aliases.
1297 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1298 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1299
1300 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1301
1302 * arc-dis.c (parse_option): Update quarkse_em option..
1303 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1304 QUARKSE1.
1305 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1306
1307 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1308
1309 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1310
1311 2017-05-01 Michael Clark <michaeljclark@mac.com>
1312
1313 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1314 register.
1315
1316 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1317
1318 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1319 and branches and not synthetic data instructions.
1320
1321 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1322
1323 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1324
1325 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1326
1327 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1328 * arc-opc.c (insert_r13el): New function.
1329 (R13_EL): Define.
1330 * arc-tbl.h: Add new enter/leave variants.
1331
1332 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1333
1334 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1335
1336 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1337
1338 * mips-dis.c (print_mips_disassembler_options): Add
1339 `no-aliases'.
1340
1341 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1342
1343 * mips16-opc.c (AL): New macro.
1344 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1345 of "ld" and "lw" as aliases.
1346
1347 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1348
1349 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1350 arguments.
1351
1352 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1353 Alan Modra <amodra@gmail.com>
1354
1355 * ppc-opc.c (ELEV): Define.
1356 (vle_opcodes): Add se_rfgi and e_sc.
1357 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1358 for E200Z4.
1359
1360 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1361
1362 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1363
1364 2017-04-21 Nick Clifton <nickc@redhat.com>
1365
1366 PR binutils/21380
1367 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1368 LD3R and LD4R.
1369
1370 2017-04-13 Alan Modra <amodra@gmail.com>
1371
1372 * epiphany-desc.c: Regenerate.
1373 * fr30-desc.c: Regenerate.
1374 * frv-desc.c: Regenerate.
1375 * ip2k-desc.c: Regenerate.
1376 * iq2000-desc.c: Regenerate.
1377 * lm32-desc.c: Regenerate.
1378 * m32c-desc.c: Regenerate.
1379 * m32r-desc.c: Regenerate.
1380 * mep-desc.c: Regenerate.
1381 * mt-desc.c: Regenerate.
1382 * or1k-desc.c: Regenerate.
1383 * xc16x-desc.c: Regenerate.
1384 * xstormy16-desc.c: Regenerate.
1385
1386 2017-04-11 Alan Modra <amodra@gmail.com>
1387
1388 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1389 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1390 PPC_OPCODE_TMR for e6500.
1391 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1392 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1393 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1394 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1395 (PPCHTM): Define as PPC_OPCODE_POWER8.
1396 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1397
1398 2017-04-10 Alan Modra <amodra@gmail.com>
1399
1400 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1401 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1402 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1403 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1404
1405 2017-04-09 Pip Cet <pipcet@gmail.com>
1406
1407 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1408 appropriate floating-point precision directly.
1409
1410 2017-04-07 Alan Modra <amodra@gmail.com>
1411
1412 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1413 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1414 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1415 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1416 vector instructions with E6500 not PPCVEC2.
1417
1418 2017-04-06 Pip Cet <pipcet@gmail.com>
1419
1420 * Makefile.am: Add wasm32-dis.c.
1421 * configure.ac: Add wasm32-dis.c to wasm32 target.
1422 * disassemble.c: Add wasm32 disassembler code.
1423 * wasm32-dis.c: New file.
1424 * Makefile.in: Regenerate.
1425 * configure: Regenerate.
1426 * po/POTFILES.in: Regenerate.
1427 * po/opcodes.pot: Regenerate.
1428
1429 2017-04-05 Pedro Alves <palves@redhat.com>
1430
1431 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1432 * arm-dis.c (parse_arm_disassembler_options): Constify.
1433 * ppc-dis.c (powerpc_init_dialect): Constify local.
1434 * vax-dis.c (parse_disassembler_options): Constify.
1435
1436 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1437
1438 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1439 RISCV_GP_SYMBOL.
1440
1441 2017-03-30 Pip Cet <pipcet@gmail.com>
1442
1443 * configure.ac: Add (empty) bfd_wasm32_arch target.
1444 * configure: Regenerate
1445 * po/opcodes.pot: Regenerate.
1446
1447 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1448
1449 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1450 OSA2015.
1451 * opcodes/sparc-opc.c (asi_table): New ASIs.
1452
1453 2017-03-29 Alan Modra <amodra@gmail.com>
1454
1455 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1456 "raw" option.
1457 (lookup_powerpc): Don't special case -1 dialect. Handle
1458 PPC_OPCODE_RAW.
1459 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1460 lookup_powerpc call, pass it on second.
1461
1462 2017-03-27 Alan Modra <amodra@gmail.com>
1463
1464 PR 21303
1465 * ppc-dis.c (struct ppc_mopt): Comment.
1466 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1467
1468 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1469
1470 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1471 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1472 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1473 (insert_nps_misc_imm_offset): New function.
1474 (extract_nps_misc imm_offset): New function.
1475 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1476 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1477
1478 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1479
1480 * s390-mkopc.c (main): Remove vx2 check.
1481 * s390-opc.txt: Remove vx2 instruction flags.
1482
1483 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1484
1485 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1486 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1487 (insert_nps_imm_offset): New function.
1488 (extract_nps_imm_offset): New function.
1489 (insert_nps_imm_entry): New function.
1490 (extract_nps_imm_entry): New function.
1491
1492 2017-03-17 Alan Modra <amodra@gmail.com>
1493
1494 PR 21248
1495 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1496 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1497 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1498
1499 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1500
1501 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1502 <c.andi>: Likewise.
1503 <c.addiw> Likewise.
1504
1505 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1506
1507 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1508
1509 2017-03-13 Andrew Waterman <andrew@sifive.com>
1510
1511 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1512 <srl> Likewise.
1513 <srai> Likewise.
1514 <sra> Likewise.
1515
1516 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1517
1518 * i386-gen.c (opcode_modifiers): Replace S with Load.
1519 * i386-opc.h (S): Removed.
1520 (Load): New.
1521 (i386_opcode_modifier): Replace s with load.
1522 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1523 and {evex}. Replace S with Load.
1524 * i386-tbl.h: Regenerated.
1525
1526 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1527
1528 * i386-opc.tbl: Use CpuCET on rdsspq.
1529 * i386-tbl.h: Regenerated.
1530
1531 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1532
1533 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1534 <vsx>: Do not use PPC_OPCODE_VSX3;
1535
1536 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1537
1538 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1539
1540 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1541
1542 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1543 (MOD_0F1E_PREFIX_1): Likewise.
1544 (MOD_0F38F5_PREFIX_2): Likewise.
1545 (MOD_0F38F6_PREFIX_0): Likewise.
1546 (RM_0F1E_MOD_3_REG_7): Likewise.
1547 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1548 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1549 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1550 (PREFIX_0F1E): Likewise.
1551 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1552 (PREFIX_0F38F5): Likewise.
1553 (dis386_twobyte): Use PREFIX_0F1E.
1554 (reg_table): Add REG_0F1E_MOD_3.
1555 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1556 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1557 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1558 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1559 (three_byte_table): Use PREFIX_0F38F5.
1560 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1561 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1562 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1563 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1564 PREFIX_MOD_3_0F01_REG_5_RM_2.
1565 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1566 (cpu_flags): Add CpuCET.
1567 * i386-opc.h (CpuCET): New enum.
1568 (CpuUnused): Commented out.
1569 (i386_cpu_flags): Add cpucet.
1570 * i386-opc.tbl: Add Intel CET instructions.
1571 * i386-init.h: Regenerated.
1572 * i386-tbl.h: Likewise.
1573
1574 2017-03-06 Alan Modra <amodra@gmail.com>
1575
1576 PR 21124
1577 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1578 (extract_raq, extract_ras, extract_rbx): New functions.
1579 (powerpc_operands): Use opposite corresponding insert function.
1580 (Q_MASK): Define.
1581 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1582 register restriction.
1583
1584 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1585
1586 * disassemble.c Include "safe-ctype.h".
1587 (disassemble_init_for_target): Handle s390 init.
1588 (remove_whitespace_and_extra_commas): New function.
1589 (disassembler_options_cmp): Likewise.
1590 * arm-dis.c: Include "libiberty.h".
1591 (NUM_ELEM): Delete.
1592 (regnames): Use long disassembler style names.
1593 Add force-thumb and no-force-thumb options.
1594 (NUM_ARM_REGNAMES): Rename from this...
1595 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1596 (get_arm_regname_num_options): Delete.
1597 (set_arm_regname_option): Likewise.
1598 (get_arm_regnames): Likewise.
1599 (parse_disassembler_options): Likewise.
1600 (parse_arm_disassembler_option): Rename from this...
1601 (parse_arm_disassembler_options): ...to this. Make static.
1602 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1603 (print_insn): Use parse_arm_disassembler_options.
1604 (disassembler_options_arm): New function.
1605 (print_arm_disassembler_options): Handle updated regnames.
1606 * ppc-dis.c: Include "libiberty.h".
1607 (ppc_opts): Add "32" and "64" entries.
1608 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1609 (powerpc_init_dialect): Add break to switch statement.
1610 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1611 (disassembler_options_powerpc): New function.
1612 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1613 Remove printing of "32" and "64".
1614 * s390-dis.c: Include "libiberty.h".
1615 (init_flag): Remove unneeded variable.
1616 (struct s390_options_t): New structure type.
1617 (options): New structure.
1618 (init_disasm): Rename from this...
1619 (disassemble_init_s390): ...to this. Add initializations for
1620 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1621 (print_insn_s390): Delete call to init_disasm.
1622 (disassembler_options_s390): New function.
1623 (print_s390_disassembler_options): Print using information from
1624 struct 'options'.
1625 * po/opcodes.pot: Regenerate.
1626
1627 2017-02-28 Jan Beulich <jbeulich@suse.com>
1628
1629 * i386-dis.c (PCMPESTR_Fixup): New.
1630 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1631 (prefix_table): Use PCMPESTR_Fixup.
1632 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1633 PCMPESTR_Fixup.
1634 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1635 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1636 Split 64-bit and non-64-bit variants.
1637 * opcodes/i386-tbl.h: Re-generate.
1638
1639 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1640
1641 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1642 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1643 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1644 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1645 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1646 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1647 (OP_SVE_V_HSD): New macros.
1648 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1649 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1650 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1651 (aarch64_opcode_table): Add new SVE instructions.
1652 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1653 for rotation operands. Add new SVE operands.
1654 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1655 (ins_sve_quad_index): Likewise.
1656 (ins_imm_rotate): Split into...
1657 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1658 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1659 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1660 functions.
1661 (aarch64_ins_sve_addr_ri_s4): New function.
1662 (aarch64_ins_sve_quad_index): Likewise.
1663 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1664 * aarch64-asm-2.c: Regenerate.
1665 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1666 (ext_sve_quad_index): Likewise.
1667 (ext_imm_rotate): Split into...
1668 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1669 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1670 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1671 functions.
1672 (aarch64_ext_sve_addr_ri_s4): New function.
1673 (aarch64_ext_sve_quad_index): Likewise.
1674 (aarch64_ext_sve_index): Allow quad indices.
1675 (do_misc_decoding): Likewise.
1676 * aarch64-dis-2.c: Regenerate.
1677 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1678 aarch64_field_kinds.
1679 (OPD_F_OD_MASK): Widen by one bit.
1680 (OPD_F_NO_ZR): Bump accordingly.
1681 (get_operand_field_width): New function.
1682 * aarch64-opc.c (fields): Add new SVE fields.
1683 (operand_general_constraint_met_p): Handle new SVE operands.
1684 (aarch64_print_operand): Likewise.
1685 * aarch64-opc-2.c: Regenerate.
1686
1687 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1688
1689 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1690 (aarch64_feature_compnum): ...this.
1691 (SIMD_V8_3): Replace with...
1692 (COMPNUM): ...this.
1693 (CNUM_INSN): New macro.
1694 (aarch64_opcode_table): Use it for the complex number instructions.
1695
1696 2017-02-24 Jan Beulich <jbeulich@suse.com>
1697
1698 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1699
1700 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1701
1702 Add support for associating SPARC ASIs with an architecture level.
1703 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1704 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1705 decoding of SPARC ASIs.
1706
1707 2017-02-23 Jan Beulich <jbeulich@suse.com>
1708
1709 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1710 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1711
1712 2017-02-21 Jan Beulich <jbeulich@suse.com>
1713
1714 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1715 1 (instead of to itself). Correct typo.
1716
1717 2017-02-14 Andrew Waterman <andrew@sifive.com>
1718
1719 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1720 pseudoinstructions.
1721
1722 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1723
1724 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1725 (aarch64_sys_reg_supported_p): Handle them.
1726
1727 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1728
1729 * arc-opc.c (UIMM6_20R): Define.
1730 (SIMM12_20): Use above.
1731 (SIMM12_20R): Define.
1732 (SIMM3_5_S): Use above.
1733 (UIMM7_A32_11R_S): Define.
1734 (UIMM7_9_S): Use above.
1735 (UIMM3_13R_S): Define.
1736 (SIMM11_A32_7_S): Use above.
1737 (SIMM9_8R): Define.
1738 (UIMM10_A32_8_S): Use above.
1739 (UIMM8_8R_S): Define.
1740 (W6): Use above.
1741 (arc_relax_opcodes): Use all above defines.
1742
1743 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1744
1745 * arc-regs.h: Distinguish some of the registers different on
1746 ARC700 and HS38 cpus.
1747
1748 2017-02-14 Alan Modra <amodra@gmail.com>
1749
1750 PR 21118
1751 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1752 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1753
1754 2017-02-11 Stafford Horne <shorne@gmail.com>
1755 Alan Modra <amodra@gmail.com>
1756
1757 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1758 Use insn_bytes_value and insn_int_value directly instead. Don't
1759 free allocated memory until function exit.
1760
1761 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1762
1763 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1764
1765 2017-02-03 Nick Clifton <nickc@redhat.com>
1766
1767 PR 21096
1768 * aarch64-opc.c (print_register_list): Ensure that the register
1769 list index will fir into the tb buffer.
1770 (print_register_offset_address): Likewise.
1771 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1772
1773 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1774
1775 PR 21056
1776 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1777 instructions when the previous fetch packet ends with a 32-bit
1778 instruction.
1779
1780 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1781
1782 * pru-opc.c: Remove vague reference to a future GDB port.
1783
1784 2017-01-20 Nick Clifton <nickc@redhat.com>
1785
1786 * po/ga.po: Updated Irish translation.
1787
1788 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1789
1790 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1791
1792 2017-01-13 Yao Qi <yao.qi@linaro.org>
1793
1794 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1795 if FETCH_DATA returns 0.
1796 (m68k_scan_mask): Likewise.
1797 (print_insn_m68k): Update code to handle -1 return value.
1798
1799 2017-01-13 Yao Qi <yao.qi@linaro.org>
1800
1801 * m68k-dis.c (enum print_insn_arg_error): New.
1802 (NEXTBYTE): Replace -3 with
1803 PRINT_INSN_ARG_MEMORY_ERROR.
1804 (NEXTULONG): Likewise.
1805 (NEXTSINGLE): Likewise.
1806 (NEXTDOUBLE): Likewise.
1807 (NEXTDOUBLE): Likewise.
1808 (NEXTPACKED): Likewise.
1809 (FETCH_ARG): Likewise.
1810 (FETCH_DATA): Update comments.
1811 (print_insn_arg): Update comments. Replace magic numbers with
1812 enum.
1813 (match_insn_m68k): Likewise.
1814
1815 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1816
1817 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1818 * i386-dis-evex.h (evex_table): Updated.
1819 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1820 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1821 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1822 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1823 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1824 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1825 * i386-init.h: Regenerate.
1826 * i386-tbl.h: Ditto.
1827
1828 2017-01-12 Yao Qi <yao.qi@linaro.org>
1829
1830 * msp430-dis.c (msp430_singleoperand): Return -1 if
1831 msp430dis_opcode_signed returns false.
1832 (msp430_doubleoperand): Likewise.
1833 (msp430_branchinstr): Return -1 if
1834 msp430dis_opcode_unsigned returns false.
1835 (msp430x_calla_instr): Likewise.
1836 (print_insn_msp430): Likewise.
1837
1838 2017-01-05 Nick Clifton <nickc@redhat.com>
1839
1840 PR 20946
1841 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1842 could not be matched.
1843 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1844 NULL.
1845
1846 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1847
1848 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1849 (aarch64_opcode_table): Use RCPC_INSN.
1850
1851 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1852
1853 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1854 extension.
1855 * riscv-opcodes/all-opcodes: Likewise.
1856
1857 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1858
1859 * riscv-dis.c (print_insn_args): Add fall through comment.
1860
1861 2017-01-03 Nick Clifton <nickc@redhat.com>
1862
1863 * po/sr.po: New Serbian translation.
1864 * configure.ac (ALL_LINGUAS): Add sr.
1865 * configure: Regenerate.
1866
1867 2017-01-02 Alan Modra <amodra@gmail.com>
1868
1869 * epiphany-desc.h: Regenerate.
1870 * epiphany-opc.h: Regenerate.
1871 * fr30-desc.h: Regenerate.
1872 * fr30-opc.h: Regenerate.
1873 * frv-desc.h: Regenerate.
1874 * frv-opc.h: Regenerate.
1875 * ip2k-desc.h: Regenerate.
1876 * ip2k-opc.h: Regenerate.
1877 * iq2000-desc.h: Regenerate.
1878 * iq2000-opc.h: Regenerate.
1879 * lm32-desc.h: Regenerate.
1880 * lm32-opc.h: Regenerate.
1881 * m32c-desc.h: Regenerate.
1882 * m32c-opc.h: Regenerate.
1883 * m32r-desc.h: Regenerate.
1884 * m32r-opc.h: Regenerate.
1885 * mep-desc.h: Regenerate.
1886 * mep-opc.h: Regenerate.
1887 * mt-desc.h: Regenerate.
1888 * mt-opc.h: Regenerate.
1889 * or1k-desc.h: Regenerate.
1890 * or1k-opc.h: Regenerate.
1891 * xc16x-desc.h: Regenerate.
1892 * xc16x-opc.h: Regenerate.
1893 * xstormy16-desc.h: Regenerate.
1894 * xstormy16-opc.h: Regenerate.
1895
1896 2017-01-02 Alan Modra <amodra@gmail.com>
1897
1898 Update year range in copyright notice of all files.
1899
1900 For older changes see ChangeLog-2016
1901 \f
1902 Copyright (C) 2017 Free Software Foundation, Inc.
1903
1904 Copying and distribution of this file, with or without modification,
1905 are permitted in any medium without royalty provided the copyright
1906 notice and this notice are preserved.
1907
1908 Local Variables:
1909 mode: change-log
1910 left-margin: 8
1911 fill-column: 74
1912 version-control: never
1913 End:
GDB Binutils - Deliverables
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