opcodes/ChangeLog

   1 2019-06-03  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (prefix_opcd_indices): Correct size.
   4
   5 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         PR gas/24625
   8         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
   9         Disp8ShiftVL.
  10         * i386-tbl.h: Regenerated.
  11
  12 2019-05-24  Alan Modra  <amodra@gmail.com>
  13
  14         * po/POTFILES.in: Regenerate.
  15
  16 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  17             Alan Modra  <amodra@gmail.com>
  18
  19         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  20         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  21         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  22         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  23         XTOP>): Define and add entries.
  24         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  25         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  26         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  27         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  28
  29 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  30             Alan Modra  <amodra@gmail.com>
  31
  32         * ppc-dis.c (ppc_opts): Add "future" entry.
  33         (PREFIX_OPCD_SEGS): Define.
  34         (prefix_opcd_indices): New array.
  35         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  36         (lookup_prefix): New function.
  37         (print_insn_powerpc): Handle 64-bit prefix instructions.
  38         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  39         (PMRR, POWERXX): Define.
  40         (prefix_opcodes): New instruction table.
  41         (prefix_num_opcodes): New constant.
  42
  43 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  44
  45         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  46         * configure: Regenerated.
  47         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  48         and cpu/bpf.opc.
  49         (HFILES): Add bpf-desc.h and bpf-opc.h.
  50         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  51         bpf-ibld.c and bpf-opc.c.
  52         (BPF_DEPS): Define.
  53         * Makefile.in: Regenerated.
  54         * disassemble.c (ARCH_bpf): Define.
  55         (disassembler): Add case for bfd_arch_bpf.
  56         (disassemble_init_for_target): Likewise.
  57         (enum epbf_isa_attr): Define.
  58         * disassemble.h: extern print_insn_bpf.
  59         * bpf-asm.c: Generated.
  60         * bpf-opc.h: Likewise.
  61         * bpf-opc.c: Likewise.
  62         * bpf-ibld.c: Likewise.
  63         * bpf-dis.c: Likewise.
  64         * bpf-desc.h: Likewise.
  65         * bpf-desc.c: Likewise.
  66
  67 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  70         and VMSR with the new operands.
  71
  72 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  73
  74         * arm-dis.c (enum mve_instructions): New enum
  75         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  76         and cneg.
  77         (mve_opcodes): New instructions as above.
  78         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  79         csneg and csel.
  80         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  81
  82 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  83
  84         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  85         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  86         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  87         uqshl, urshrl and urshr.
  88         (is_mve_okay_in_it): Add new instructions to TRUE list.
  89         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  90         (print_insn_mve): Updated to accept new %j,
  91         %<bitfield>m and %<bitfield>n patterns.
  92
  93 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  94
  95         * mips-opc.c (mips_builtin_opcodes): Change source register
  96         constraint for DAUI.
  97
  98 2019-05-20  Nick Clifton  <nickc@redhat.com>
  99
 100         * po/fr.po: Updated French translation.
 101
 102 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 103             Michael Collison <michael.collison@arm.com>
 104
 105         * arm-dis.c (thumb32_opcodes): Add new instructions.
 106         (enum mve_instructions): Likewise.
 107         (enum mve_undefined): Add new reasons.
 108         (is_mve_encoding_conflict): Handle new instructions.
 109         (is_mve_undefined): Likewise.
 110         (is_mve_unpredictable): Likewise.
 111         (print_mve_undefined): Likewise.
 112         (print_mve_size): Likewise.
 113
 114 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 115             Michael Collison <michael.collison@arm.com>
 116
 117         * arm-dis.c (thumb32_opcodes): Add new instructions.
 118         (enum mve_instructions): Likewise.
 119         (is_mve_encoding_conflict): Handle new instructions.
 120         (is_mve_undefined): Likewise.
 121         (is_mve_unpredictable): Likewise.
 122         (print_mve_size): Likewise.
 123
 124 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 125             Michael Collison <michael.collison@arm.com>
 126
 127         * arm-dis.c (thumb32_opcodes): Add new instructions.
 128         (enum mve_instructions): Likewise.
 129         (is_mve_encoding_conflict): Likewise.
 130         (is_mve_unpredictable): Likewise.
 131         (print_mve_size): Likewise.
 132
 133 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 134             Michael Collison <michael.collison@arm.com>
 135
 136         * arm-dis.c (thumb32_opcodes): Add new instructions.
 137         (enum mve_instructions): Likewise.
 138         (is_mve_encoding_conflict): Handle new instructions.
 139         (is_mve_undefined): Likewise.
 140         (is_mve_unpredictable): Likewise.
 141         (print_mve_size): Likewise.
 142
 143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 144             Michael Collison <michael.collison@arm.com>
 145
 146         * arm-dis.c (thumb32_opcodes): Add new instructions.
 147         (enum mve_instructions): Likewise.
 148         (is_mve_encoding_conflict): Handle new instructions.
 149         (is_mve_undefined): Likewise.
 150         (is_mve_unpredictable): Likewise.
 151         (print_mve_size): Likewise.
 152         (print_insn_mve): Likewise.
 153
 154 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 155             Michael Collison <michael.collison@arm.com>
 156
 157         * arm-dis.c (thumb32_opcodes): Add new instructions.
 158         (print_insn_thumb32): Handle new instructions.
 159
 160 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 161             Michael Collison <michael.collison@arm.com>
 162
 163         * arm-dis.c (enum mve_instructions): Add new instructions.
 164         (enum mve_undefined): Add new reasons.
 165         (is_mve_encoding_conflict): Handle new instructions.
 166         (is_mve_undefined): Likewise.
 167         (is_mve_unpredictable): Likewise.
 168         (print_mve_undefined): Likewise.
 169         (print_mve_size): Likewise.
 170         (print_mve_shift_n): Likewise.
 171         (print_insn_mve): Likewise.
 172
 173 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 174             Michael Collison <michael.collison@arm.com>
 175
 176         * arm-dis.c (enum mve_instructions): Add new instructions.
 177         (is_mve_encoding_conflict): Handle new instructions.
 178         (is_mve_unpredictable): Likewise.
 179         (print_mve_rotate): Likewise.
 180         (print_mve_size): Likewise.
 181         (print_insn_mve): Likewise.
 182
 183 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 184             Michael Collison <michael.collison@arm.com>
 185
 186         * arm-dis.c (enum mve_instructions): Add new instructions.
 187         (is_mve_encoding_conflict): Handle new instructions.
 188         (is_mve_unpredictable): Likewise.
 189         (print_mve_size): Likewise.
 190         (print_insn_mve): Likewise.
 191
 192 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 193             Michael Collison <michael.collison@arm.com>
 194
 195         * arm-dis.c (enum mve_instructions): Add new instructions.
 196         (enum mve_undefined): Add new reasons.
 197         (is_mve_encoding_conflict): Handle new instructions.
 198         (is_mve_undefined): Likewise.
 199         (is_mve_unpredictable): Likewise.
 200         (print_mve_undefined): Likewise.
 201         (print_mve_size): Likewise.
 202         (print_insn_mve): Likewise.
 203
 204 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 205             Michael Collison <michael.collison@arm.com>
 206
 207         * arm-dis.c (enum mve_instructions): Add new instructions.
 208         (is_mve_encoding_conflict): Handle new instructions.
 209         (is_mve_undefined): Likewise.
 210         (is_mve_unpredictable): Likewise.
 211         (print_mve_size): Likewise.
 212         (print_insn_mve): Likewise.
 213
 214 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 215             Michael Collison <michael.collison@arm.com>
 216
 217         * arm-dis.c (enum mve_instructions): Add new instructions.
 218         (enum mve_unpredictable): Add new reasons.
 219         (enum mve_undefined): Likewise.
 220         (is_mve_okay_in_it): Handle new isntructions.
 221         (is_mve_encoding_conflict): Likewise.
 222         (is_mve_undefined): Likewise.
 223         (is_mve_unpredictable): Likewise.
 224         (print_mve_vmov_index): Likewise.
 225         (print_simd_imm8): Likewise.
 226         (print_mve_undefined): Likewise.
 227         (print_mve_unpredictable): Likewise.
 228         (print_mve_size): Likewise.
 229         (print_insn_mve): Likewise.
 230
 231 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 232             Michael Collison <michael.collison@arm.com>
 233
 234         * arm-dis.c (enum mve_instructions): Add new instructions.
 235         (enum mve_unpredictable): Add new reasons.
 236         (enum mve_undefined): Likewise.
 237         (is_mve_encoding_conflict): Handle new instructions.
 238         (is_mve_undefined): Likewise.
 239         (is_mve_unpredictable): Likewise.
 240         (print_mve_undefined): Likewise.
 241         (print_mve_unpredictable): Likewise.
 242         (print_mve_rounding_mode): Likewise.
 243         (print_mve_vcvt_size): Likewise.
 244         (print_mve_size): Likewise.
 245         (print_insn_mve): Likewise.
 246
 247 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 248             Michael Collison <michael.collison@arm.com>
 249
 250         * arm-dis.c (enum mve_instructions): Add new instructions.
 251         (enum mve_unpredictable): Add new reasons.
 252         (enum mve_undefined): Likewise.
 253         (is_mve_undefined): Handle new instructions.
 254         (is_mve_unpredictable): Likewise.
 255         (print_mve_undefined): Likewise.
 256         (print_mve_unpredictable): Likewise.
 257         (print_mve_size): Likewise.
 258         (print_insn_mve): Likewise.
 259
 260 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 261             Michael Collison <michael.collison@arm.com>
 262
 263         * arm-dis.c (enum mve_instructions): Add new instructions.
 264         (enum mve_undefined): Add new reasons.
 265         (insns): Add new instructions.
 266         (is_mve_encoding_conflict):
 267         (print_mve_vld_str_addr): New print function.
 268         (is_mve_undefined): Handle new instructions.
 269         (is_mve_unpredictable): Likewise.
 270         (print_mve_undefined): Likewise.
 271         (print_mve_size): Likewise.
 272         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 273         (print_insn_mve):  Handle new operands.
 274
 275 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 276             Michael Collison <michael.collison@arm.com>
 277
 278         * arm-dis.c (enum mve_instructions): Add new instructions.
 279         (enum mve_unpredictable): Add new reasons.
 280         (is_mve_encoding_conflict): Handle new instructions.
 281         (is_mve_unpredictable): Likewise.
 282         (mve_opcodes): Add new instructions.
 283         (print_mve_unpredictable): Handle new reasons.
 284         (print_mve_register_blocks): New print function.
 285         (print_mve_size): Handle new instructions.
 286         (print_insn_mve): Likewise.
 287
 288 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 289             Michael Collison <michael.collison@arm.com>
 290
 291         * arm-dis.c (enum mve_instructions): Add new instructions.
 292         (enum mve_unpredictable): Add new reasons.
 293         (enum mve_undefined): Likewise.
 294         (is_mve_encoding_conflict): Handle new instructions.
 295         (is_mve_undefined): Likewise.
 296         (is_mve_unpredictable): Likewise.
 297         (coprocessor_opcodes): Move NEON VDUP from here...
 298         (neon_opcodes): ... to here.
 299         (mve_opcodes): Add new instructions.
 300         (print_mve_undefined):  Handle new reasons.
 301         (print_mve_unpredictable): Likewise.
 302         (print_mve_size): Handle new instructions.
 303         (print_insn_neon): Handle vdup.
 304         (print_insn_mve): Handle new operands.
 305
 306 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 307             Michael Collison <michael.collison@arm.com>
 308
 309         * arm-dis.c (enum mve_instructions): Add new instructions.
 310         (enum mve_unpredictable): Add new values.
 311         (mve_opcodes): Add new instructions.
 312         (vec_condnames): New array with vector conditions.
 313         (mve_predicatenames): New array with predicate suffixes.
 314         (mve_vec_sizename): New array with vector sizes.
 315         (enum vpt_pred_state): New enum with vector predication states.
 316         (struct vpt_block): New struct type for vpt blocks.
 317         (vpt_block_state): Global struct to keep track of state.
 318         (mve_extract_pred_mask): New helper function.
 319         (num_instructions_vpt_block): Likewise.
 320         (mark_outside_vpt_block): Likewise.
 321         (mark_inside_vpt_block): Likewise.
 322         (invert_next_predicate_state): Likewise.
 323         (update_next_predicate_state): Likewise.
 324         (update_vpt_block_state): Likewise.
 325         (is_vpt_instruction): Likewise.
 326         (is_mve_encoding_conflict): Add entries for new instructions.
 327         (is_mve_unpredictable): Likewise.
 328         (print_mve_unpredictable): Handle new cases.
 329         (print_instruction_predicate): Likewise.
 330         (print_mve_size): New function.
 331         (print_vec_condition): New function.
 332         (print_insn_mve): Handle vpt blocks and new print operands.
 333
 334 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 335
 336         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 337         8, 14 and 15 for Armv8.1-M Mainline.
 338
 339 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 340             Michael Collison <michael.collison@arm.com>
 341
 342         * arm-dis.c (enum mve_instructions): New enum.
 343         (enum mve_unpredictable): Likewise.
 344         (enum mve_undefined): Likewise.
 345         (struct mopcode32): New struct.
 346         (is_mve_okay_in_it): New function.
 347         (is_mve_architecture): Likewise.
 348         (arm_decode_field): Likewise.
 349         (arm_decode_field_multiple): Likewise.
 350         (is_mve_encoding_conflict): Likewise.
 351         (is_mve_undefined): Likewise.
 352         (is_mve_unpredictable): Likewise.
 353         (print_mve_undefined): Likewise.
 354         (print_mve_unpredictable): Likewise.
 355         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 356         (print_insn_mve): New function.
 357         (print_insn_thumb32): Handle MVE architecture.
 358         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 359
 360 2019-05-10  Nick Clifton  <nickc@redhat.com>
 361
 362         PR 24538
 363         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 364         end of the table prematurely.
 365
 366 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 367
 368         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 369         macros for R6.
 370
 371 2019-05-11  Alan Modra  <amodra@gmail.com>
 372
 373         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 374         when -Mraw is in effect.
 375
 376 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 377
 378         * aarch64-dis-2.c: Regenerate.
 379         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 380         (OP_SVE_BBB): New variant set.
 381         (OP_SVE_DDDD): New variant set.
 382         (OP_SVE_HHH): New variant set.
 383         (OP_SVE_HHHU): New variant set.
 384         (OP_SVE_SSS): New variant set.
 385         (OP_SVE_SSSU): New variant set.
 386         (OP_SVE_SHH): New variant set.
 387         (OP_SVE_SBBU): New variant set.
 388         (OP_SVE_DSS): New variant set.
 389         (OP_SVE_DHHU): New variant set.
 390         (OP_SVE_VMV_HSD_BHS): New variant set.
 391         (OP_SVE_VVU_HSD_BHS): New variant set.
 392         (OP_SVE_VVVU_SD_BH): New variant set.
 393         (OP_SVE_VVVU_BHSD): New variant set.
 394         (OP_SVE_VVV_QHD_DBS): New variant set.
 395         (OP_SVE_VVV_HSD_BHS): New variant set.
 396         (OP_SVE_VVV_HSD_BHS2): New variant set.
 397         (OP_SVE_VVV_BHS_HSD): New variant set.
 398         (OP_SVE_VV_BHS_HSD): New variant set.
 399         (OP_SVE_VVV_SD): New variant set.
 400         (OP_SVE_VVU_BHS_HSD): New variant set.
 401         (OP_SVE_VZVV_SD): New variant set.
 402         (OP_SVE_VZVV_BH): New variant set.
 403         (OP_SVE_VZV_SD): New variant set.
 404         (aarch64_opcode_table): Add sve2 instructions.
 405
 406 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 407
 408         * aarch64-asm-2.c: Regenerated.
 409         * aarch64-dis-2.c: Regenerated.
 410         * aarch64-opc-2.c: Regenerated.
 411         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 412         for SVE_SHLIMM_UNPRED_22.
 413         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 414         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 415         operand.
 416
 417 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 418
 419         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 420         sve_size_tsz_bhs iclass encode.
 421         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 422         sve_size_tsz_bhs iclass decode.
 423
 424 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 425
 426         * aarch64-asm-2.c: Regenerated.
 427         * aarch64-dis-2.c: Regenerated.
 428         * aarch64-opc-2.c: Regenerated.
 429         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 430         for SVE_Zm4_11_INDEX.
 431         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 432         (fields): Handle SVE_i2h field.
 433         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 434         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 435
 436 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 437
 438         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 439         sve_shift_tsz_bhsd iclass encode.
 440         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 441         sve_shift_tsz_bhsd iclass decode.
 442
 443 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 444
 445         * aarch64-asm-2.c: Regenerated.
 446         * aarch64-dis-2.c: Regenerated.
 447         * aarch64-opc-2.c: Regenerated.
 448         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 449         (aarch64_encode_variant_using_iclass): Handle
 450         sve_shift_tsz_hsd iclass encode.
 451         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 452         sve_shift_tsz_hsd iclass decode.
 453         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 454         for SVE_SHRIMM_UNPRED_22.
 455         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 456         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 457         operand.
 458
 459 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 460
 461         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 462         sve_size_013 iclass encode.
 463         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 464         sve_size_013 iclass decode.
 465
 466 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 467
 468         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 469         sve_size_bh iclass encode.
 470         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 471         sve_size_bh iclass decode.
 472
 473 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 474
 475         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 476         sve_size_sd2 iclass encode.
 477         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 478         sve_size_sd2 iclass decode.
 479         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 480         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 481
 482 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 483
 484         * aarch64-asm-2.c: Regenerated.
 485         * aarch64-dis-2.c: Regenerated.
 486         * aarch64-opc-2.c: Regenerated.
 487         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 488         for SVE_ADDR_ZX.
 489         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 490         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 491
 492 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 493
 494         * aarch64-asm-2.c: Regenerated.
 495         * aarch64-dis-2.c: Regenerated.
 496         * aarch64-opc-2.c: Regenerated.
 497         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 498         for SVE_Zm3_11_INDEX.
 499         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 500         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 501         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 502         fields.
 503         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 504
 505 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 506
 507         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 508         sve_size_hsd2 iclass encode.
 509         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 510         sve_size_hsd2 iclass decode.
 511         * aarch64-opc.c (fields): Handle SVE_size field.
 512         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 513
 514 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 515
 516         * aarch64-asm-2.c: Regenerated.
 517         * aarch64-dis-2.c: Regenerated.
 518         * aarch64-opc-2.c: Regenerated.
 519         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 520         for SVE_IMM_ROT3.
 521         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 522         (fields): Handle SVE_rot3 field.
 523         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 524         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 525
 526 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 527
 528         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 529         instructions.
 530
 531 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 532
 533         * aarch64-tbl.h
 534         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 535         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 536         aarch64_feature_sve2bitperm): New feature sets.
 537         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 538         for feature set addresses.
 539         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 540         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 541
 542 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 543             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 544
 545         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 546         argument and set ASE_EVA_R6 appropriately.
 547         (set_default_mips_dis_options): Pass ISA to above.
 548         (parse_mips_dis_option): Likewise.
 549         * mips-opc.c (EVAR6): New macro.
 550         (mips_builtin_opcodes): Add llwpe, scwpe.
 551
 552 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 553
 554         * aarch64-asm-2.c: Regenerated.
 555         * aarch64-dis-2.c: Regenerated.
 556         * aarch64-opc-2.c: Regenerated.
 557         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 558         AARCH64_OPND_TME_UIMM16.
 559         (aarch64_print_operand): Likewise.
 560         * aarch64-tbl.h (QL_IMM_NIL): New.
 561         (TME): New.
 562         (_TME_INSN): New.
 563         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 564
 565 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 566
 567         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 568
 569 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 570             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 571
 572         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 573
 574 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 575
 576         * s12z-opc.h: Add extern "C" bracketing to help
 577         users who wish to use this interface in c++ code.
 578
 579 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 580
 581         * s12z-opc.c (bm_decode): Handle bit map operations with the
 582         "reserved0" mode.
 583
 584 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 585
 586         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 587         specifier.  Add entries for VLDR and VSTR of system registers.
 588         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 589         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 590         of %J and %K format specifier.
 591
 592 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 593
 594         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 595         Add new entries for VSCCLRM instruction.
 596         (print_insn_coprocessor): Handle new %C format control code.
 597
 598 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 599
 600         * arm-dis.c (enum isa): New enum.
 601         (struct sopcode32): New structure.
 602         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 603         set isa field of all current entries to ANY.
 604         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 605         Only match an entry if its isa field allows the current mode.
 606
 607 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 608
 609         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 610         CLRM.
 611         (print_insn_thumb32): Add logic to print %n CLRM register list.
 612
 613 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 614
 615         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 616         and %Q patterns.
 617
 618 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 619
 620         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 621         (print_insn_thumb32): Edit the switch case for %Z.
 622
 623 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 624
 625         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 626
 627 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 628
 629         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 630
 631 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 632
 633         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 634
 635 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 636
 637         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 638         Arm register with r13 and r15 unpredictable.
 639         (thumb32_opcodes): New instructions for bfx and bflx.
 640
 641 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 642
 643         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 644
 645 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 646
 647         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 648
 649 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 650
 651         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 652
 653 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 654
 655         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 656
 657 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 658
 659         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 660         "optr". ("operator" is a reserved word in c++).
 661
 662 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 663
 664         * aarch64-opc.c (aarch64_print_operand): Add case for
 665         AARCH64_OPND_Rt_SP.
 666         (verify_constraints): Likewise.
 667         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 668         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 669         to accept Rt|SP as first operand.
 670         (AARCH64_OPERANDS): Add new Rt_SP.
 671         * aarch64-asm-2.c: Regenerated.
 672         * aarch64-dis-2.c: Regenerated.
 673         * aarch64-opc-2.c: Regenerated.
 674
 675 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 676
 677         * aarch64-asm-2.c: Regenerated.
 678         * aarch64-dis-2.c: Likewise.
 679         * aarch64-opc-2.c: Likewise.
 680         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 681
 682 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 683
 684         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 685
 686 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 689         * i386-init.h: Regenerated.
 690
 691 2019-04-07  Alan Modra  <amodra@gmail.com>
 692
 693         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 694         op_separator to control printing of spaces, comma and parens
 695         rather than need_comma, need_paren and spaces vars.
 696
 697 2019-04-07  Alan Modra  <amodra@gmail.com>
 698
 699         PR 24421
 700         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 701         (print_insn_neon, print_insn_arm): Likewise.
 702
 703 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 704
 705         * i386-dis-evex.h (evex_table): Updated to support BF16
 706         instructions.
 707         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 708         and EVEX_W_0F3872_P_3.
 709         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 710         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 711         * i386-opc.h (enum): Add CpuAVX512_BF16.
 712         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 713         * i386-opc.tbl: Add AVX512 BF16 instructions.
 714         * i386-init.h: Regenerated.
 715         * i386-tbl.h: Likewise.
 716
 717 2019-04-05  Alan Modra  <amodra@gmail.com>
 718
 719         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 720         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 721         to favour printing of "-" branch hint when using the "y" bit.
 722         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 723
 724 2019-04-05  Alan Modra  <amodra@gmail.com>
 725
 726         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 727         opcode until first operand is output.
 728
 729 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 730
 731         PR gas/24349
 732         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 733         (valid_bo_post_v2): Add support for 'at' branch hints.
 734         (insert_bo): Only error on branch on ctr.
 735         (get_bo_hint_mask): New function.
 736         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 737         for inserting 'at' branch hints.
 738         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 739         for extracting 'at' branch hints.
 740         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 741         (BOE): Delete operand.
 742         (BOM, BOP): New operands.
 743         (RM): Update value.
 744         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 745         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 746         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 747         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 748         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 749         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 750         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 751         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 752         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 753         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 754         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 755         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 756         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 757         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 758         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 759         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 760         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 761         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 762         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 763         bttarl+>: New extended mnemonics.
 764
 765 2019-03-28  Alan Modra  <amodra@gmail.com>
 766
 767         PR 24390
 768         * ppc-opc.c (BTF): Define.
 769         (powerpc_opcodes): Use for mtfsb*.
 770         * ppc-dis.c (print_insn_powerpc): Print fields with both
 771         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 772
 773 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 774
 775         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 776         (mapping_symbol_for_insn): Implement new algorithm.
 777         (print_insn): Remove duplicate code.
 778
 779 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 780
 781         * aarch64-dis.c (print_insn_aarch64):
 782         Implement override.
 783
 784 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 785
 786         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 787         order.
 788
 789 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 790
 791         * aarch64-dis.c (last_stop_offset): New.
 792         (print_insn_aarch64): Use stop_offset.
 793
 794 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 795
 796         PR gas/24359
 797         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 798         CPU_ANY_AVX2_FLAGS.
 799         * i386-init.h: Regenerated.
 800
 801 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         PR gas/24348
 804         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 805         vmovdqu16, vmovdqu32 and vmovdqu64.
 806         * i386-tbl.h: Regenerated.
 807
 808 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 809
 810         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 811         from vstrszb, vstrszh, and vstrszf.
 812
 813 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 814
 815         * s390-opc.txt: Add instruction descriptions.
 816
 817 2019-02-08  Jim Wilson  <jimw@sifive.com>
 818
 819         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 820         <bne>: Likewise.
 821
 822 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 823
 824         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 825
 826 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 827
 828         PR binutils/23212
 829         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 830         * aarch64-opc.c (verify_elem_sd): New.
 831         (fields): Add FLD_sz entr.
 832         * aarch64-tbl.h (_SIMD_INSN): New.
 833         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 834         fmulx scalar and vector by element isns.
 835
 836 2019-02-07  Nick Clifton  <nickc@redhat.com>
 837
 838         * po/sv.po: Updated Swedish translation.
 839
 840 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 841
 842         * s390-mkopc.c (main): Accept arch13 as cpu string.
 843         * s390-opc.c: Add new instruction formats and instruction opcode
 844         masks.
 845         * s390-opc.txt: Add new arch13 instructions.
 846
 847 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 848
 849         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 850         (aarch64_opcode): Change encoding for stg, stzg
 851         st2g and st2zg.
 852         * aarch64-asm-2.c: Regenerated.
 853         * aarch64-dis-2.c: Regenerated.
 854         * aarch64-opc-2.c: Regenerated.
 855
 856 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 857
 858         * aarch64-asm-2.c: Regenerated.
 859         * aarch64-dis-2.c: Likewise.
 860         * aarch64-opc-2.c: Likewise.
 861         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 862
 863 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 864             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 865
 866         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 867         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 868         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 869         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 870         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 871         case for ldstgv_indexed.
 872         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 873         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 874         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 875         * aarch64-asm-2.c: Regenerated.
 876         * aarch64-dis-2.c: Regenerated.
 877         * aarch64-opc-2.c: Regenerated.
 878
 879 2019-01-23  Nick Clifton  <nickc@redhat.com>
 880
 881         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 882
 883 2019-01-21  Nick Clifton  <nickc@redhat.com>
 884
 885         * po/de.po: Updated German translation.
 886         * po/uk.po: Updated Ukranian translation.
 887
 888 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 889         * mips-dis.c (mips_arch_choices): Fix typo in
 890         gs464, gs464e and gs264e descriptors.
 891
 892 2019-01-19  Nick Clifton  <nickc@redhat.com>
 893
 894         * configure: Regenerate.
 895         * po/opcodes.pot: Regenerate.
 896
 897 2018-06-24  Nick Clifton  <nickc@redhat.com>
 898
 899         2.32 branch created.
 900
 901 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 902
 903         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 904         if it is null.
 905         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 906         zero.
 907
 908 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 909
 910         * configure: Regenerate.
 911
 912 2019-01-07  Alan Modra  <amodra@gmail.com>
 913
 914         * configure: Regenerate.
 915         * po/POTFILES.in: Regenerate.
 916
 917 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 918
 919         * s12z-opc.c: New file.
 920         * s12z-opc.h: New file.
 921         * s12z-dis.c: Removed all code not directly related to display
 922         of instructions.  Used the interface provided by the new files
 923         instead.
 924         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 925         * Makefile.in: Regenerate.
 926         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 927         * configure: Regenerate.
 928
 929 2019-01-01  Alan Modra  <amodra@gmail.com>
 930
 931         Update year range in copyright notice of all files.
 932
 933 For older changes see ChangeLog-2018
 934 \f
 935 Copyright (C) 2019 Free Software Foundation, Inc.
 936
 937 Copying and distribution of this file, with or without modification,
 938 are permitted in any medium without royalty provided the copyright
 939 notice and this notice are preserved.
 940
 941 Local Variables:
 942 mode: change-log
 943 left-margin: 8
 944 fill-column: 74
 945 version-control: never
 946 End: