opcodes/ChangeLog

   1 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * bpf-desc.c: Regenerated.
   4
   5 2019-07-17  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-gen.c (static_assert): Define.
   8         (main): Use it.
   9         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  10         (Opcode_Modifier_Num): ... this.
  11         (Mem): Delete.
  12
  13 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-gen.c (operand_types): Move RegMem ...
  16         (opcode_modifiers): ... here.
  17         * i386-opc.h (RegMem): Move to opcode modifer enum.
  18         (union i386_operand_type): Move regmem field ...
  19         (struct i386_opcode_modifier): ... here.
  20         * i386-opc.tbl (RegMem): Define.
  21         (mov, movq): Move RegMem on segment, control, debug, and test
  22         register flavors.
  23         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  24         to non-SSE2AVX flavor.
  25         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  26         Move RegMem on register only flavors. Drop IgnoreSize from
  27         legacy encoding flavors.
  28         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  29         flavors.
  30         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  31         register only flavors.
  32         (vmovd): Move RegMem and drop IgnoreSize on register only
  33         flavor. Change opcode and operand order to store form.
  34         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  35
  36 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  39         entries.
  40         * i386-opc.h (SReg2, SReg3): Replace by ...
  41         (SReg): ... this.
  42         (union i386_operand_type): Replace sreg fields.
  43         * i386-opc.tbl (mov, ): Use SReg.
  44         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  45         register flavors.
  46         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  47         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  48
  49 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  50
  51         * bpf-desc.c: Regenerate.
  52         * bpf-opc.c: Likewise.
  53         * bpf-opc.h: Likewise.
  54
  55 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  56
  57         * bpf-desc.c: Regenerate.
  58         * bpf-opc.c: Likewise.
  59
  60 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  61
  62         * arm-dis.c (print_insn_coprocessor): Rename index to
  63         index_operand.
  64
  65 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  66
  67         * riscv-opc.c (riscv_insn_types): Add r4 type.
  68
  69         * riscv-opc.c (riscv_insn_types): Add b and j type.
  70
  71         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  72         format for sb type and correct s type.
  73
  74 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  75
  76         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
  77         SVE FMOV alias of FCPY.
  78
  79 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  80
  81         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
  82         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
  83
  84 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  85
  86         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
  87         registers in an instruction prefixed by MOVPRFX.
  88
  89 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
  90
  91         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
  92         sve_size_13 icode to account for variant behaviour of
  93         pmull{t,b}.
  94         * aarch64-dis-2.c: Regenerate.
  95         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
  96         sve_size_13 icode to account for variant behaviour of
  97         pmull{t,b}.
  98         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
  99         (OP_SVE_VVV_Q_D): Add new qualifier.
 100         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 101         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 102         AES and those not.
 103
 104 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 105
 106         * opcodes/i386-gen.c (operand_type_init): Remove
 107         OPERAND_TYPE_VEC_IMM4 entry.
 108         (operand_types): Remove Vec_Imm4.
 109         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 110         (union i386_operand_type): Remove vec_imm4.
 111         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 112         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 113
 114 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 117         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 118         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 119         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 120         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 121         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 122         * i386-tbl.h: Re-generate.
 123
 124 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 127         register operands.
 128         * i386-tbl.h: Re-generate.
 129
 130 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (C): New.
 133         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 134         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 135         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 136         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 137         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 138         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 139         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 140         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 141         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 142         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 143         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 144         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 145         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 146         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 147         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 148         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 149         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 150         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 151         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 152         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 153         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 154         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 155         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 156         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 157         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 158         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 159         flavors.
 160         * i386-tbl.h: Re-generate.
 161
 162 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 165         register operands.
 166         * i386-tbl.h: Re-generate.
 167
 168 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 171         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 172         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 173         * i386-tbl.h: Re-generate.
 174
 175 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 178         Disp8MemShift from register only templates.
 179         * i386-tbl.h: Re-generate.
 180
 181 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 184         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 185         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 186         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 187         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 188         EVEX_W_0F11_P_3_M_1): Delete.
 189         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 190         EVEX_W_0F11_P_3): New.
 191         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 192         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 193         MOD_EVEX_0F11_PREFIX_3 table entries.
 194         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 195         PREFIX_EVEX_0F11 table entries.
 196         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 197         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 198         EVEX_W_0F11_P_3_M_{0,1} table entries.
 199
 200 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 203         Delete.
 204
 205 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 206
 207         PR binutils/24719
 208         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 209         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 210         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 211         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 212         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 213         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 214         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 215         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 216         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 217         PREFIX_EVEX_0F38C6_REG_6 entries.
 218         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 219         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 220         EVEX_W_0F38C7_R_6_P_2 entries.
 221         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 222         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 223         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 224         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 225         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 226         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 227         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 228
 229 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 232         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 233         VEX_LEN_0F2D_P_3): Delete.
 234         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 235         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 236         (prefix_table): ... here.
 237
 238 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-dis.c (Iq): Delete.
 241         (Id): New.
 242         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 243         TBM insns.
 244         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 245         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 246         (OP_E_memory): Also honor needindex when deciding whether an
 247         address size prefix needs printing.
 248         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 249
 250 2019-06-26  Jim Wilson  <jimw@sifive.com>
 251
 252         PR binutils/24739
 253         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 254         Set info->display_endian to info->endian_code.
 255
 256 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 259         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 260         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 261         OPERAND_TYPE_ACC64 entries.
 262         * i386-init.h: Re-generate.
 263
 264 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 267         Delete.
 268         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 269         of dqa_mode.
 270         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 271         entries here.
 272         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 273         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 274
 275 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 278         variables.
 279
 280 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 283         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 284         movnti.
 285         * i386-opc.tbl (movnti): Add IgnoreSize.
 286         * i386-tbl.h: Re-generate.
 287
 288 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 291         * i386-tbl.h: Re-generate.
 292
 293 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         * i386-dis-evex.h: Break into ...
 296         * i386-dis-evex-len.h: New file.
 297         * i386-dis-evex-mod.h: Likewise.
 298         * i386-dis-evex-prefix.h: Likewise.
 299         * i386-dis-evex-reg.h: Likewise.
 300         * i386-dis-evex-w.h: Likewise.
 301         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 302         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 303         i386-dis-evex-mod.h.
 304
 305 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         PR binutils/24700
 308         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 309         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 310         EVEX_W_0F385B_P_2.
 311         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 312         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 313         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 314         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 315         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 316         EVEX_LEN_0F385B_P_2_W_1.
 317         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 318         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 319         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 320         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 321         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 322         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 323         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 324         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 325         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 326         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 327
 328 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR binutils/24691
 331         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 332         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 333         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 334         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 335         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 336         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 337         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 338         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 339         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 340         EVEX_LEN_0F3A43_P_2_W_1.
 341         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 342         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 343         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 344         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 345         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 346         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 347         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 348         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 349         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 350         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 351         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 352         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 353
 354 2019-06-14  Nick Clifton  <nickc@redhat.com>
 355
 356         * po/fr.po; Updated French translation.
 357
 358 2019-06-13  Stafford Horne  <shorne@gmail.com>
 359
 360         * or1k-asm.c: Regenerated.
 361         * or1k-desc.c: Regenerated.
 362         * or1k-desc.h: Regenerated.
 363         * or1k-dis.c: Regenerated.
 364         * or1k-ibld.c: Regenerated.
 365         * or1k-opc.c: Regenerated.
 366         * or1k-opc.h: Regenerated.
 367         * or1k-opinst.c: Regenerated.
 368
 369 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 370
 371         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 372
 373 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         PR binutils/24633
 376         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 377         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 378         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 379         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 380         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 381         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 382         EVEX_LEN_0F3A1B_P_2_W_1.
 383         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 384         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 385         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 386         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 387         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 388         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 389         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 390         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 391
 392 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         PR binutils/24626
 395         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 396         EVEX.vvvv when disassembling VEX and EVEX instructions.
 397         (OP_VEX): Set vex.register_specifier to 0 after readding
 398         vex.register_specifier.
 399         (OP_Vex_2src_1): Likewise.
 400         (OP_Vex_2src_2): Likewise.
 401         (OP_LWP_E): Likewise.
 402         (OP_EX_Vex): Don't check vex.register_specifier.
 403         (OP_XMM_Vex): Likewise.
 404
 405 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 406             Lili Cui  <lili.cui@intel.com>
 407
 408         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 409         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 410         instructions.
 411         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 412         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 413         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 414         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 415         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 416         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 417         * i386-init.h: Regenerated.
 418         * i386-tbl.h: Likewise.
 419
 420 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 421             Lili Cui  <lili.cui@intel.com>
 422
 423         * doc/c-i386.texi: Document enqcmd.
 424         * testsuite/gas/i386/enqcmd-intel.d: New file.
 425         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 426         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 427         * testsuite/gas/i386/enqcmd.d: Likewise.
 428         * testsuite/gas/i386/enqcmd.s: Likewise.
 429         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 430         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 431         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 432         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 433         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 434         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 435         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 436         and x86-64-enqcmd.
 437
 438 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 439
 440         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 441
 442 2019-06-03  Alan Modra  <amodra@gmail.com>
 443
 444         * ppc-dis.c (prefix_opcd_indices): Correct size.
 445
 446 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 447
 448         PR gas/24625
 449         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 450         Disp8ShiftVL.
 451         * i386-tbl.h: Regenerated.
 452
 453 2019-05-24  Alan Modra  <amodra@gmail.com>
 454
 455         * po/POTFILES.in: Regenerate.
 456
 457 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 458             Alan Modra  <amodra@gmail.com>
 459
 460         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 461         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 462         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 463         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 464         XTOP>): Define and add entries.
 465         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 466         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 467         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 468         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 469
 470 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 471             Alan Modra  <amodra@gmail.com>
 472
 473         * ppc-dis.c (ppc_opts): Add "future" entry.
 474         (PREFIX_OPCD_SEGS): Define.
 475         (prefix_opcd_indices): New array.
 476         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 477         (lookup_prefix): New function.
 478         (print_insn_powerpc): Handle 64-bit prefix instructions.
 479         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 480         (PMRR, POWERXX): Define.
 481         (prefix_opcodes): New instruction table.
 482         (prefix_num_opcodes): New constant.
 483
 484 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 485
 486         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 487         * configure: Regenerated.
 488         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 489         and cpu/bpf.opc.
 490         (HFILES): Add bpf-desc.h and bpf-opc.h.
 491         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 492         bpf-ibld.c and bpf-opc.c.
 493         (BPF_DEPS): Define.
 494         * Makefile.in: Regenerated.
 495         * disassemble.c (ARCH_bpf): Define.
 496         (disassembler): Add case for bfd_arch_bpf.
 497         (disassemble_init_for_target): Likewise.
 498         (enum epbf_isa_attr): Define.
 499         * disassemble.h: extern print_insn_bpf.
 500         * bpf-asm.c: Generated.
 501         * bpf-opc.h: Likewise.
 502         * bpf-opc.c: Likewise.
 503         * bpf-ibld.c: Likewise.
 504         * bpf-dis.c: Likewise.
 505         * bpf-desc.h: Likewise.
 506         * bpf-desc.c: Likewise.
 507
 508 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 509
 510         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 511         and VMSR with the new operands.
 512
 513 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 514
 515         * arm-dis.c (enum mve_instructions): New enum
 516         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 517         and cneg.
 518         (mve_opcodes): New instructions as above.
 519         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 520         csneg and csel.
 521         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 522
 523 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 524
 525         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 526         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 527         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 528         uqshl, urshrl and urshr.
 529         (is_mve_okay_in_it): Add new instructions to TRUE list.
 530         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 531         (print_insn_mve): Updated to accept new %j,
 532         %<bitfield>m and %<bitfield>n patterns.
 533
 534 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 535
 536         * mips-opc.c (mips_builtin_opcodes): Change source register
 537         constraint for DAUI.
 538
 539 2019-05-20  Nick Clifton  <nickc@redhat.com>
 540
 541         * po/fr.po: Updated French translation.
 542
 543 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 544             Michael Collison <michael.collison@arm.com>
 545
 546         * arm-dis.c (thumb32_opcodes): Add new instructions.
 547         (enum mve_instructions): Likewise.
 548         (enum mve_undefined): Add new reasons.
 549         (is_mve_encoding_conflict): Handle new instructions.
 550         (is_mve_undefined): Likewise.
 551         (is_mve_unpredictable): Likewise.
 552         (print_mve_undefined): Likewise.
 553         (print_mve_size): Likewise.
 554
 555 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 556             Michael Collison <michael.collison@arm.com>
 557
 558         * arm-dis.c (thumb32_opcodes): Add new instructions.
 559         (enum mve_instructions): Likewise.
 560         (is_mve_encoding_conflict): Handle new instructions.
 561         (is_mve_undefined): Likewise.
 562         (is_mve_unpredictable): Likewise.
 563         (print_mve_size): Likewise.
 564
 565 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 566             Michael Collison <michael.collison@arm.com>
 567
 568         * arm-dis.c (thumb32_opcodes): Add new instructions.
 569         (enum mve_instructions): Likewise.
 570         (is_mve_encoding_conflict): Likewise.
 571         (is_mve_unpredictable): Likewise.
 572         (print_mve_size): Likewise.
 573
 574 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 575             Michael Collison <michael.collison@arm.com>
 576
 577         * arm-dis.c (thumb32_opcodes): Add new instructions.
 578         (enum mve_instructions): Likewise.
 579         (is_mve_encoding_conflict): Handle new instructions.
 580         (is_mve_undefined): Likewise.
 581         (is_mve_unpredictable): Likewise.
 582         (print_mve_size): Likewise.
 583
 584 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 585             Michael Collison <michael.collison@arm.com>
 586
 587         * arm-dis.c (thumb32_opcodes): Add new instructions.
 588         (enum mve_instructions): Likewise.
 589         (is_mve_encoding_conflict): Handle new instructions.
 590         (is_mve_undefined): Likewise.
 591         (is_mve_unpredictable): Likewise.
 592         (print_mve_size): Likewise.
 593         (print_insn_mve): Likewise.
 594
 595 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 596             Michael Collison <michael.collison@arm.com>
 597
 598         * arm-dis.c (thumb32_opcodes): Add new instructions.
 599         (print_insn_thumb32): Handle new instructions.
 600
 601 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 602             Michael Collison <michael.collison@arm.com>
 603
 604         * arm-dis.c (enum mve_instructions): Add new instructions.
 605         (enum mve_undefined): Add new reasons.
 606         (is_mve_encoding_conflict): Handle new instructions.
 607         (is_mve_undefined): Likewise.
 608         (is_mve_unpredictable): Likewise.
 609         (print_mve_undefined): Likewise.
 610         (print_mve_size): Likewise.
 611         (print_mve_shift_n): Likewise.
 612         (print_insn_mve): Likewise.
 613
 614 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 615             Michael Collison <michael.collison@arm.com>
 616
 617         * arm-dis.c (enum mve_instructions): Add new instructions.
 618         (is_mve_encoding_conflict): Handle new instructions.
 619         (is_mve_unpredictable): Likewise.
 620         (print_mve_rotate): Likewise.
 621         (print_mve_size): Likewise.
 622         (print_insn_mve): Likewise.
 623
 624 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 625             Michael Collison <michael.collison@arm.com>
 626
 627         * arm-dis.c (enum mve_instructions): Add new instructions.
 628         (is_mve_encoding_conflict): Handle new instructions.
 629         (is_mve_unpredictable): Likewise.
 630         (print_mve_size): Likewise.
 631         (print_insn_mve): Likewise.
 632
 633 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 634             Michael Collison <michael.collison@arm.com>
 635
 636         * arm-dis.c (enum mve_instructions): Add new instructions.
 637         (enum mve_undefined): Add new reasons.
 638         (is_mve_encoding_conflict): Handle new instructions.
 639         (is_mve_undefined): Likewise.
 640         (is_mve_unpredictable): Likewise.
 641         (print_mve_undefined): Likewise.
 642         (print_mve_size): Likewise.
 643         (print_insn_mve): Likewise.
 644
 645 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 646             Michael Collison <michael.collison@arm.com>
 647
 648         * arm-dis.c (enum mve_instructions): Add new instructions.
 649         (is_mve_encoding_conflict): Handle new instructions.
 650         (is_mve_undefined): Likewise.
 651         (is_mve_unpredictable): Likewise.
 652         (print_mve_size): Likewise.
 653         (print_insn_mve): Likewise.
 654
 655 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 656             Michael Collison <michael.collison@arm.com>
 657
 658         * arm-dis.c (enum mve_instructions): Add new instructions.
 659         (enum mve_unpredictable): Add new reasons.
 660         (enum mve_undefined): Likewise.
 661         (is_mve_okay_in_it): Handle new isntructions.
 662         (is_mve_encoding_conflict): Likewise.
 663         (is_mve_undefined): Likewise.
 664         (is_mve_unpredictable): Likewise.
 665         (print_mve_vmov_index): Likewise.
 666         (print_simd_imm8): Likewise.
 667         (print_mve_undefined): Likewise.
 668         (print_mve_unpredictable): Likewise.
 669         (print_mve_size): Likewise.
 670         (print_insn_mve): Likewise.
 671
 672 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 673             Michael Collison <michael.collison@arm.com>
 674
 675         * arm-dis.c (enum mve_instructions): Add new instructions.
 676         (enum mve_unpredictable): Add new reasons.
 677         (enum mve_undefined): Likewise.
 678         (is_mve_encoding_conflict): Handle new instructions.
 679         (is_mve_undefined): Likewise.
 680         (is_mve_unpredictable): Likewise.
 681         (print_mve_undefined): Likewise.
 682         (print_mve_unpredictable): Likewise.
 683         (print_mve_rounding_mode): Likewise.
 684         (print_mve_vcvt_size): Likewise.
 685         (print_mve_size): Likewise.
 686         (print_insn_mve): Likewise.
 687
 688 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 689             Michael Collison <michael.collison@arm.com>
 690
 691         * arm-dis.c (enum mve_instructions): Add new instructions.
 692         (enum mve_unpredictable): Add new reasons.
 693         (enum mve_undefined): Likewise.
 694         (is_mve_undefined): Handle new instructions.
 695         (is_mve_unpredictable): Likewise.
 696         (print_mve_undefined): Likewise.
 697         (print_mve_unpredictable): Likewise.
 698         (print_mve_size): Likewise.
 699         (print_insn_mve): Likewise.
 700
 701 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 702             Michael Collison <michael.collison@arm.com>
 703
 704         * arm-dis.c (enum mve_instructions): Add new instructions.
 705         (enum mve_undefined): Add new reasons.
 706         (insns): Add new instructions.
 707         (is_mve_encoding_conflict):
 708         (print_mve_vld_str_addr): New print function.
 709         (is_mve_undefined): Handle new instructions.
 710         (is_mve_unpredictable): Likewise.
 711         (print_mve_undefined): Likewise.
 712         (print_mve_size): Likewise.
 713         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 714         (print_insn_mve):  Handle new operands.
 715
 716 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 717             Michael Collison <michael.collison@arm.com>
 718
 719         * arm-dis.c (enum mve_instructions): Add new instructions.
 720         (enum mve_unpredictable): Add new reasons.
 721         (is_mve_encoding_conflict): Handle new instructions.
 722         (is_mve_unpredictable): Likewise.
 723         (mve_opcodes): Add new instructions.
 724         (print_mve_unpredictable): Handle new reasons.
 725         (print_mve_register_blocks): New print function.
 726         (print_mve_size): Handle new instructions.
 727         (print_insn_mve): Likewise.
 728
 729 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 730             Michael Collison <michael.collison@arm.com>
 731
 732         * arm-dis.c (enum mve_instructions): Add new instructions.
 733         (enum mve_unpredictable): Add new reasons.
 734         (enum mve_undefined): Likewise.
 735         (is_mve_encoding_conflict): Handle new instructions.
 736         (is_mve_undefined): Likewise.
 737         (is_mve_unpredictable): Likewise.
 738         (coprocessor_opcodes): Move NEON VDUP from here...
 739         (neon_opcodes): ... to here.
 740         (mve_opcodes): Add new instructions.
 741         (print_mve_undefined):  Handle new reasons.
 742         (print_mve_unpredictable): Likewise.
 743         (print_mve_size): Handle new instructions.
 744         (print_insn_neon): Handle vdup.
 745         (print_insn_mve): Handle new operands.
 746
 747 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 748             Michael Collison <michael.collison@arm.com>
 749
 750         * arm-dis.c (enum mve_instructions): Add new instructions.
 751         (enum mve_unpredictable): Add new values.
 752         (mve_opcodes): Add new instructions.
 753         (vec_condnames): New array with vector conditions.
 754         (mve_predicatenames): New array with predicate suffixes.
 755         (mve_vec_sizename): New array with vector sizes.
 756         (enum vpt_pred_state): New enum with vector predication states.
 757         (struct vpt_block): New struct type for vpt blocks.
 758         (vpt_block_state): Global struct to keep track of state.
 759         (mve_extract_pred_mask): New helper function.
 760         (num_instructions_vpt_block): Likewise.
 761         (mark_outside_vpt_block): Likewise.
 762         (mark_inside_vpt_block): Likewise.
 763         (invert_next_predicate_state): Likewise.
 764         (update_next_predicate_state): Likewise.
 765         (update_vpt_block_state): Likewise.
 766         (is_vpt_instruction): Likewise.
 767         (is_mve_encoding_conflict): Add entries for new instructions.
 768         (is_mve_unpredictable): Likewise.
 769         (print_mve_unpredictable): Handle new cases.
 770         (print_instruction_predicate): Likewise.
 771         (print_mve_size): New function.
 772         (print_vec_condition): New function.
 773         (print_insn_mve): Handle vpt blocks and new print operands.
 774
 775 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 776
 777         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 778         8, 14 and 15 for Armv8.1-M Mainline.
 779
 780 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 781             Michael Collison <michael.collison@arm.com>
 782
 783         * arm-dis.c (enum mve_instructions): New enum.
 784         (enum mve_unpredictable): Likewise.
 785         (enum mve_undefined): Likewise.
 786         (struct mopcode32): New struct.
 787         (is_mve_okay_in_it): New function.
 788         (is_mve_architecture): Likewise.
 789         (arm_decode_field): Likewise.
 790         (arm_decode_field_multiple): Likewise.
 791         (is_mve_encoding_conflict): Likewise.
 792         (is_mve_undefined): Likewise.
 793         (is_mve_unpredictable): Likewise.
 794         (print_mve_undefined): Likewise.
 795         (print_mve_unpredictable): Likewise.
 796         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 797         (print_insn_mve): New function.
 798         (print_insn_thumb32): Handle MVE architecture.
 799         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 800
 801 2019-05-10  Nick Clifton  <nickc@redhat.com>
 802
 803         PR 24538
 804         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 805         end of the table prematurely.
 806
 807 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 808
 809         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 810         macros for R6.
 811
 812 2019-05-11  Alan Modra  <amodra@gmail.com>
 813
 814         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 815         when -Mraw is in effect.
 816
 817 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 818
 819         * aarch64-dis-2.c: Regenerate.
 820         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 821         (OP_SVE_BBB): New variant set.
 822         (OP_SVE_DDDD): New variant set.
 823         (OP_SVE_HHH): New variant set.
 824         (OP_SVE_HHHU): New variant set.
 825         (OP_SVE_SSS): New variant set.
 826         (OP_SVE_SSSU): New variant set.
 827         (OP_SVE_SHH): New variant set.
 828         (OP_SVE_SBBU): New variant set.
 829         (OP_SVE_DSS): New variant set.
 830         (OP_SVE_DHHU): New variant set.
 831         (OP_SVE_VMV_HSD_BHS): New variant set.
 832         (OP_SVE_VVU_HSD_BHS): New variant set.
 833         (OP_SVE_VVVU_SD_BH): New variant set.
 834         (OP_SVE_VVVU_BHSD): New variant set.
 835         (OP_SVE_VVV_QHD_DBS): New variant set.
 836         (OP_SVE_VVV_HSD_BHS): New variant set.
 837         (OP_SVE_VVV_HSD_BHS2): New variant set.
 838         (OP_SVE_VVV_BHS_HSD): New variant set.
 839         (OP_SVE_VV_BHS_HSD): New variant set.
 840         (OP_SVE_VVV_SD): New variant set.
 841         (OP_SVE_VVU_BHS_HSD): New variant set.
 842         (OP_SVE_VZVV_SD): New variant set.
 843         (OP_SVE_VZVV_BH): New variant set.
 844         (OP_SVE_VZV_SD): New variant set.
 845         (aarch64_opcode_table): Add sve2 instructions.
 846
 847 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 848
 849         * aarch64-asm-2.c: Regenerated.
 850         * aarch64-dis-2.c: Regenerated.
 851         * aarch64-opc-2.c: Regenerated.
 852         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 853         for SVE_SHLIMM_UNPRED_22.
 854         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 855         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 856         operand.
 857
 858 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 859
 860         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 861         sve_size_tsz_bhs iclass encode.
 862         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 863         sve_size_tsz_bhs iclass decode.
 864
 865 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 866
 867         * aarch64-asm-2.c: Regenerated.
 868         * aarch64-dis-2.c: Regenerated.
 869         * aarch64-opc-2.c: Regenerated.
 870         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 871         for SVE_Zm4_11_INDEX.
 872         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 873         (fields): Handle SVE_i2h field.
 874         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 875         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 876
 877 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 878
 879         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 880         sve_shift_tsz_bhsd iclass encode.
 881         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 882         sve_shift_tsz_bhsd iclass decode.
 883
 884 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 885
 886         * aarch64-asm-2.c: Regenerated.
 887         * aarch64-dis-2.c: Regenerated.
 888         * aarch64-opc-2.c: Regenerated.
 889         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 890         (aarch64_encode_variant_using_iclass): Handle
 891         sve_shift_tsz_hsd iclass encode.
 892         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 893         sve_shift_tsz_hsd iclass decode.
 894         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 895         for SVE_SHRIMM_UNPRED_22.
 896         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 897         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 898         operand.
 899
 900 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 901
 902         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 903         sve_size_013 iclass encode.
 904         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 905         sve_size_013 iclass decode.
 906
 907 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 908
 909         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 910         sve_size_bh iclass encode.
 911         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 912         sve_size_bh iclass decode.
 913
 914 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 915
 916         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 917         sve_size_sd2 iclass encode.
 918         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 919         sve_size_sd2 iclass decode.
 920         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 921         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 922
 923 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 924
 925         * aarch64-asm-2.c: Regenerated.
 926         * aarch64-dis-2.c: Regenerated.
 927         * aarch64-opc-2.c: Regenerated.
 928         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 929         for SVE_ADDR_ZX.
 930         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 931         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 932
 933 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 934
 935         * aarch64-asm-2.c: Regenerated.
 936         * aarch64-dis-2.c: Regenerated.
 937         * aarch64-opc-2.c: Regenerated.
 938         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 939         for SVE_Zm3_11_INDEX.
 940         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 941         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 942         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 943         fields.
 944         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 945
 946 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 947
 948         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 949         sve_size_hsd2 iclass encode.
 950         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 951         sve_size_hsd2 iclass decode.
 952         * aarch64-opc.c (fields): Handle SVE_size field.
 953         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 954
 955 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 956
 957         * aarch64-asm-2.c: Regenerated.
 958         * aarch64-dis-2.c: Regenerated.
 959         * aarch64-opc-2.c: Regenerated.
 960         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 961         for SVE_IMM_ROT3.
 962         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 963         (fields): Handle SVE_rot3 field.
 964         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 965         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 966
 967 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 968
 969         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 970         instructions.
 971
 972 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 973
 974         * aarch64-tbl.h
 975         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 976         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 977         aarch64_feature_sve2bitperm): New feature sets.
 978         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 979         for feature set addresses.
 980         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 981         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 982
 983 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 984             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 985
 986         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 987         argument and set ASE_EVA_R6 appropriately.
 988         (set_default_mips_dis_options): Pass ISA to above.
 989         (parse_mips_dis_option): Likewise.
 990         * mips-opc.c (EVAR6): New macro.
 991         (mips_builtin_opcodes): Add llwpe, scwpe.
 992
 993 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 994
 995         * aarch64-asm-2.c: Regenerated.
 996         * aarch64-dis-2.c: Regenerated.
 997         * aarch64-opc-2.c: Regenerated.
 998         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 999         AARCH64_OPND_TME_UIMM16.
1000         (aarch64_print_operand): Likewise.
1001         * aarch64-tbl.h (QL_IMM_NIL): New.
1002         (TME): New.
1003         (_TME_INSN): New.
1004         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1005
1006 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1007
1008         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1009
1010 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1011             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1012
1013         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1014
1015 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1016
1017         * s12z-opc.h: Add extern "C" bracketing to help
1018         users who wish to use this interface in c++ code.
1019
1020 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1021
1022         * s12z-opc.c (bm_decode): Handle bit map operations with the
1023         "reserved0" mode.
1024
1025 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1026
1027         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1028         specifier.  Add entries for VLDR and VSTR of system registers.
1029         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1030         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1031         of %J and %K format specifier.
1032
1033 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1034
1035         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1036         Add new entries for VSCCLRM instruction.
1037         (print_insn_coprocessor): Handle new %C format control code.
1038
1039 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1040
1041         * arm-dis.c (enum isa): New enum.
1042         (struct sopcode32): New structure.
1043         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1044         set isa field of all current entries to ANY.
1045         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1046         Only match an entry if its isa field allows the current mode.
1047
1048 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1049
1050         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1051         CLRM.
1052         (print_insn_thumb32): Add logic to print %n CLRM register list.
1053
1054 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1055
1056         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1057         and %Q patterns.
1058
1059 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1060
1061         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1062         (print_insn_thumb32): Edit the switch case for %Z.
1063
1064 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1065
1066         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1067
1068 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1069
1070         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1071
1072 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1073
1074         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1075
1076 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1077
1078         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1079         Arm register with r13 and r15 unpredictable.
1080         (thumb32_opcodes): New instructions for bfx and bflx.
1081
1082 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1083
1084         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1085
1086 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1087
1088         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1089
1090 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1091
1092         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1093
1094 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1095
1096         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1097
1098 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1099
1100         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1101         "optr". ("operator" is a reserved word in c++).
1102
1103 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1104
1105         * aarch64-opc.c (aarch64_print_operand): Add case for
1106         AARCH64_OPND_Rt_SP.
1107         (verify_constraints): Likewise.
1108         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1109         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1110         to accept Rt|SP as first operand.
1111         (AARCH64_OPERANDS): Add new Rt_SP.
1112         * aarch64-asm-2.c: Regenerated.
1113         * aarch64-dis-2.c: Regenerated.
1114         * aarch64-opc-2.c: Regenerated.
1115
1116 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1117
1118         * aarch64-asm-2.c: Regenerated.
1119         * aarch64-dis-2.c: Likewise.
1120         * aarch64-opc-2.c: Likewise.
1121         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1122
1123 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1124
1125         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1126
1127 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1128
1129         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1130         * i386-init.h: Regenerated.
1131
1132 2019-04-07  Alan Modra  <amodra@gmail.com>
1133
1134         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1135         op_separator to control printing of spaces, comma and parens
1136         rather than need_comma, need_paren and spaces vars.
1137
1138 2019-04-07  Alan Modra  <amodra@gmail.com>
1139
1140         PR 24421
1141         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1142         (print_insn_neon, print_insn_arm): Likewise.
1143
1144 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1145
1146         * i386-dis-evex.h (evex_table): Updated to support BF16
1147         instructions.
1148         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1149         and EVEX_W_0F3872_P_3.
1150         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1151         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1152         * i386-opc.h (enum): Add CpuAVX512_BF16.
1153         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1154         * i386-opc.tbl: Add AVX512 BF16 instructions.
1155         * i386-init.h: Regenerated.
1156         * i386-tbl.h: Likewise.
1157
1158 2019-04-05  Alan Modra  <amodra@gmail.com>
1159
1160         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1161         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1162         to favour printing of "-" branch hint when using the "y" bit.
1163         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1164
1165 2019-04-05  Alan Modra  <amodra@gmail.com>
1166
1167         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1168         opcode until first operand is output.
1169
1170 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1171
1172         PR gas/24349
1173         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1174         (valid_bo_post_v2): Add support for 'at' branch hints.
1175         (insert_bo): Only error on branch on ctr.
1176         (get_bo_hint_mask): New function.
1177         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1178         for inserting 'at' branch hints.
1179         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1180         for extracting 'at' branch hints.
1181         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1182         (BOE): Delete operand.
1183         (BOM, BOP): New operands.
1184         (RM): Update value.
1185         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1186         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1187         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1188         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1189         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1190         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1191         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1192         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1193         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1194         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1195         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1196         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1197         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1198         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1199         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1200         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1201         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1202         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1203         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1204         bttarl+>: New extended mnemonics.
1205
1206 2019-03-28  Alan Modra  <amodra@gmail.com>
1207
1208         PR 24390
1209         * ppc-opc.c (BTF): Define.
1210         (powerpc_opcodes): Use for mtfsb*.
1211         * ppc-dis.c (print_insn_powerpc): Print fields with both
1212         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1213
1214 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1215
1216         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1217         (mapping_symbol_for_insn): Implement new algorithm.
1218         (print_insn): Remove duplicate code.
1219
1220 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1221
1222         * aarch64-dis.c (print_insn_aarch64):
1223         Implement override.
1224
1225 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1226
1227         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1228         order.
1229
1230 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1231
1232         * aarch64-dis.c (last_stop_offset): New.
1233         (print_insn_aarch64): Use stop_offset.
1234
1235 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1236
1237         PR gas/24359
1238         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1239         CPU_ANY_AVX2_FLAGS.
1240         * i386-init.h: Regenerated.
1241
1242 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1243
1244         PR gas/24348
1245         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1246         vmovdqu16, vmovdqu32 and vmovdqu64.
1247         * i386-tbl.h: Regenerated.
1248
1249 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1250
1251         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1252         from vstrszb, vstrszh, and vstrszf.
1253
1254 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1255
1256         * s390-opc.txt: Add instruction descriptions.
1257
1258 2019-02-08  Jim Wilson  <jimw@sifive.com>
1259
1260         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1261         <bne>: Likewise.
1262
1263 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1264
1265         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1266
1267 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1268
1269         PR binutils/23212
1270         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1271         * aarch64-opc.c (verify_elem_sd): New.
1272         (fields): Add FLD_sz entr.
1273         * aarch64-tbl.h (_SIMD_INSN): New.
1274         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1275         fmulx scalar and vector by element isns.
1276
1277 2019-02-07  Nick Clifton  <nickc@redhat.com>
1278
1279         * po/sv.po: Updated Swedish translation.
1280
1281 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1282
1283         * s390-mkopc.c (main): Accept arch13 as cpu string.
1284         * s390-opc.c: Add new instruction formats and instruction opcode
1285         masks.
1286         * s390-opc.txt: Add new arch13 instructions.
1287
1288 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1289
1290         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1291         (aarch64_opcode): Change encoding for stg, stzg
1292         st2g and st2zg.
1293         * aarch64-asm-2.c: Regenerated.
1294         * aarch64-dis-2.c: Regenerated.
1295         * aarch64-opc-2.c: Regenerated.
1296
1297 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1298
1299         * aarch64-asm-2.c: Regenerated.
1300         * aarch64-dis-2.c: Likewise.
1301         * aarch64-opc-2.c: Likewise.
1302         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1303
1304 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1305             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1306
1307         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1308         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1309         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1310         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1311         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1312         case for ldstgv_indexed.
1313         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1314         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1315         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1316         * aarch64-asm-2.c: Regenerated.
1317         * aarch64-dis-2.c: Regenerated.
1318         * aarch64-opc-2.c: Regenerated.
1319
1320 2019-01-23  Nick Clifton  <nickc@redhat.com>
1321
1322         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1323
1324 2019-01-21  Nick Clifton  <nickc@redhat.com>
1325
1326         * po/de.po: Updated German translation.
1327         * po/uk.po: Updated Ukranian translation.
1328
1329 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1330         * mips-dis.c (mips_arch_choices): Fix typo in
1331         gs464, gs464e and gs264e descriptors.
1332
1333 2019-01-19  Nick Clifton  <nickc@redhat.com>
1334
1335         * configure: Regenerate.
1336         * po/opcodes.pot: Regenerate.
1337
1338 2018-06-24  Nick Clifton  <nickc@redhat.com>
1339
1340         2.32 branch created.
1341
1342 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1343
1344         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1345         if it is null.
1346         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1347         zero.
1348
1349 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1350
1351         * configure: Regenerate.
1352
1353 2019-01-07  Alan Modra  <amodra@gmail.com>
1354
1355         * configure: Regenerate.
1356         * po/POTFILES.in: Regenerate.
1357
1358 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1359
1360         * s12z-opc.c: New file.
1361         * s12z-opc.h: New file.
1362         * s12z-dis.c: Removed all code not directly related to display
1363         of instructions.  Used the interface provided by the new files
1364         instead.
1365         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1366         * Makefile.in: Regenerate.
1367         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1368         * configure: Regenerate.
1369
1370 2019-01-01  Alan Modra  <amodra@gmail.com>
1371
1372         Update year range in copyright notice of all files.
1373
1374 For older changes see ChangeLog-2018
1375 \f
1376 Copyright (C) 2019 Free Software Foundation, Inc.
1377
1378 Copying and distribution of this file, with or without modification,
1379 are permitted in any medium without royalty provided the copyright
1380 notice and this notice are preserved.
1381
1382 Local Variables:
1383 mode: change-log
1384 left-margin: 8
1385 fill-column: 74
1386 version-control: never
1387 End: