opcodes/ChangeLog

   1 2017-11-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
   4         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
   5         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
   6         vpcmpw): Move up.
   7         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
   8         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
   9         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
  10         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
  11         vpcmpnltuw): New.
  12         * i386-tbl.h: Re-generate.
  13
  14 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
  17         smov, ssca, stos, ssto, xlat): Drop Disp*.
  18         * i386-tbl.h: Re-generate.
  19
  20 2017-11-13  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
  23         xsaveopt64): Add No_qSuf.
  24         * i386-tbl.h: Re-generate.
  25
  26 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  27
  28         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
  29         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
  30         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
  31         sder32_el2, vncr_el2.
  32         (aarch64_sys_reg_supported_p): Likewise.
  33         (aarch64_pstatefields): Add dit register.
  34         (aarch64_pstatefield_supported_p): Likewise.
  35         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
  36         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
  37         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
  38         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
  39         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
  40         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
  41         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
  42
  43 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  44
  45         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
  46         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
  47         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
  48         (QL_STLW, QL_STLX): New.
  49
  50 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  51
  52         * aarch64-asm.h (ins_addr_offset): New.
  53         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
  54         (aarch64_ins_addr_offset): New.
  55         * aarch64-asm-2.c: Regenerate.
  56         * aarch64-dis.h (ext_addr_offset): New.
  57         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
  58         (aarch64_ext_addr_offset): New.
  59         * aarch64-dis-2.c: Regenerate.
  60         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
  61         FLD_imm4_2 and FLD_SM3_imm2.
  62         * aarch64-opc.c (fields): Add FLD_imm6_2,
  63         FLD_imm4_2 and FLD_SM3_imm2.
  64         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
  65         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
  66         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
  67         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
  68         * aarch64-tbl.h
  69         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
  70
  71 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
  72
  73         * aarch64-tbl.h
  74         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
  75         (aarch64_feature_sm4, aarch64_feature_sha3): New.
  76         (aarch64_feature_fp_16_v8_2): New.
  77         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
  78         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
  79         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
  80
  81 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
  82
  83         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
  84         (aarch64_feature_sha2, aarch64_feature_aes): New.
  85         (SHA2, AES): New.
  86         (AES_INSN, SHA2_INSN): New.
  87         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
  88         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
  89          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
  90         Change to SHA2_INS.
  91
  92 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
  93             Tamar Christina <tamar.christina@arm.com>
  94
  95         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
  96         FP16 instructions, including vfmal.f16 and vfmsl.f16.
  97
  98 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
  99
 100         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 101
 102 2017-11-07  Alan Modra  <amodra@gmail.com>
 103
 104         * opintl.h: Formatting, comment fixes.
 105         (gettext, ngettext): Redefine when ENABLE_NLS.
 106         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 107         (_): Define using gettext.
 108         (textdomain, bindtextdomain): Use safer "do nothing".
 109
 110 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 111
 112         * arc-dis.c (print_hex): New variable.
 113         (parse_option): Check for hex option.
 114         (print_insn_arc): Use hexadecimal representation for short
 115         immediate values when requested.
 116         (print_arc_disassembler_options): Add hex option to the list.
 117
 118 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 119
 120         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 121         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 122         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 123         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 124         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 125         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 126         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 127         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 128         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 129         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 130         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 131         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 132         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 133         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 134         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 135         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 136         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 137         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 138         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 139         Changed opcodes.
 140         (prealloc, prefetch*): Place them before ld instruction.
 141         * arc-opc.c (skip_this_opcode): Add ARITH class.
 142
 143 2017-10-25  Alan Modra  <amodra@gmail.com>
 144
 145         PR 22348
 146         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 147         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 148         (imm4flag, size_changed): Likewise.
 149         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 150         (words, allWords, processing_argument_number): Likewise.
 151         (cst4flag, size_changed): Likewise.
 152         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 153         (crx_cst4_maps): Rename from cst4_maps.
 154         (crx_no_op_insn): Rename from no_op_insn.
 155
 156 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 157
 158         * riscv-opc.c (match_c_addi16sp) : New function.
 159         (match_c_addi4spn): New function.
 160         (match_c_lui): Don't allow 0-immediate encodings.
 161         (riscv_opcodes) <addi>: Use the above functions.
 162         <add>: Likewise.
 163         <c.addi4spn>: Likewise.
 164         <c.addi16sp>: Likewise.
 165
 166 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 167
 168         * i386-init.h: Regenerate
 169         * i386-tbl.h: Likewise
 170
 171 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 172
 173         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 174         (enum): Add EVEX_W_0F3854_P_2.
 175         * i386-dis-evex.h (evex_table): Updated.
 176         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 177         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 178         (cpu_flags): Add CpuAVX512_BITALG.
 179         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 180         (i386_cpu_flags): Add cpuavx512_bitalg..
 181         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 182         * i386-init.h: Regenerate.
 183         * i386-tbl.h: Likewise.
 184
 185 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 186
 187         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 188         * i386-dis-evex.h (evex_table): Updated.
 189         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 190         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 191         (cpu_flags): Add CpuAVX512_VNNI.
 192         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 193         (i386_cpu_flags): Add cpuavx512_vnni.
 194         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 195         * i386-init.h: Regenerate.
 196         * i386-tbl.h: Likewise.
 197
 198 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 199
 200         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 201         (enum): Remove VEX_LEN_0F3A44_P_2.
 202         (vex_len_table): Ditto.
 203         (enum): Remove VEX_W_0F3A44_P_2.
 204         (vew_w_table): Ditto.
 205         (prefix_table): Adjust instructions (see prefixes above).
 206         * i386-dis-evex.h (evex_table):
 207         Add new instructions (see prefixes above).
 208         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 209         (bitfield_cpu_flags): Ditto.
 210         * i386-opc.h (enum): Ditto.
 211         (i386_cpu_flags): Ditto.
 212         (CpuUnused): Comment out to avoid zero-width field problem.
 213         * i386-opc.tbl (vpclmulqdq): New instruction.
 214         * i386-init.h: Regenerate.
 215         * i386-tbl.h: Ditto.
 216
 217 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 218
 219         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 220         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 221         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 222         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 223         (vex_len_table): Ditto.
 224         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 225         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 226         (vew_w_table): Ditto.
 227         (prefix_table): Adjust instructions (see prefixes above).
 228         * i386-dis-evex.h (evex_table):
 229         Add new instructions (see prefixes above).
 230         * i386-gen.c (cpu_flag_init): Add VAES.
 231         (bitfield_cpu_flags): Ditto.
 232         * i386-opc.h (enum): Ditto.
 233         (i386_cpu_flags): Ditto.
 234         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 235         * i386-init.h: Regenerate.
 236         * i386-tbl.h: Ditto.
 237
 238 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 239
 240         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 241         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 242         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 243         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 244         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 245         (prefix_table): Updated (see prefixes above).
 246         (three_byte_table): Likewise.
 247         (vex_w_table): Likewise.
 248         * i386-dis-evex.h: Likewise.
 249         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 250         (cpu_flags): Add CpuGFNI.
 251         * i386-opc.h (enum): Add CpuGFNI.
 252         (i386_cpu_flags): Add cpugfni.
 253         * i386-opc.tbl: Add Intel GFNI instructions.
 254         * i386-init.h: Regenerate.
 255         * i386-tbl.h: Likewise.
 256
 257 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 258
 259         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 260         Define EXbScalar and EXwScalar for OP_EX.
 261         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 262         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 263         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 264         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 265         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 266         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 267         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 268         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 269         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 270         (OP_E_memory): Likewise.
 271         * i386-dis-evex.h: Updated.
 272         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 273         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 274         (cpu_flags): Add CpuAVX512_VBMI2.
 275         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 276         (i386_cpu_flags): Add cpuavx512_vbmi2.
 277         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 278         * i386-init.h: Regenerate.
 279         * i386-tbl.h: Likewise.
 280
 281 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 282
 283         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 284
 285 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 286
 287         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 288         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 289         K15. Add jmpix pattern.
 290
 291 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 292
 293         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 294
 295 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 296
 297         * s390-opc.c (INSTR_SI_RD): New macro.
 298         (INSTR_S_RD): Adjust example instruction.
 299         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 300         SI_RD.
 301
 302 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 303
 304         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 305         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 306         VLE multimple load/store instructions. Old e_ldm* variants are
 307         kept as aliases.
 308         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 309
 310 2017-09-27  Nick Clifton  <nickc@redhat.com>
 311
 312         PR 22179
 313         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 314         names for the fmv.x.s and fmv.s.x instructions respectively.
 315
 316 2017-09-26  do  <do@nerilex.org>
 317
 318         PR 22123
 319         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 320         be used on CPUs that have emacs support.
 321
 322 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 323
 324         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 325
 326 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 327
 328         * nds32-asm.c: Rename __BIT() to N32_BIT().
 329         * nds32-asm.h: Likewise.
 330         * nds32-dis.c: Likewise.
 331
 332 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-dis.c (last_active_prefix): Removed.
 335         (ckprefix): Don't set last_active_prefix.
 336         (NOTRACK_Fixup): Don't check last_active_prefix.
 337
 338 2017-08-31  Nick Clifton  <nickc@redhat.com>
 339
 340         * po/fr.po: Updated French translation.
 341
 342 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 343
 344         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 345         fields.
 346
 347 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 348             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 349
 350         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 351         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 352         New entries efs2 and spe2.
 353         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 354         (SPE2_OPCD_SEGS): New macro.
 355         (spe2_opcd_indices): New.
 356         (disassemble_init_powerpc): Handle SPE2 opcodes.
 357         (lookup_spe2): New function.
 358         (print_insn_powerpc): call lookup_spe2.
 359         * ppc-opc.c (insert_evuimm1_ex0): New function.
 360         (extract_evuimm1_ex0): Likewise.
 361         (insert_evuimm_lt8): Likewise.
 362         (extract_evuimm_lt8): Likewise.
 363         (insert_off_spe2): Likewise.
 364         (extract_off_spe2): Likewise.
 365         (insert_Ddd): Likewise.
 366         (extract_Ddd): Likewise.
 367         (DD): New operand.
 368         (EVUIMM_LT8): Likewise.
 369         (EVUIMM_LT16): Adjust.
 370         (MMMM): New operand.
 371         (EVUIMM_1): Likewise.
 372         (EVUIMM_1_EX0): Likewise.
 373         (EVUIMM_2): Adjust.
 374         (NNN): New operand.
 375         (VX_OFF_SPE2): Likewise.
 376         (BBB): Likewise.
 377         (DDD): Likewise.
 378         (VX_MASK_DDD): New mask.
 379         (HH): New operand.
 380         (VX_RA_CONST): New macro.
 381         (VX_RA_CONST_MASK): Likewise.
 382         (VX_RB_CONST): Likewise.
 383         (VX_RB_CONST_MASK): Likewise.
 384         (VX_OFF_SPE2_MASK): Likewise.
 385         (VX_SPE_CRFD): Likewise.
 386         (VX_SPE_CRFD_MASK VX): Likewise.
 387         (VX_SPE2_CLR): Likewise.
 388         (VX_SPE2_CLR_MASK): Likewise.
 389         (VX_SPE2_SPLATB): Likewise.
 390         (VX_SPE2_SPLATB_MASK): Likewise.
 391         (VX_SPE2_OCTET): Likewise.
 392         (VX_SPE2_OCTET_MASK): Likewise.
 393         (VX_SPE2_DDHH): Likewise.
 394         (VX_SPE2_DDHH_MASK): Likewise.
 395         (VX_SPE2_HH): Likewise.
 396         (VX_SPE2_HH_MASK): Likewise.
 397         (VX_SPE2_EVMAR): Likewise.
 398         (VX_SPE2_EVMAR_MASK): Likewise.
 399         (PPCSPE2): Likewise.
 400         (PPCEFS2): Likewise.
 401         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 402         (powerpc_macros): Map old SPE instructions have new names
 403         with the same opcodes. Add SPE2 instructions which just are
 404         mapped to SPE2.
 405         (spe2_opcodes): Add SPE2 opcodes.
 406
 407 2017-08-23  Alan Modra  <amodra@gmail.com>
 408
 409         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 410         extract functions earlier, deleting forward declarations.
 411         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 412         RA_MASK.
 413
 414 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 415
 416         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 417
 418 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 419             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 420
 421         * ppc-opc.c (insert_evuimm2_ex0): New function.
 422         (extract_evuimm2_ex0): Likewise.
 423         (insert_evuimm4_ex0): Likewise.
 424         (extract_evuimm4_ex0): Likewise.
 425         (insert_evuimm8_ex0): Likewise.
 426         (extract_evuimm8_ex0): Likewise.
 427         (insert_evuimm_lt16): Likewise.
 428         (extract_evuimm_lt16): Likewise.
 429         (insert_rD_rS_even): Likewise.
 430         (extract_rD_rS_even): Likewise.
 431         (insert_off_lsp): Likewise.
 432         (extract_off_lsp): Likewise.
 433         (RD_EVEN): New operand.
 434         (RS_EVEN): Likewise.
 435         (RSQ): Adjust.
 436         (EVUIMM_LT16): New operand.
 437         (HTM_SI): Adjust.
 438         (EVUIMM_2_EX0): New operand.
 439         (EVUIMM_4): Adjust.
 440         (EVUIMM_4_EX0): New operand.
 441         (EVUIMM_8): Adjust.
 442         (EVUIMM_8_EX0): New operand.
 443         (WS): Adjust.
 444         (VX_OFF): New operand.
 445         (VX_LSP): New macro.
 446         (VX_LSP_MASK): Likewise.
 447         (VX_LSP_OFF_MASK): Likewise.
 448         (PPC_OPCODE_LSP): Likewise.
 449         (vle_opcodes): Add LSP opcodes.
 450         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 451
 452 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 453
 454         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 455         register operands in CRC instructions.
 456         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 457         comments.
 458
 459 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         * disassemble.c (disassembler): Mark big and mach with
 462         ATTRIBUTE_UNUSED.
 463
 464 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 465
 466         * disassemble.c (disassembler): Remove arch/mach/endian
 467         assertions.
 468
 469 2017-07-25  Nick Clifton  <nickc@redhat.com>
 470
 471         PR 21739
 472         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 473         message.
 474         (insert_r0): Likewise.
 475         (insert_r1): Likewise.
 476         (insert_r2): Likewise.
 477         (insert_r3): Likewise.
 478         (insert_sp): Likewise.
 479         (insert_gp): Likewise.
 480         (insert_pcl): Likewise.
 481         (insert_blink): Likewise.
 482         (insert_ilink1): Likewise.
 483         (insert_ilink2): Likewise.
 484         (insert_ras): Likewise.
 485         (insert_rbs): Likewise.
 486         (insert_rcs): Likewise.
 487         (insert_simm3s): Likewise.
 488         (insert_rrange): Likewise.
 489         (insert_r13el): Likewise.
 490         (insert_fpel): Likewise.
 491         (insert_blinkel): Likewise.
 492         (insert_pclel): Likewise.
 493         (insert_nps_bitop_size_2b): Likewise.
 494         (insert_nps_imm_offset): Likewise.
 495         (insert_nps_imm_entry): Likewise.
 496         (insert_nps_size_16bit): Likewise.
 497         (insert_nps_##NAME##_pos): Likewise.
 498         (insert_nps_##NAME): Likewise.
 499         (insert_nps_bitop_ins_ext): Likewise.
 500         (insert_nps_##NAME): Likewise.
 501         (insert_nps_min_hofs): Likewise.
 502         (insert_nps_##NAME): Likewise.
 503         (insert_nps_rbdouble_64): Likewise.
 504         (insert_nps_misc_imm_offset): Likewise.
 505         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 506         option description.
 507
 508 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 509             Jiong Wang  <jiong.wang@arm.com>
 510
 511         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 512         correct the print.
 513         * aarch64-dis-2.c: Regenerated.
 514
 515 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 516
 517         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 518         table.
 519
 520 2017-07-20  Nick Clifton  <nickc@redhat.com>
 521
 522         * po/de.po: Updated German translation.
 523
 524 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 525
 526         * arc-regs.h (sec_stat): New aux register.
 527         (aux_kernel_sp): Likewise.
 528         (aux_sec_u_sp): Likewise.
 529         (aux_sec_k_sp): Likewise.
 530         (sec_vecbase_build): Likewise.
 531         (nsc_table_top): Likewise.
 532         (nsc_table_base): Likewise.
 533         (ersec_stat): Likewise.
 534         (aux_sec_except): Likewise.
 535
 536 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 537
 538         * arc-opc.c (extract_uimm12_20): New function.
 539         (UIMM12_20): New operand.
 540         (SIMM3_5_S): Adjust.
 541         * arc-tbl.h (sjli): Add new instruction.
 542
 543 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 544             John Eric Martin  <John.Martin@emmicro-us.com>
 545
 546         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 547         (UIMM3_23): Adjust accordingly.
 548         * arc-regs.h: Add/correct jli_base register.
 549         * arc-tbl.h (jli_s): Likewise.
 550
 551 2017-07-18  Nick Clifton  <nickc@redhat.com>
 552
 553         PR 21775
 554         * aarch64-opc.c: Fix spelling typos.
 555         * i386-dis.c: Likewise.
 556
 557 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 558
 559         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 560         max_addr_offset and octets variables to size_t.
 561
 562 2017-07-12  Alan Modra  <amodra@gmail.com>
 563
 564         * po/da.po: Update from translationproject.org/latest/opcodes/.
 565         * po/de.po: Likewise.
 566         * po/es.po: Likewise.
 567         * po/fi.po: Likewise.
 568         * po/fr.po: Likewise.
 569         * po/id.po: Likewise.
 570         * po/it.po: Likewise.
 571         * po/nl.po: Likewise.
 572         * po/pt_BR.po: Likewise.
 573         * po/ro.po: Likewise.
 574         * po/sv.po: Likewise.
 575         * po/tr.po: Likewise.
 576         * po/uk.po: Likewise.
 577         * po/vi.po: Likewise.
 578         * po/zh_CN.po: Likewise.
 579
 580 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 581             Alan Modra  <amodra@gmail.com>
 582
 583         * cgen.sh: Mark generated files read-only.
 584         * epiphany-asm.c: Regenerate.
 585         * epiphany-desc.c: Regenerate.
 586         * epiphany-desc.h: Regenerate.
 587         * epiphany-dis.c: Regenerate.
 588         * epiphany-ibld.c: Regenerate.
 589         * epiphany-opc.c: Regenerate.
 590         * epiphany-opc.h: Regenerate.
 591         * fr30-asm.c: Regenerate.
 592         * fr30-desc.c: Regenerate.
 593         * fr30-desc.h: Regenerate.
 594         * fr30-dis.c: Regenerate.
 595         * fr30-ibld.c: Regenerate.
 596         * fr30-opc.c: Regenerate.
 597         * fr30-opc.h: Regenerate.
 598         * frv-asm.c: Regenerate.
 599         * frv-desc.c: Regenerate.
 600         * frv-desc.h: Regenerate.
 601         * frv-dis.c: Regenerate.
 602         * frv-ibld.c: Regenerate.
 603         * frv-opc.c: Regenerate.
 604         * frv-opc.h: Regenerate.
 605         * ip2k-asm.c: Regenerate.
 606         * ip2k-desc.c: Regenerate.
 607         * ip2k-desc.h: Regenerate.
 608         * ip2k-dis.c: Regenerate.
 609         * ip2k-ibld.c: Regenerate.
 610         * ip2k-opc.c: Regenerate.
 611         * ip2k-opc.h: Regenerate.
 612         * iq2000-asm.c: Regenerate.
 613         * iq2000-desc.c: Regenerate.
 614         * iq2000-desc.h: Regenerate.
 615         * iq2000-dis.c: Regenerate.
 616         * iq2000-ibld.c: Regenerate.
 617         * iq2000-opc.c: Regenerate.
 618         * iq2000-opc.h: Regenerate.
 619         * lm32-asm.c: Regenerate.
 620         * lm32-desc.c: Regenerate.
 621         * lm32-desc.h: Regenerate.
 622         * lm32-dis.c: Regenerate.
 623         * lm32-ibld.c: Regenerate.
 624         * lm32-opc.c: Regenerate.
 625         * lm32-opc.h: Regenerate.
 626         * lm32-opinst.c: Regenerate.
 627         * m32c-asm.c: Regenerate.
 628         * m32c-desc.c: Regenerate.
 629         * m32c-desc.h: Regenerate.
 630         * m32c-dis.c: Regenerate.
 631         * m32c-ibld.c: Regenerate.
 632         * m32c-opc.c: Regenerate.
 633         * m32c-opc.h: Regenerate.
 634         * m32r-asm.c: Regenerate.
 635         * m32r-desc.c: Regenerate.
 636         * m32r-desc.h: Regenerate.
 637         * m32r-dis.c: Regenerate.
 638         * m32r-ibld.c: Regenerate.
 639         * m32r-opc.c: Regenerate.
 640         * m32r-opc.h: Regenerate.
 641         * m32r-opinst.c: Regenerate.
 642         * mep-asm.c: Regenerate.
 643         * mep-desc.c: Regenerate.
 644         * mep-desc.h: Regenerate.
 645         * mep-dis.c: Regenerate.
 646         * mep-ibld.c: Regenerate.
 647         * mep-opc.c: Regenerate.
 648         * mep-opc.h: Regenerate.
 649         * mt-asm.c: Regenerate.
 650         * mt-desc.c: Regenerate.
 651         * mt-desc.h: Regenerate.
 652         * mt-dis.c: Regenerate.
 653         * mt-ibld.c: Regenerate.
 654         * mt-opc.c: Regenerate.
 655         * mt-opc.h: Regenerate.
 656         * or1k-asm.c: Regenerate.
 657         * or1k-desc.c: Regenerate.
 658         * or1k-desc.h: Regenerate.
 659         * or1k-dis.c: Regenerate.
 660         * or1k-ibld.c: Regenerate.
 661         * or1k-opc.c: Regenerate.
 662         * or1k-opc.h: Regenerate.
 663         * or1k-opinst.c: Regenerate.
 664         * xc16x-asm.c: Regenerate.
 665         * xc16x-desc.c: Regenerate.
 666         * xc16x-desc.h: Regenerate.
 667         * xc16x-dis.c: Regenerate.
 668         * xc16x-ibld.c: Regenerate.
 669         * xc16x-opc.c: Regenerate.
 670         * xc16x-opc.h: Regenerate.
 671         * xstormy16-asm.c: Regenerate.
 672         * xstormy16-desc.c: Regenerate.
 673         * xstormy16-desc.h: Regenerate.
 674         * xstormy16-dis.c: Regenerate.
 675         * xstormy16-ibld.c: Regenerate.
 676         * xstormy16-opc.c: Regenerate.
 677         * xstormy16-opc.h: Regenerate.
 678
 679 2017-07-07  Alan Modra  <amodra@gmail.com>
 680
 681         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 682         * m32c-dis.c: Regenerate.
 683         * mep-dis.c: Regenerate.
 684
 685 2017-07-05  Borislav Petkov  <bp@suse.de>
 686
 687         * i386-dis.c: Enable ModRM.reg /6 aliases.
 688
 689 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 690
 691         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 692         with vmrs and vmsr.
 693
 694 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 695
 696         * configure: Regenerate.
 697
 698 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 699
 700         * po/opcodes.pot: Regenerate.
 701
 702 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 703
 704         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 705         entries to the MSA ASE instruction block.
 706
 707 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 708             Maciej W. Rozycki  <macro@imgtec.com>
 709
 710         * micromips-opc.c (XPA, XPAVZ): New macros.
 711         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 712         "mthgc0".
 713
 714 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 715             Maciej W. Rozycki  <macro@imgtec.com>
 716
 717         * micromips-opc.c (I36): New macro.
 718         (micromips_opcodes): Add "eretnc".
 719
 720 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 721             Andrew Bennett  <andrew.bennett@imgtec.com>
 722
 723         * mips-dis.c (mips_calculate_combination_ases): Handle the
 724         ASE_XPA_VIRT flag.
 725         (parse_mips_ase_option): New function.
 726         (parse_mips_dis_option): Factor out ASE option handling to the
 727         new function.  Call `mips_calculate_combination_ases'.
 728         * mips-opc.c (XPAVZ): New macro.
 729         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 730         "mfhgc0", "mthc0" and "mthgc0".
 731
 732 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 733
 734         * mips-dis.c (mips_calculate_combination_ases): New function.
 735         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 736         calculation to the new function.
 737         (set_default_mips_dis_options): Call the new function.
 738
 739 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 740
 741         * arc-dis.c (parse_disassembler_options): Use
 742         FOR_EACH_DISASSEMBLER_OPTION.
 743
 744 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 745
 746         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 747         disassembler option strings.
 748         (parse_cpu_option): Likewise.
 749
 750 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 751
 752         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 753         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 754         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 755         (aarch64_feature_dotprod, DOT_INSN): New.
 756         (udot, sdot): New.
 757         * aarch64-dis-2.c: Regenerated.
 758
 759 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 760
 761         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 762
 763 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 764             Matthew Fortune  <matthew.fortune@imgtec.com>
 765             Andrew Bennett  <andrew.bennett@imgtec.com>
 766
 767         * mips-formats.h (INT_BIAS): New macro.
 768         (INT_ADJ): Redefine in INT_BIAS terms.
 769         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 770         (mips_print_save_restore): New function.
 771         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 772         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 773         call.
 774         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 775         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 776         OP_SAVE_RESTORE_LIST handling, factored out from here.
 777         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 778         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 779         (mips_builtin_opcodes): Add "restore" and "save" entries.
 780         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 781         (IAMR2): New macro.
 782         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 783
 784 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 785
 786         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 787         alias; do not mark SLTI instruction as an alias.
 788
 789 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 790
 791         * i386-dis.c (RM_0FAE_REG_5): Removed.
 792         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 793         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 794         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 795         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 796         PREFIX_MOD_3_0F01_REG_5_RM_0.
 797         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 798         PREFIX_MOD_3_0FAE_REG_5.
 799         (mod_table): Update MOD_0FAE_REG_5.
 800         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 801         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 802         * i386-tbl.h: Regenerated.
 803
 804 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 805
 806         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 807         * i386-opc.tbl: Likewise.
 808         * i386-tbl.h: Regenerated.
 809
 810 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 811
 812         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 813         and "jmp{&|}".
 814         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 815         prefix.
 816
 817 2017-06-19  Nick Clifton  <nickc@redhat.com>
 818
 819         PR binutils/21614
 820         * score-dis.c (score_opcodes): Add sentinel.
 821
 822 2017-06-16  Alan Modra  <amodra@gmail.com>
 823
 824         * rx-decode.c: Regenerate.
 825
 826 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 827
 828         PR binutils/21594
 829         * i386-dis.c (OP_E_register): Check valid bnd register.
 830         (OP_G): Likewise.
 831
 832 2017-06-15  Nick Clifton  <nickc@redhat.com>
 833
 834         PR binutils/21595
 835         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 836         range value.
 837
 838 2017-06-15  Nick Clifton  <nickc@redhat.com>
 839
 840         PR binutils/21588
 841         * rl78-decode.opc (OP_BUF_LEN): Define.
 842         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 843         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 844         array.
 845         * rl78-decode.c: Regenerate.
 846
 847 2017-06-15  Nick Clifton  <nickc@redhat.com>
 848
 849         PR binutils/21586
 850         * bfin-dis.c (gregs): Clip index to prevent overflow.
 851         (regs): Likewise.
 852         (regs_lo): Likewise.
 853         (regs_hi): Likewise.
 854
 855 2017-06-14  Nick Clifton  <nickc@redhat.com>
 856
 857         PR binutils/21576
 858         * score7-dis.c (score_opcodes): Add sentinel.
 859
 860 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 861
 862         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 863         * arm-dis.c: Likewise.
 864         * ia64-dis.c: Likewise.
 865         * mips-dis.c: Likewise.
 866         * spu-dis.c: Likewise.
 867         * disassemble.h (print_insn_aarch64): New declaration, moved from
 868         include/dis-asm.h.
 869         (print_insn_big_arm, print_insn_big_mips): Likewise.
 870         (print_insn_i386, print_insn_ia64): Likewise.
 871         (print_insn_little_arm, print_insn_little_mips): Likewise.
 872
 873 2017-06-14  Nick Clifton  <nickc@redhat.com>
 874
 875         PR binutils/21587
 876         * rx-decode.opc: Include libiberty.h
 877         (GET_SCALE): New macro - validates access to SCALE array.
 878         (GET_PSCALE): New macro - validates access to PSCALE array.
 879         (DIs, SIs, S2Is, rx_disp): Use new macros.
 880         * rx-decode.c: Regenerate.
 881
 882 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 883
 884         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 885
 886 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 887
 888         * arc-dis.c (enforced_isa_mask): Declare.
 889         (cpu_types): Likewise.
 890         (parse_cpu_option): New function.
 891         (parse_disassembler_options): Use it.
 892         (print_insn_arc): Use enforced_isa_mask.
 893         (print_arc_disassembler_options): Document new options.
 894
 895 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 896
 897         * alpha-dis.c: Include disassemble.h, don't include
 898         dis-asm.h.
 899         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 900         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 901         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 902         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 903         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 904         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 905         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 906         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 907         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 908         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 909         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 910         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 911         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 912         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 913         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 914         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 915         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 916         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 917         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 918         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 919         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 920         * z80-dis.c, z8k-dis.c: Likewise.
 921         * disassemble.h: New file.
 922
 923 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 924
 925         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 926         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 927
 928 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 929
 930         * disassemble.c (disassembler): Add arguments a, big and mach.
 931         Use them.
 932
 933 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 934
 935         * i386-dis.c (NOTRACK_Fixup): New.
 936         (NOTRACK): Likewise.
 937         (NOTRACK_PREFIX): Likewise.
 938         (last_active_prefix): Likewise.
 939         (reg_table): Use NOTRACK on indirect call and jmp.
 940         (ckprefix): Set last_active_prefix.
 941         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 942         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 943         * i386-opc.h (NoTrackPrefixOk): New.
 944         (i386_opcode_modifier): Add notrackprefixok.
 945         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 946         Add notrack.
 947         * i386-tbl.h: Regenerated.
 948
 949 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 950
 951         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 952         (X_IMM2): Define.
 953         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 954         bfd_mach_sparc_v9m8.
 955         (print_insn_sparc): Handle new operand types.
 956         * sparc-opc.c (MASK_M8): Define.
 957         (v6): Add MASK_M8.
 958         (v6notlet): Likewise.
 959         (v7): Likewise.
 960         (v8): Likewise.
 961         (v9): Likewise.
 962         (v9a): Likewise.
 963         (v9b): Likewise.
 964         (v9c): Likewise.
 965         (v9d): Likewise.
 966         (v9e): Likewise.
 967         (v9v): Likewise.
 968         (v9m): Likewise.
 969         (v9andleon): Likewise.
 970         (m8): Define.
 971         (HWS_VM8): Define.
 972         (HWS2_VM8): Likewise.
 973         (sparc_opcode_archs): Add entry for "m8".
 974         (sparc_opcodes): Add OSA2017 and M8 instructions
 975         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 976         fpx{ll,ra,rl}64x,
 977         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 978         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 979         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 980         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 981         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 982         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 983         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 984         ASI_CORE_SELECT_COMMIT_NHT.
 985
 986 2017-05-18  Alan Modra  <amodra@gmail.com>
 987
 988         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 989         * aarch64-dis.c: Likewise.
 990         * aarch64-gen.c: Likewise.
 991         * aarch64-opc.c: Likewise.
 992
 993 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 994             Matthew Fortune  <matthew.fortune@imgtec.com>
 995
 996         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 997         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 998         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 999         (print_insn_arg) <OP_REG28>: Add handler.
1000         (validate_insn_args) <OP_REG28>: Handle.
1001         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1002         32-bit encoding and 9-bit immediates.
1003         (print_insn_mips16): Handle MIPS16 instructions that require
1004         32-bit encoding and MFC0/MTC0 operand decoding.
1005         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1006         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1007         (RD_C0, WR_C0, E2, E2MT): New macros.
1008         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1009         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1010         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1011         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1012         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1013         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1014         instructions, "swl", "swr", "sync" and its "sync_acquire",
1015         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1016         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1017         regular/extended entries for original MIPS16 ISA revision
1018         instructions whose extended forms are subdecoded in the MIPS16e2
1019         ISA revision: "li", "sll" and "srl".
1020
1021 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1022
1023         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1024         reference in CP0 move operand decoding.
1025
1026 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1027
1028         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1029         type to hexadecimal.
1030         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1031
1032 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1033
1034         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1035         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1036         "sync_rmb" and "sync_wmb" as aliases.
1037         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1038         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1039
1040 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1041
1042         * arc-dis.c (parse_option): Update quarkse_em option..
1043         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1044         QUARKSE1.
1045         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1046
1047 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1048
1049         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1050
1051 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1052
1053         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1054         register.
1055
1056 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1057
1058         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1059         and branches and not synthetic data instructions.
1060
1061 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1062
1063         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1064
1065 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1066
1067         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1068         * arc-opc.c (insert_r13el): New function.
1069         (R13_EL): Define.
1070         * arc-tbl.h: Add new enter/leave variants.
1071
1072 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1073
1074         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1075
1076 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1077
1078         * mips-dis.c (print_mips_disassembler_options): Add
1079         `no-aliases'.
1080
1081 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1082
1083         * mips16-opc.c (AL): New macro.
1084         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1085         of "ld" and "lw" as aliases.
1086
1087 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1088
1089         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1090         arguments.
1091
1092 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1093             Alan Modra  <amodra@gmail.com>
1094
1095         * ppc-opc.c (ELEV): Define.
1096         (vle_opcodes): Add se_rfgi and e_sc.
1097         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1098         for E200Z4.
1099
1100 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1101
1102         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1103
1104 2017-04-21  Nick Clifton  <nickc@redhat.com>
1105
1106         PR binutils/21380
1107         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1108         LD3R and LD4R.
1109
1110 2017-04-13  Alan Modra  <amodra@gmail.com>
1111
1112         * epiphany-desc.c: Regenerate.
1113         * fr30-desc.c: Regenerate.
1114         * frv-desc.c: Regenerate.
1115         * ip2k-desc.c: Regenerate.
1116         * iq2000-desc.c: Regenerate.
1117         * lm32-desc.c: Regenerate.
1118         * m32c-desc.c: Regenerate.
1119         * m32r-desc.c: Regenerate.
1120         * mep-desc.c: Regenerate.
1121         * mt-desc.c: Regenerate.
1122         * or1k-desc.c: Regenerate.
1123         * xc16x-desc.c: Regenerate.
1124         * xstormy16-desc.c: Regenerate.
1125
1126 2017-04-11  Alan Modra  <amodra@gmail.com>
1127
1128         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1129         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1130         PPC_OPCODE_TMR for e6500.
1131         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1132         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1133         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1134         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1135         (PPCHTM): Define as PPC_OPCODE_POWER8.
1136         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1137
1138 2017-04-10  Alan Modra  <amodra@gmail.com>
1139
1140         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1141         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1142         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1143         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1144
1145 2017-04-09  Pip Cet  <pipcet@gmail.com>
1146
1147         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1148         appropriate floating-point precision directly.
1149
1150 2017-04-07  Alan Modra  <amodra@gmail.com>
1151
1152         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1153         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1154         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1155         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1156         vector instructions with E6500 not PPCVEC2.
1157
1158 2017-04-06  Pip Cet  <pipcet@gmail.com>
1159
1160         * Makefile.am: Add wasm32-dis.c.
1161         * configure.ac: Add wasm32-dis.c to wasm32 target.
1162         * disassemble.c: Add wasm32 disassembler code.
1163         * wasm32-dis.c: New file.
1164         * Makefile.in: Regenerate.
1165         * configure: Regenerate.
1166         * po/POTFILES.in: Regenerate.
1167         * po/opcodes.pot: Regenerate.
1168
1169 2017-04-05  Pedro Alves  <palves@redhat.com>
1170
1171         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1172         * arm-dis.c (parse_arm_disassembler_options): Constify.
1173         * ppc-dis.c (powerpc_init_dialect): Constify local.
1174         * vax-dis.c (parse_disassembler_options): Constify.
1175
1176 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1177
1178         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1179         RISCV_GP_SYMBOL.
1180
1181 2017-03-30  Pip Cet  <pipcet@gmail.com>
1182
1183         * configure.ac: Add (empty) bfd_wasm32_arch target.
1184         * configure: Regenerate
1185         * po/opcodes.pot: Regenerate.
1186
1187 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1188
1189         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1190         OSA2015.
1191         * opcodes/sparc-opc.c (asi_table): New ASIs.
1192
1193 2017-03-29  Alan Modra  <amodra@gmail.com>
1194
1195         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1196         "raw" option.
1197         (lookup_powerpc): Don't special case -1 dialect.  Handle
1198         PPC_OPCODE_RAW.
1199         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1200         lookup_powerpc call, pass it on second.
1201
1202 2017-03-27  Alan Modra  <amodra@gmail.com>
1203
1204         PR 21303
1205         * ppc-dis.c (struct ppc_mopt): Comment.
1206         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1207
1208 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1209
1210         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1211         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1212         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1213         (insert_nps_misc_imm_offset): New function.
1214         (extract_nps_misc imm_offset): New function.
1215         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1216         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1217
1218 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1219
1220         * s390-mkopc.c (main): Remove vx2 check.
1221         * s390-opc.txt: Remove vx2 instruction flags.
1222
1223 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1224
1225         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1226         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1227         (insert_nps_imm_offset): New function.
1228         (extract_nps_imm_offset): New function.
1229         (insert_nps_imm_entry): New function.
1230         (extract_nps_imm_entry): New function.
1231
1232 2017-03-17  Alan Modra  <amodra@gmail.com>
1233
1234         PR 21248
1235         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1236         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1237         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1238
1239 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1240
1241         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1242         <c.andi>: Likewise.
1243         <c.addiw> Likewise.
1244
1245 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1246
1247         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1248
1249 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1250
1251         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1252         <srl> Likewise.
1253         <srai> Likewise.
1254         <sra> Likewise.
1255
1256 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1257
1258         * i386-gen.c (opcode_modifiers): Replace S with Load.
1259         * i386-opc.h (S): Removed.
1260         (Load): New.
1261         (i386_opcode_modifier): Replace s with load.
1262         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1263         and {evex}.  Replace S with Load.
1264         * i386-tbl.h: Regenerated.
1265
1266 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1267
1268         * i386-opc.tbl: Use CpuCET on rdsspq.
1269         * i386-tbl.h: Regenerated.
1270
1271 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1272
1273         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1274         <vsx>: Do not use PPC_OPCODE_VSX3;
1275
1276 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1277
1278         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1279
1280 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1281
1282         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1283         (MOD_0F1E_PREFIX_1): Likewise.
1284         (MOD_0F38F5_PREFIX_2): Likewise.
1285         (MOD_0F38F6_PREFIX_0): Likewise.
1286         (RM_0F1E_MOD_3_REG_7): Likewise.
1287         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1288         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1289         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1290         (PREFIX_0F1E): Likewise.
1291         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1292         (PREFIX_0F38F5): Likewise.
1293         (dis386_twobyte): Use PREFIX_0F1E.
1294         (reg_table): Add REG_0F1E_MOD_3.
1295         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1296         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1297         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1298         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1299         (three_byte_table): Use PREFIX_0F38F5.
1300         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1301         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1302         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1303         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1304         PREFIX_MOD_3_0F01_REG_5_RM_2.
1305         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1306         (cpu_flags): Add CpuCET.
1307         * i386-opc.h (CpuCET): New enum.
1308         (CpuUnused): Commented out.
1309         (i386_cpu_flags): Add cpucet.
1310         * i386-opc.tbl: Add Intel CET instructions.
1311         * i386-init.h: Regenerated.
1312         * i386-tbl.h: Likewise.
1313
1314 2017-03-06  Alan Modra  <amodra@gmail.com>
1315
1316         PR 21124
1317         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1318         (extract_raq, extract_ras, extract_rbx): New functions.
1319         (powerpc_operands): Use opposite corresponding insert function.
1320         (Q_MASK): Define.
1321         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1322         register restriction.
1323
1324 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1325
1326         * disassemble.c Include "safe-ctype.h".
1327         (disassemble_init_for_target): Handle s390 init.
1328         (remove_whitespace_and_extra_commas): New function.
1329         (disassembler_options_cmp): Likewise.
1330         * arm-dis.c: Include "libiberty.h".
1331         (NUM_ELEM): Delete.
1332         (regnames): Use long disassembler style names.
1333         Add force-thumb and no-force-thumb options.
1334         (NUM_ARM_REGNAMES): Rename from this...
1335         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1336         (get_arm_regname_num_options): Delete.
1337         (set_arm_regname_option): Likewise.
1338         (get_arm_regnames): Likewise.
1339         (parse_disassembler_options): Likewise.
1340         (parse_arm_disassembler_option): Rename from this...
1341         (parse_arm_disassembler_options): ...to this.  Make static.
1342         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1343         (print_insn): Use parse_arm_disassembler_options.
1344         (disassembler_options_arm): New function.
1345         (print_arm_disassembler_options): Handle updated regnames.
1346         * ppc-dis.c: Include "libiberty.h".
1347         (ppc_opts): Add "32" and "64" entries.
1348         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1349         (powerpc_init_dialect): Add break to switch statement.
1350         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1351         (disassembler_options_powerpc): New function.
1352         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1353         Remove printing of "32" and "64".
1354         * s390-dis.c: Include "libiberty.h".
1355         (init_flag): Remove unneeded variable.
1356         (struct s390_options_t): New structure type.
1357         (options): New structure.
1358         (init_disasm): Rename from this...
1359         (disassemble_init_s390): ...to this.  Add initializations for
1360         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1361         (print_insn_s390): Delete call to init_disasm.
1362         (disassembler_options_s390): New function.
1363         (print_s390_disassembler_options): Print using information from
1364         struct 'options'.
1365         * po/opcodes.pot: Regenerate.
1366
1367 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1368
1369         * i386-dis.c (PCMPESTR_Fixup): New.
1370         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1371         (prefix_table): Use PCMPESTR_Fixup.
1372         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1373         PCMPESTR_Fixup.
1374         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1375         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1376         Split 64-bit and non-64-bit variants.
1377         * opcodes/i386-tbl.h: Re-generate.
1378
1379 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1380
1381         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1382         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1383         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1384         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1385         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1386         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1387         (OP_SVE_V_HSD): New macros.
1388         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1389         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1390         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1391         (aarch64_opcode_table): Add new SVE instructions.
1392         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1393         for rotation operands.  Add new SVE operands.
1394         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1395         (ins_sve_quad_index): Likewise.
1396         (ins_imm_rotate): Split into...
1397         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1398         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1399         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1400         functions.
1401         (aarch64_ins_sve_addr_ri_s4): New function.
1402         (aarch64_ins_sve_quad_index): Likewise.
1403         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1404         * aarch64-asm-2.c: Regenerate.
1405         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1406         (ext_sve_quad_index): Likewise.
1407         (ext_imm_rotate): Split into...
1408         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1409         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1410         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1411         functions.
1412         (aarch64_ext_sve_addr_ri_s4): New function.
1413         (aarch64_ext_sve_quad_index): Likewise.
1414         (aarch64_ext_sve_index): Allow quad indices.
1415         (do_misc_decoding): Likewise.
1416         * aarch64-dis-2.c: Regenerate.
1417         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1418         aarch64_field_kinds.
1419         (OPD_F_OD_MASK): Widen by one bit.
1420         (OPD_F_NO_ZR): Bump accordingly.
1421         (get_operand_field_width): New function.
1422         * aarch64-opc.c (fields): Add new SVE fields.
1423         (operand_general_constraint_met_p): Handle new SVE operands.
1424         (aarch64_print_operand): Likewise.
1425         * aarch64-opc-2.c: Regenerate.
1426
1427 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1428
1429         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1430         (aarch64_feature_compnum): ...this.
1431         (SIMD_V8_3): Replace with...
1432         (COMPNUM): ...this.
1433         (CNUM_INSN): New macro.
1434         (aarch64_opcode_table): Use it for the complex number instructions.
1435
1436 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1437
1438         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1439
1440 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1441
1442         Add support for associating SPARC ASIs with an architecture level.
1443         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1444         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1445         decoding of SPARC ASIs.
1446
1447 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1448
1449         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1450         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1451
1452 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1453
1454         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1455         1 (instead of to itself). Correct typo.
1456
1457 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1458
1459         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1460         pseudoinstructions.
1461
1462 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1463
1464         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1465         (aarch64_sys_reg_supported_p): Handle them.
1466
1467 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1468
1469         * arc-opc.c (UIMM6_20R): Define.
1470         (SIMM12_20): Use above.
1471         (SIMM12_20R): Define.
1472         (SIMM3_5_S): Use above.
1473         (UIMM7_A32_11R_S): Define.
1474         (UIMM7_9_S): Use above.
1475         (UIMM3_13R_S): Define.
1476         (SIMM11_A32_7_S): Use above.
1477         (SIMM9_8R): Define.
1478         (UIMM10_A32_8_S): Use above.
1479         (UIMM8_8R_S): Define.
1480         (W6): Use above.
1481         (arc_relax_opcodes): Use all above defines.
1482
1483 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1484
1485         * arc-regs.h: Distinguish some of the registers different on
1486         ARC700 and HS38 cpus.
1487
1488 2017-02-14  Alan Modra  <amodra@gmail.com>
1489
1490         PR 21118
1491         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1492         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1493
1494 2017-02-11  Stafford Horne  <shorne@gmail.com>
1495             Alan Modra  <amodra@gmail.com>
1496
1497         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1498         Use insn_bytes_value and insn_int_value directly instead.  Don't
1499         free allocated memory until function exit.
1500
1501 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1502
1503         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1504
1505 2017-02-03  Nick Clifton  <nickc@redhat.com>
1506
1507         PR 21096
1508         * aarch64-opc.c (print_register_list): Ensure that the register
1509         list index will fir into the tb buffer.
1510         (print_register_offset_address): Likewise.
1511         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1512
1513 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1514
1515         PR 21056
1516         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1517         instructions when the previous fetch packet ends with a 32-bit
1518         instruction.
1519
1520 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1521
1522         * pru-opc.c: Remove vague reference to a future GDB port.
1523
1524 2017-01-20  Nick Clifton  <nickc@redhat.com>
1525
1526         * po/ga.po: Updated Irish translation.
1527
1528 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1529
1530         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1531
1532 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1533
1534         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1535         if FETCH_DATA returns 0.
1536         (m68k_scan_mask): Likewise.
1537         (print_insn_m68k): Update code to handle -1 return value.
1538
1539 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1540
1541         * m68k-dis.c (enum print_insn_arg_error): New.
1542         (NEXTBYTE): Replace -3 with
1543         PRINT_INSN_ARG_MEMORY_ERROR.
1544         (NEXTULONG): Likewise.
1545         (NEXTSINGLE): Likewise.
1546         (NEXTDOUBLE): Likewise.
1547         (NEXTDOUBLE): Likewise.
1548         (NEXTPACKED): Likewise.
1549         (FETCH_ARG): Likewise.
1550         (FETCH_DATA): Update comments.
1551         (print_insn_arg): Update comments. Replace magic numbers with
1552         enum.
1553         (match_insn_m68k): Likewise.
1554
1555 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1556
1557         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1558         * i386-dis-evex.h (evex_table): Updated.
1559         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1560         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1561         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1562         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1563         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1564         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1565         * i386-init.h: Regenerate.
1566         * i386-tbl.h: Ditto.
1567
1568 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1569
1570         * msp430-dis.c (msp430_singleoperand): Return -1 if
1571         msp430dis_opcode_signed returns false.
1572         (msp430_doubleoperand): Likewise.
1573         (msp430_branchinstr): Return -1 if
1574         msp430dis_opcode_unsigned returns false.
1575         (msp430x_calla_instr): Likewise.
1576         (print_insn_msp430): Likewise.
1577
1578 2017-01-05  Nick Clifton  <nickc@redhat.com>
1579
1580         PR 20946
1581         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1582         could not be matched.
1583         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1584         NULL.
1585
1586 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1587
1588         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1589         (aarch64_opcode_table): Use RCPC_INSN.
1590
1591 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1592
1593         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1594         extension.
1595         * riscv-opcodes/all-opcodes: Likewise.
1596
1597 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1598
1599         * riscv-dis.c (print_insn_args): Add fall through comment.
1600
1601 2017-01-03  Nick Clifton  <nickc@redhat.com>
1602
1603         * po/sr.po: New Serbian translation.
1604         * configure.ac (ALL_LINGUAS): Add sr.
1605         * configure: Regenerate.
1606
1607 2017-01-02  Alan Modra  <amodra@gmail.com>
1608
1609         * epiphany-desc.h: Regenerate.
1610         * epiphany-opc.h: Regenerate.
1611         * fr30-desc.h: Regenerate.
1612         * fr30-opc.h: Regenerate.
1613         * frv-desc.h: Regenerate.
1614         * frv-opc.h: Regenerate.
1615         * ip2k-desc.h: Regenerate.
1616         * ip2k-opc.h: Regenerate.
1617         * iq2000-desc.h: Regenerate.
1618         * iq2000-opc.h: Regenerate.
1619         * lm32-desc.h: Regenerate.
1620         * lm32-opc.h: Regenerate.
1621         * m32c-desc.h: Regenerate.
1622         * m32c-opc.h: Regenerate.
1623         * m32r-desc.h: Regenerate.
1624         * m32r-opc.h: Regenerate.
1625         * mep-desc.h: Regenerate.
1626         * mep-opc.h: Regenerate.
1627         * mt-desc.h: Regenerate.
1628         * mt-opc.h: Regenerate.
1629         * or1k-desc.h: Regenerate.
1630         * or1k-opc.h: Regenerate.
1631         * xc16x-desc.h: Regenerate.
1632         * xc16x-opc.h: Regenerate.
1633         * xstormy16-desc.h: Regenerate.
1634         * xstormy16-opc.h: Regenerate.
1635
1636 2017-01-02  Alan Modra  <amodra@gmail.com>
1637
1638         Update year range in copyright notice of all files.
1639
1640 For older changes see ChangeLog-2016
1641 \f
1642 Copyright (C) 2017 Free Software Foundation, Inc.
1643
1644 Copying and distribution of this file, with or without modification,
1645 are permitted in any medium without royalty provided the copyright
1646 notice and this notice are preserved.
1647
1648 Local Variables:
1649 mode: change-log
1650 left-margin: 8
1651 fill-column: 74
1652 version-control: never
1653 End: