opcodes/ChangeLog

   1 2019-11-05  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
   4         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
   5         (prefix_table): Add respective entries.
   6         (rm_table): Link to those entries.
   7
   8 2019-11-05  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
  11         (REG_0F1C_P_0_MOD_0): ... this.
  12         (REG_0F1E_MOD_3): Rename to ...
  13         (REG_0F1E_P_1_MOD_3): ... this.
  14         (RM_0F01_REG_5): Rename to ...
  15         (RM_0F01_REG_5_MOD_3): ... this.
  16         (RM_0F01_REG_7): Rename to ...
  17         (RM_0F01_REG_7_MOD_3): ... this.
  18         (RM_0F1E_MOD_3_REG_7): Rename to ...
  19         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
  20         (RM_0FAE_REG_6): Rename to ...
  21         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
  22         (RM_0FAE_REG_7): Rename to ...
  23         (RM_0FAE_REG_7_MOD_3): ... this.
  24         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
  25         (PREFIX_0F01_REG_5_MOD_0): ... this.
  26         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
  27         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
  28         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
  29         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
  30         (PREFIX_0FAE_REG_0): Rename to ...
  31         (PREFIX_0FAE_REG_0_MOD_3): ... this.
  32         (PREFIX_0FAE_REG_1): Rename to ...
  33         (PREFIX_0FAE_REG_1_MOD_3): ... this.
  34         (PREFIX_0FAE_REG_2): Rename to ...
  35         (PREFIX_0FAE_REG_2_MOD_3): ... this.
  36         (PREFIX_0FAE_REG_3): Rename to ...
  37         (PREFIX_0FAE_REG_3_MOD_3): ... this.
  38         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
  39         (PREFIX_0FAE_REG_4_MOD_0): ... this.
  40         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
  41         (PREFIX_0FAE_REG_4_MOD_3): ... this.
  42         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
  43         (PREFIX_0FAE_REG_5_MOD_0): ... this.
  44         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
  45         (PREFIX_0FAE_REG_5_MOD_3): ... this.
  46         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
  47         (PREFIX_0FAE_REG_6_MOD_0): ... this.
  48         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
  49         (PREFIX_0FAE_REG_6_MOD_3): ... this.
  50         (PREFIX_0FAE_REG_7): Rename to ...
  51         (PREFIX_0FAE_REG_7_MOD_0): ... this.
  52         (PREFIX_MOD_0_0FC3): Rename to ...
  53         (PREFIX_0FC3_MOD_0): ... this.
  54         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
  55         (PREFIX_0FC7_REG_6_MOD_0): ... this.
  56         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
  57         (PREFIX_0FC7_REG_6_MOD_3): ... this.
  58         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
  59         (PREFIX_0FC7_REG_7_MOD_3): ... this.
  60         (reg_table, prefix_table, mod_table, rm_table): Adjust
  61         accordingly.
  62
  63 2019-11-04  Nick Clifton  <nickc@redhat.com>
  64
  65         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
  66         of a v850 system register.  Move the v850_sreg_names array into
  67         this function.
  68         (get_v850_reg_name): Likewise for ordinary register names.
  69         (get_v850_vreg_name): Likewise for vector register names.
  70         (get_v850_cc_name): Likewise for condition codes.
  71         * get_v850_float_cc_name): Likewise for floating point condition
  72         codes.
  73         (get_v850_cacheop_name): Likewise for cache-ops.
  74         (get_v850_prefop_name): Likewise for pref-ops.
  75         (disassemble): Use the new accessor functions.
  76
  77 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
  78
  79         * aarch64-opc.c (print_immediate_offset_address): Don't print the
  80         immediate for the writeback form of ldraa/ldrab if it is 0.
  81         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
  82         * aarch64-opc-2.c: Regenerated.
  83
  84 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-gen.c (operand_type_shorthands): Delete.
  87         (operand_type_init): Expand previous shorthands.
  88         (set_bitfield_from_shorthand): Rename back to ...
  89         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
  90         of operand_type_init[].
  91         (set_bitfield): Adjust call to the above function.
  92         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
  93         RegXMM, RegYMM, RegZMM): Define.
  94         * i386-reg.tbl: Expand prior shorthands.
  95
  96 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-gen.c (output_i386_opcode): Change order of fields
  99         emitted to output.
 100         * i386-opc.h (struct insn_template): Move operands field.
 101         Convert extension_opcode field to unsigned short.
 102         * i386-tbl.h: Re-generate.
 103
 104 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 107         of W.
 108         * i386-opc.h (W): Extend comment.
 109         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 110         general purpose variants not allowing for byte operands.
 111         * i386-tbl.h: Re-generate.
 112
 113 2019-10-29  Nick Clifton  <nickc@redhat.com>
 114
 115         * tic30-dis.c (print_branch): Correct size of operand array.
 116
 117 2019-10-29  Nick Clifton  <nickc@redhat.com>
 118
 119         * d30v-dis.c (print_insn): Check that operand index is valid
 120         before attempting to access the operands array.
 121
 122 2019-10-29  Nick Clifton  <nickc@redhat.com>
 123
 124         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 125         locating the bit to be tested.
 126
 127 2019-10-29  Nick Clifton  <nickc@redhat.com>
 128
 129         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 130         values.
 131         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 132         (print_insn_s12z):  Check for illegal size values.
 133
 134 2019-10-28  Nick Clifton  <nickc@redhat.com>
 135
 136         * csky-dis.c (csky_chars_to_number): Check for a negative
 137         count. Use an unsigned integer to construct the return value.
 138
 139 2019-10-28  Nick Clifton  <nickc@redhat.com>
 140
 141         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 142         operand buffer.  Set value to 15 not 13.
 143         (get_register_operand): Use OPERAND_BUFFER_LEN.
 144         (get_indirect_operand): Likewise.
 145         (print_two_operand): Likewise.
 146         (print_three_operand): Likewise.
 147         (print_oar_insn): Likewise.
 148
 149 2019-10-28  Nick Clifton  <nickc@redhat.com>
 150
 151         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 152         (bit_extract_simple): Likewise.
 153         (bit_copy): Likewise.
 154         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 155         index_offset array are not accessed.
 156
 157 2019-10-28  Nick Clifton  <nickc@redhat.com>
 158
 159         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 160         operand.
 161
 162 2019-10-25  Nick Clifton  <nickc@redhat.com>
 163
 164         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 165         access to opcodes.op array element.
 166
 167 2019-10-23  Nick Clifton  <nickc@redhat.com>
 168
 169         * rx-dis.c (get_register_name): Fix spelling typo in error
 170         message.
 171         (get_condition_name, get_flag_name, get_double_register_name)
 172         (get_double_register_high_name, get_double_register_low_name)
 173         (get_double_control_register_name, get_double_condition_name)
 174         (get_opsize_name, get_size_name): Likewise.
 175
 176 2019-10-22  Nick Clifton  <nickc@redhat.com>
 177
 178         * rx-dis.c (get_size_name): New function.  Provides safe
 179         access to name array.
 180         (get_opsize_name): Likewise.
 181         (print_insn_rx): Use the accessor functions.
 182
 183 2019-10-16  Nick Clifton  <nickc@redhat.com>
 184
 185         * rx-dis.c (get_register_name): New function.  Provides safe
 186         access to name array.
 187         (get_condition_name, get_flag_name, get_double_register_name)
 188         (get_double_register_high_name, get_double_register_low_name)
 189         (get_double_control_register_name, get_double_condition_name):
 190         Likewise.
 191         (print_insn_rx): Use the accessor functions.
 192
 193 2019-10-09  Nick Clifton  <nickc@redhat.com>
 194
 195         PR 25041
 196         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 197         instructions.
 198
 199 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 200
 201         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 202         (cmpsd): Likewise. Move EsSeg to other operand.
 203         * opcodes/i386-tbl.h: Re-generate.
 204
 205 2019-09-23  Alan Modra  <amodra@gmail.com>
 206
 207         * m68k-dis.c: Include cpu-m68k.h
 208
 209 2019-09-23  Alan Modra  <amodra@gmail.com>
 210
 211         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 212         "elf/mips.h" earlier.
 213
 214 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 215
 216         PR gas/25012
 217         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 218         with SReg operand.
 219         * i386-tbl.h: Re-generate.
 220
 221 2019-09-18  Alan Modra  <amodra@gmail.com>
 222
 223         * arc-ext.c: Update throughout for bfd section macro changes.
 224
 225 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 226
 227         * Makefile.in: Re-generate.
 228         * configure: Re-generate.
 229
 230 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 231
 232         * riscv-opc.c (riscv_opcodes): Change subset field
 233         to insn_class field for all instructions.
 234         (riscv_insn_types): Likewise.
 235
 236 2019-09-16  Phil Blundell  <pb@pbcl.net>
 237
 238         * configure: Regenerated.
 239
 240 2019-09-10  Miod Vallat  <miod@online.fr>
 241
 242         PR 24982
 243         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 244
 245 2019-09-09  Phil Blundell  <pb@pbcl.net>
 246
 247         binutils 2.33 branch created.
 248
 249 2019-09-03  Nick Clifton  <nickc@redhat.com>
 250
 251         PR 24961
 252         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 253         greater than zero before indexing via (bufcnt -1).
 254
 255 2019-09-03  Nick Clifton  <nickc@redhat.com>
 256
 257         PR 24958
 258         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 259         (MAX_SPEC_REG_NAME_LEN): Define.
 260         (struct mmix_dis_info): Use defined constants for array lengths.
 261         (get_reg_name): New function.
 262         (get_sprec_reg_name): New function.
 263         (print_insn_mmix): Use new functions.
 264
 265 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 266
 267         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 268         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 269         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 270
 271 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 272
 273         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 274         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 275         (aarch64_sys_reg_supported_p): Update checks for the above.
 276
 277 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 278
 279         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 280         cases MVE_SQRSHRL and MVE_UQRSHLL.
 281         (print_insn_mve): Add case for specifier 'k' to check
 282         specific bit of the instruction.
 283
 284 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 285
 286         PR 24854
 287         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 288         encountering an unknown machine type.
 289         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 290         cases return -1 rather than calling abort.
 291
 292 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 295         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 296         IgnoreSize.
 297         * i386-tbl.h: Re-generate.
 298
 299 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 300
 301         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 302         instructions.
 303
 304 2019-07-30  Mel Chen <mel.chen@sifive.com>
 305
 306         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 307         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 308
 309         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 310         fscsr.
 311
 312 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 313
 314         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 315         and MPY class instructions.
 316         (parse_option): Add nps400 option.
 317         (print_arc_disassembler_options): Add nps400 info.
 318
 319 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 320
 321         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 322         (bspop): Likewise.
 323         (modapp): Likewise.
 324         * arc-opc.c (RAD_CHK): Add.
 325         * arc-tbl.h: Regenerate.
 326
 327 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 328
 329         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 330         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 331
 332 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 333
 334         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 335         instructions as UNPREDICTABLE.
 336
 337 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 338
 339         * bpf-desc.c: Regenerated.
 340
 341 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-gen.c (static_assert): Define.
 344         (main): Use it.
 345         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 346         (Opcode_Modifier_Num): ... this.
 347         (Mem): Delete.
 348
 349 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-gen.c (operand_types): Move RegMem ...
 352         (opcode_modifiers): ... here.
 353         * i386-opc.h (RegMem): Move to opcode modifer enum.
 354         (union i386_operand_type): Move regmem field ...
 355         (struct i386_opcode_modifier): ... here.
 356         * i386-opc.tbl (RegMem): Define.
 357         (mov, movq): Move RegMem on segment, control, debug, and test
 358         register flavors.
 359         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 360         to non-SSE2AVX flavor.
 361         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 362         Move RegMem on register only flavors. Drop IgnoreSize from
 363         legacy encoding flavors.
 364         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 365         flavors.
 366         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 367         register only flavors.
 368         (vmovd): Move RegMem and drop IgnoreSize on register only
 369         flavor. Change opcode and operand order to store form.
 370         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 371
 372 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 373
 374         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 375         entries.
 376         * i386-opc.h (SReg2, SReg3): Replace by ...
 377         (SReg): ... this.
 378         (union i386_operand_type): Replace sreg fields.
 379         * i386-opc.tbl (mov, ): Use SReg.
 380         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 381         register flavors.
 382         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 383         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 384
 385 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 386
 387         * bpf-desc.c: Regenerate.
 388         * bpf-opc.c: Likewise.
 389         * bpf-opc.h: Likewise.
 390
 391 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 392
 393         * bpf-desc.c: Regenerate.
 394         * bpf-opc.c: Likewise.
 395
 396 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 397
 398         * arm-dis.c (print_insn_coprocessor): Rename index to
 399         index_operand.
 400
 401 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 402
 403         * riscv-opc.c (riscv_insn_types): Add r4 type.
 404
 405         * riscv-opc.c (riscv_insn_types): Add b and j type.
 406
 407         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 408         format for sb type and correct s type.
 409
 410 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 411
 412         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 413         SVE FMOV alias of FCPY.
 414
 415 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 416
 417         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 418         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 419
 420 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 421
 422         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 423         registers in an instruction prefixed by MOVPRFX.
 424
 425 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 426
 427         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 428         sve_size_13 icode to account for variant behaviour of
 429         pmull{t,b}.
 430         * aarch64-dis-2.c: Regenerate.
 431         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 432         sve_size_13 icode to account for variant behaviour of
 433         pmull{t,b}.
 434         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 435         (OP_SVE_VVV_Q_D): Add new qualifier.
 436         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 437         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 438         AES and those not.
 439
 440 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 441
 442         * opcodes/i386-gen.c (operand_type_init): Remove
 443         OPERAND_TYPE_VEC_IMM4 entry.
 444         (operand_types): Remove Vec_Imm4.
 445         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 446         (union i386_operand_type): Remove vec_imm4.
 447         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 448         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 449
 450 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 451
 452         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 453         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 454         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 455         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 456         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 457         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 458         * i386-tbl.h: Re-generate.
 459
 460 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 463         register operands.
 464         * i386-tbl.h: Re-generate.
 465
 466 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-opc.tbl (C): New.
 469         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 470         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 471         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 472         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 473         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 474         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 475         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 476         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 477         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 478         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 479         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 480         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 481         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 482         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 483         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 484         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 485         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 486         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 487         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 488         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 489         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 490         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 491         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 492         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 493         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 494         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 495         flavors.
 496         * i386-tbl.h: Re-generate.
 497
 498 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 501         register operands.
 502         * i386-tbl.h: Re-generate.
 503
 504 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 507         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 508         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 509         * i386-tbl.h: Re-generate.
 510
 511 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 514         Disp8MemShift from register only templates.
 515         * i386-tbl.h: Re-generate.
 516
 517 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 520         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 521         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 522         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 523         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 524         EVEX_W_0F11_P_3_M_1): Delete.
 525         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 526         EVEX_W_0F11_P_3): New.
 527         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 528         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 529         MOD_EVEX_0F11_PREFIX_3 table entries.
 530         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 531         PREFIX_EVEX_0F11 table entries.
 532         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 533         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 534         EVEX_W_0F11_P_3_M_{0,1} table entries.
 535
 536 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 539         Delete.
 540
 541 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 542
 543         PR binutils/24719
 544         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 545         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 546         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 547         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 548         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 549         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 550         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 551         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 552         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 553         PREFIX_EVEX_0F38C6_REG_6 entries.
 554         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 555         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 556         EVEX_W_0F38C7_R_6_P_2 entries.
 557         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 558         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 559         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 560         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 561         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 562         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 563         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 564
 565 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 568         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 569         VEX_LEN_0F2D_P_3): Delete.
 570         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 571         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 572         (prefix_table): ... here.
 573
 574 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-dis.c (Iq): Delete.
 577         (Id): New.
 578         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 579         TBM insns.
 580         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 581         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 582         (OP_E_memory): Also honor needindex when deciding whether an
 583         address size prefix needs printing.
 584         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 585
 586 2019-06-26  Jim Wilson  <jimw@sifive.com>
 587
 588         PR binutils/24739
 589         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 590         Set info->display_endian to info->endian_code.
 591
 592 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 595         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 596         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 597         OPERAND_TYPE_ACC64 entries.
 598         * i386-init.h: Re-generate.
 599
 600 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 603         Delete.
 604         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 605         of dqa_mode.
 606         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 607         entries here.
 608         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 609         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 610
 611 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 614         variables.
 615
 616 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 619         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 620         movnti.
 621         * i386-opc.tbl (movnti): Add IgnoreSize.
 622         * i386-tbl.h: Re-generate.
 623
 624 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 627         * i386-tbl.h: Re-generate.
 628
 629 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 630
 631         * i386-dis-evex.h: Break into ...
 632         * i386-dis-evex-len.h: New file.
 633         * i386-dis-evex-mod.h: Likewise.
 634         * i386-dis-evex-prefix.h: Likewise.
 635         * i386-dis-evex-reg.h: Likewise.
 636         * i386-dis-evex-w.h: Likewise.
 637         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 638         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 639         i386-dis-evex-mod.h.
 640
 641 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 642
 643         PR binutils/24700
 644         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 645         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 646         EVEX_W_0F385B_P_2.
 647         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 648         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 649         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 650         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 651         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 652         EVEX_LEN_0F385B_P_2_W_1.
 653         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 654         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 655         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 656         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 657         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 658         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 659         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 660         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 661         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 662         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 663
 664 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         PR binutils/24691
 667         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 668         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 669         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 670         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 671         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 672         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 673         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 674         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 675         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 676         EVEX_LEN_0F3A43_P_2_W_1.
 677         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 678         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 679         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 680         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 681         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 682         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 683         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 684         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 685         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 686         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 687         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 688         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 689
 690 2019-06-14  Nick Clifton  <nickc@redhat.com>
 691
 692         * po/fr.po; Updated French translation.
 693
 694 2019-06-13  Stafford Horne  <shorne@gmail.com>
 695
 696         * or1k-asm.c: Regenerated.
 697         * or1k-desc.c: Regenerated.
 698         * or1k-desc.h: Regenerated.
 699         * or1k-dis.c: Regenerated.
 700         * or1k-ibld.c: Regenerated.
 701         * or1k-opc.c: Regenerated.
 702         * or1k-opc.h: Regenerated.
 703         * or1k-opinst.c: Regenerated.
 704
 705 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 706
 707         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 708
 709 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         PR binutils/24633
 712         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 713         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 714         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 715         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 716         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 717         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 718         EVEX_LEN_0F3A1B_P_2_W_1.
 719         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 720         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 721         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 722         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 723         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 724         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 725         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 726         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 727
 728 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         PR binutils/24626
 731         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 732         EVEX.vvvv when disassembling VEX and EVEX instructions.
 733         (OP_VEX): Set vex.register_specifier to 0 after readding
 734         vex.register_specifier.
 735         (OP_Vex_2src_1): Likewise.
 736         (OP_Vex_2src_2): Likewise.
 737         (OP_LWP_E): Likewise.
 738         (OP_EX_Vex): Don't check vex.register_specifier.
 739         (OP_XMM_Vex): Likewise.
 740
 741 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 742             Lili Cui  <lili.cui@intel.com>
 743
 744         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 745         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 746         instructions.
 747         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 748         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 749         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 750         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 751         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 752         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 753         * i386-init.h: Regenerated.
 754         * i386-tbl.h: Likewise.
 755
 756 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 757             Lili Cui  <lili.cui@intel.com>
 758
 759         * doc/c-i386.texi: Document enqcmd.
 760         * testsuite/gas/i386/enqcmd-intel.d: New file.
 761         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 762         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 763         * testsuite/gas/i386/enqcmd.d: Likewise.
 764         * testsuite/gas/i386/enqcmd.s: Likewise.
 765         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 766         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 767         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 768         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 769         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 770         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 771         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 772         and x86-64-enqcmd.
 773
 774 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 775
 776         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 777
 778 2019-06-03  Alan Modra  <amodra@gmail.com>
 779
 780         * ppc-dis.c (prefix_opcd_indices): Correct size.
 781
 782 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         PR gas/24625
 785         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 786         Disp8ShiftVL.
 787         * i386-tbl.h: Regenerated.
 788
 789 2019-05-24  Alan Modra  <amodra@gmail.com>
 790
 791         * po/POTFILES.in: Regenerate.
 792
 793 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 794             Alan Modra  <amodra@gmail.com>
 795
 796         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 797         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 798         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 799         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 800         XTOP>): Define and add entries.
 801         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 802         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 803         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 804         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 805
 806 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 807             Alan Modra  <amodra@gmail.com>
 808
 809         * ppc-dis.c (ppc_opts): Add "future" entry.
 810         (PREFIX_OPCD_SEGS): Define.
 811         (prefix_opcd_indices): New array.
 812         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 813         (lookup_prefix): New function.
 814         (print_insn_powerpc): Handle 64-bit prefix instructions.
 815         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 816         (PMRR, POWERXX): Define.
 817         (prefix_opcodes): New instruction table.
 818         (prefix_num_opcodes): New constant.
 819
 820 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 821
 822         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 823         * configure: Regenerated.
 824         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 825         and cpu/bpf.opc.
 826         (HFILES): Add bpf-desc.h and bpf-opc.h.
 827         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 828         bpf-ibld.c and bpf-opc.c.
 829         (BPF_DEPS): Define.
 830         * Makefile.in: Regenerated.
 831         * disassemble.c (ARCH_bpf): Define.
 832         (disassembler): Add case for bfd_arch_bpf.
 833         (disassemble_init_for_target): Likewise.
 834         (enum epbf_isa_attr): Define.
 835         * disassemble.h: extern print_insn_bpf.
 836         * bpf-asm.c: Generated.
 837         * bpf-opc.h: Likewise.
 838         * bpf-opc.c: Likewise.
 839         * bpf-ibld.c: Likewise.
 840         * bpf-dis.c: Likewise.
 841         * bpf-desc.h: Likewise.
 842         * bpf-desc.c: Likewise.
 843
 844 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 845
 846         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 847         and VMSR with the new operands.
 848
 849 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 850
 851         * arm-dis.c (enum mve_instructions): New enum
 852         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 853         and cneg.
 854         (mve_opcodes): New instructions as above.
 855         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 856         csneg and csel.
 857         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 858
 859 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 860
 861         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 862         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 863         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 864         uqshl, urshrl and urshr.
 865         (is_mve_okay_in_it): Add new instructions to TRUE list.
 866         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 867         (print_insn_mve): Updated to accept new %j,
 868         %<bitfield>m and %<bitfield>n patterns.
 869
 870 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 871
 872         * mips-opc.c (mips_builtin_opcodes): Change source register
 873         constraint for DAUI.
 874
 875 2019-05-20  Nick Clifton  <nickc@redhat.com>
 876
 877         * po/fr.po: Updated French translation.
 878
 879 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 880             Michael Collison <michael.collison@arm.com>
 881
 882         * arm-dis.c (thumb32_opcodes): Add new instructions.
 883         (enum mve_instructions): Likewise.
 884         (enum mve_undefined): Add new reasons.
 885         (is_mve_encoding_conflict): Handle new instructions.
 886         (is_mve_undefined): Likewise.
 887         (is_mve_unpredictable): Likewise.
 888         (print_mve_undefined): Likewise.
 889         (print_mve_size): Likewise.
 890
 891 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 892             Michael Collison <michael.collison@arm.com>
 893
 894         * arm-dis.c (thumb32_opcodes): Add new instructions.
 895         (enum mve_instructions): Likewise.
 896         (is_mve_encoding_conflict): Handle new instructions.
 897         (is_mve_undefined): Likewise.
 898         (is_mve_unpredictable): Likewise.
 899         (print_mve_size): Likewise.
 900
 901 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 902             Michael Collison <michael.collison@arm.com>
 903
 904         * arm-dis.c (thumb32_opcodes): Add new instructions.
 905         (enum mve_instructions): Likewise.
 906         (is_mve_encoding_conflict): Likewise.
 907         (is_mve_unpredictable): Likewise.
 908         (print_mve_size): Likewise.
 909
 910 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 911             Michael Collison <michael.collison@arm.com>
 912
 913         * arm-dis.c (thumb32_opcodes): Add new instructions.
 914         (enum mve_instructions): Likewise.
 915         (is_mve_encoding_conflict): Handle new instructions.
 916         (is_mve_undefined): Likewise.
 917         (is_mve_unpredictable): Likewise.
 918         (print_mve_size): Likewise.
 919
 920 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 921             Michael Collison <michael.collison@arm.com>
 922
 923         * arm-dis.c (thumb32_opcodes): Add new instructions.
 924         (enum mve_instructions): Likewise.
 925         (is_mve_encoding_conflict): Handle new instructions.
 926         (is_mve_undefined): Likewise.
 927         (is_mve_unpredictable): Likewise.
 928         (print_mve_size): Likewise.
 929         (print_insn_mve): Likewise.
 930
 931 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 932             Michael Collison <michael.collison@arm.com>
 933
 934         * arm-dis.c (thumb32_opcodes): Add new instructions.
 935         (print_insn_thumb32): Handle new instructions.
 936
 937 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 938             Michael Collison <michael.collison@arm.com>
 939
 940         * arm-dis.c (enum mve_instructions): Add new instructions.
 941         (enum mve_undefined): Add new reasons.
 942         (is_mve_encoding_conflict): Handle new instructions.
 943         (is_mve_undefined): Likewise.
 944         (is_mve_unpredictable): Likewise.
 945         (print_mve_undefined): Likewise.
 946         (print_mve_size): Likewise.
 947         (print_mve_shift_n): Likewise.
 948         (print_insn_mve): Likewise.
 949
 950 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 951             Michael Collison <michael.collison@arm.com>
 952
 953         * arm-dis.c (enum mve_instructions): Add new instructions.
 954         (is_mve_encoding_conflict): Handle new instructions.
 955         (is_mve_unpredictable): Likewise.
 956         (print_mve_rotate): Likewise.
 957         (print_mve_size): Likewise.
 958         (print_insn_mve): Likewise.
 959
 960 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 961             Michael Collison <michael.collison@arm.com>
 962
 963         * arm-dis.c (enum mve_instructions): Add new instructions.
 964         (is_mve_encoding_conflict): Handle new instructions.
 965         (is_mve_unpredictable): Likewise.
 966         (print_mve_size): Likewise.
 967         (print_insn_mve): Likewise.
 968
 969 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 970             Michael Collison <michael.collison@arm.com>
 971
 972         * arm-dis.c (enum mve_instructions): Add new instructions.
 973         (enum mve_undefined): Add new reasons.
 974         (is_mve_encoding_conflict): Handle new instructions.
 975         (is_mve_undefined): Likewise.
 976         (is_mve_unpredictable): Likewise.
 977         (print_mve_undefined): Likewise.
 978         (print_mve_size): Likewise.
 979         (print_insn_mve): Likewise.
 980
 981 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 982             Michael Collison <michael.collison@arm.com>
 983
 984         * arm-dis.c (enum mve_instructions): Add new instructions.
 985         (is_mve_encoding_conflict): Handle new instructions.
 986         (is_mve_undefined): Likewise.
 987         (is_mve_unpredictable): Likewise.
 988         (print_mve_size): Likewise.
 989         (print_insn_mve): Likewise.
 990
 991 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 992             Michael Collison <michael.collison@arm.com>
 993
 994         * arm-dis.c (enum mve_instructions): Add new instructions.
 995         (enum mve_unpredictable): Add new reasons.
 996         (enum mve_undefined): Likewise.
 997         (is_mve_okay_in_it): Handle new isntructions.
 998         (is_mve_encoding_conflict): Likewise.
 999         (is_mve_undefined): Likewise.
1000         (is_mve_unpredictable): Likewise.
1001         (print_mve_vmov_index): Likewise.
1002         (print_simd_imm8): Likewise.
1003         (print_mve_undefined): Likewise.
1004         (print_mve_unpredictable): Likewise.
1005         (print_mve_size): Likewise.
1006         (print_insn_mve): Likewise.
1007
1008 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1009             Michael Collison <michael.collison@arm.com>
1010
1011         * arm-dis.c (enum mve_instructions): Add new instructions.
1012         (enum mve_unpredictable): Add new reasons.
1013         (enum mve_undefined): Likewise.
1014         (is_mve_encoding_conflict): Handle new instructions.
1015         (is_mve_undefined): Likewise.
1016         (is_mve_unpredictable): Likewise.
1017         (print_mve_undefined): Likewise.
1018         (print_mve_unpredictable): Likewise.
1019         (print_mve_rounding_mode): Likewise.
1020         (print_mve_vcvt_size): Likewise.
1021         (print_mve_size): Likewise.
1022         (print_insn_mve): Likewise.
1023
1024 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1025             Michael Collison <michael.collison@arm.com>
1026
1027         * arm-dis.c (enum mve_instructions): Add new instructions.
1028         (enum mve_unpredictable): Add new reasons.
1029         (enum mve_undefined): Likewise.
1030         (is_mve_undefined): Handle new instructions.
1031         (is_mve_unpredictable): Likewise.
1032         (print_mve_undefined): Likewise.
1033         (print_mve_unpredictable): Likewise.
1034         (print_mve_size): Likewise.
1035         (print_insn_mve): Likewise.
1036
1037 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1038             Michael Collison <michael.collison@arm.com>
1039
1040         * arm-dis.c (enum mve_instructions): Add new instructions.
1041         (enum mve_undefined): Add new reasons.
1042         (insns): Add new instructions.
1043         (is_mve_encoding_conflict):
1044         (print_mve_vld_str_addr): New print function.
1045         (is_mve_undefined): Handle new instructions.
1046         (is_mve_unpredictable): Likewise.
1047         (print_mve_undefined): Likewise.
1048         (print_mve_size): Likewise.
1049         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1050         (print_insn_mve):  Handle new operands.
1051
1052 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1053             Michael Collison <michael.collison@arm.com>
1054
1055         * arm-dis.c (enum mve_instructions): Add new instructions.
1056         (enum mve_unpredictable): Add new reasons.
1057         (is_mve_encoding_conflict): Handle new instructions.
1058         (is_mve_unpredictable): Likewise.
1059         (mve_opcodes): Add new instructions.
1060         (print_mve_unpredictable): Handle new reasons.
1061         (print_mve_register_blocks): New print function.
1062         (print_mve_size): Handle new instructions.
1063         (print_insn_mve): Likewise.
1064
1065 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1066             Michael Collison <michael.collison@arm.com>
1067
1068         * arm-dis.c (enum mve_instructions): Add new instructions.
1069         (enum mve_unpredictable): Add new reasons.
1070         (enum mve_undefined): Likewise.
1071         (is_mve_encoding_conflict): Handle new instructions.
1072         (is_mve_undefined): Likewise.
1073         (is_mve_unpredictable): Likewise.
1074         (coprocessor_opcodes): Move NEON VDUP from here...
1075         (neon_opcodes): ... to here.
1076         (mve_opcodes): Add new instructions.
1077         (print_mve_undefined):  Handle new reasons.
1078         (print_mve_unpredictable): Likewise.
1079         (print_mve_size): Handle new instructions.
1080         (print_insn_neon): Handle vdup.
1081         (print_insn_mve): Handle new operands.
1082
1083 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1084             Michael Collison <michael.collison@arm.com>
1085
1086         * arm-dis.c (enum mve_instructions): Add new instructions.
1087         (enum mve_unpredictable): Add new values.
1088         (mve_opcodes): Add new instructions.
1089         (vec_condnames): New array with vector conditions.
1090         (mve_predicatenames): New array with predicate suffixes.
1091         (mve_vec_sizename): New array with vector sizes.
1092         (enum vpt_pred_state): New enum with vector predication states.
1093         (struct vpt_block): New struct type for vpt blocks.
1094         (vpt_block_state): Global struct to keep track of state.
1095         (mve_extract_pred_mask): New helper function.
1096         (num_instructions_vpt_block): Likewise.
1097         (mark_outside_vpt_block): Likewise.
1098         (mark_inside_vpt_block): Likewise.
1099         (invert_next_predicate_state): Likewise.
1100         (update_next_predicate_state): Likewise.
1101         (update_vpt_block_state): Likewise.
1102         (is_vpt_instruction): Likewise.
1103         (is_mve_encoding_conflict): Add entries for new instructions.
1104         (is_mve_unpredictable): Likewise.
1105         (print_mve_unpredictable): Handle new cases.
1106         (print_instruction_predicate): Likewise.
1107         (print_mve_size): New function.
1108         (print_vec_condition): New function.
1109         (print_insn_mve): Handle vpt blocks and new print operands.
1110
1111 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1112
1113         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1114         8, 14 and 15 for Armv8.1-M Mainline.
1115
1116 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1117             Michael Collison <michael.collison@arm.com>
1118
1119         * arm-dis.c (enum mve_instructions): New enum.
1120         (enum mve_unpredictable): Likewise.
1121         (enum mve_undefined): Likewise.
1122         (struct mopcode32): New struct.
1123         (is_mve_okay_in_it): New function.
1124         (is_mve_architecture): Likewise.
1125         (arm_decode_field): Likewise.
1126         (arm_decode_field_multiple): Likewise.
1127         (is_mve_encoding_conflict): Likewise.
1128         (is_mve_undefined): Likewise.
1129         (is_mve_unpredictable): Likewise.
1130         (print_mve_undefined): Likewise.
1131         (print_mve_unpredictable): Likewise.
1132         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1133         (print_insn_mve): New function.
1134         (print_insn_thumb32): Handle MVE architecture.
1135         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1136
1137 2019-05-10  Nick Clifton  <nickc@redhat.com>
1138
1139         PR 24538
1140         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1141         end of the table prematurely.
1142
1143 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1144
1145         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1146         macros for R6.
1147
1148 2019-05-11  Alan Modra  <amodra@gmail.com>
1149
1150         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1151         when -Mraw is in effect.
1152
1153 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1154
1155         * aarch64-dis-2.c: Regenerate.
1156         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1157         (OP_SVE_BBB): New variant set.
1158         (OP_SVE_DDDD): New variant set.
1159         (OP_SVE_HHH): New variant set.
1160         (OP_SVE_HHHU): New variant set.
1161         (OP_SVE_SSS): New variant set.
1162         (OP_SVE_SSSU): New variant set.
1163         (OP_SVE_SHH): New variant set.
1164         (OP_SVE_SBBU): New variant set.
1165         (OP_SVE_DSS): New variant set.
1166         (OP_SVE_DHHU): New variant set.
1167         (OP_SVE_VMV_HSD_BHS): New variant set.
1168         (OP_SVE_VVU_HSD_BHS): New variant set.
1169         (OP_SVE_VVVU_SD_BH): New variant set.
1170         (OP_SVE_VVVU_BHSD): New variant set.
1171         (OP_SVE_VVV_QHD_DBS): New variant set.
1172         (OP_SVE_VVV_HSD_BHS): New variant set.
1173         (OP_SVE_VVV_HSD_BHS2): New variant set.
1174         (OP_SVE_VVV_BHS_HSD): New variant set.
1175         (OP_SVE_VV_BHS_HSD): New variant set.
1176         (OP_SVE_VVV_SD): New variant set.
1177         (OP_SVE_VVU_BHS_HSD): New variant set.
1178         (OP_SVE_VZVV_SD): New variant set.
1179         (OP_SVE_VZVV_BH): New variant set.
1180         (OP_SVE_VZV_SD): New variant set.
1181         (aarch64_opcode_table): Add sve2 instructions.
1182
1183 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1184
1185         * aarch64-asm-2.c: Regenerated.
1186         * aarch64-dis-2.c: Regenerated.
1187         * aarch64-opc-2.c: Regenerated.
1188         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1189         for SVE_SHLIMM_UNPRED_22.
1190         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1191         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1192         operand.
1193
1194 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1195
1196         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1197         sve_size_tsz_bhs iclass encode.
1198         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1199         sve_size_tsz_bhs iclass decode.
1200
1201 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1202
1203         * aarch64-asm-2.c: Regenerated.
1204         * aarch64-dis-2.c: Regenerated.
1205         * aarch64-opc-2.c: Regenerated.
1206         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1207         for SVE_Zm4_11_INDEX.
1208         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1209         (fields): Handle SVE_i2h field.
1210         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1211         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1212
1213 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1214
1215         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1216         sve_shift_tsz_bhsd iclass encode.
1217         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1218         sve_shift_tsz_bhsd iclass decode.
1219
1220 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1221
1222         * aarch64-asm-2.c: Regenerated.
1223         * aarch64-dis-2.c: Regenerated.
1224         * aarch64-opc-2.c: Regenerated.
1225         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1226         (aarch64_encode_variant_using_iclass): Handle
1227         sve_shift_tsz_hsd iclass encode.
1228         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1229         sve_shift_tsz_hsd iclass decode.
1230         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1231         for SVE_SHRIMM_UNPRED_22.
1232         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1233         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1234         operand.
1235
1236 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1237
1238         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1239         sve_size_013 iclass encode.
1240         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1241         sve_size_013 iclass decode.
1242
1243 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1244
1245         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1246         sve_size_bh iclass encode.
1247         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1248         sve_size_bh iclass decode.
1249
1250 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1251
1252         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1253         sve_size_sd2 iclass encode.
1254         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1255         sve_size_sd2 iclass decode.
1256         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1257         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1258
1259 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1260
1261         * aarch64-asm-2.c: Regenerated.
1262         * aarch64-dis-2.c: Regenerated.
1263         * aarch64-opc-2.c: Regenerated.
1264         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1265         for SVE_ADDR_ZX.
1266         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1267         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1268
1269 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1270
1271         * aarch64-asm-2.c: Regenerated.
1272         * aarch64-dis-2.c: Regenerated.
1273         * aarch64-opc-2.c: Regenerated.
1274         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1275         for SVE_Zm3_11_INDEX.
1276         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1277         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1278         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1279         fields.
1280         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1281
1282 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1283
1284         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1285         sve_size_hsd2 iclass encode.
1286         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1287         sve_size_hsd2 iclass decode.
1288         * aarch64-opc.c (fields): Handle SVE_size field.
1289         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1290
1291 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1292
1293         * aarch64-asm-2.c: Regenerated.
1294         * aarch64-dis-2.c: Regenerated.
1295         * aarch64-opc-2.c: Regenerated.
1296         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1297         for SVE_IMM_ROT3.
1298         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1299         (fields): Handle SVE_rot3 field.
1300         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1301         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1302
1303 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1304
1305         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1306         instructions.
1307
1308 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1309
1310         * aarch64-tbl.h
1311         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1312         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1313         aarch64_feature_sve2bitperm): New feature sets.
1314         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1315         for feature set addresses.
1316         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1317         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1318
1319 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1320             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1321
1322         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1323         argument and set ASE_EVA_R6 appropriately.
1324         (set_default_mips_dis_options): Pass ISA to above.
1325         (parse_mips_dis_option): Likewise.
1326         * mips-opc.c (EVAR6): New macro.
1327         (mips_builtin_opcodes): Add llwpe, scwpe.
1328
1329 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1330
1331         * aarch64-asm-2.c: Regenerated.
1332         * aarch64-dis-2.c: Regenerated.
1333         * aarch64-opc-2.c: Regenerated.
1334         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1335         AARCH64_OPND_TME_UIMM16.
1336         (aarch64_print_operand): Likewise.
1337         * aarch64-tbl.h (QL_IMM_NIL): New.
1338         (TME): New.
1339         (_TME_INSN): New.
1340         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1341
1342 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1343
1344         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1345
1346 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1347             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1348
1349         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1350
1351 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1352
1353         * s12z-opc.h: Add extern "C" bracketing to help
1354         users who wish to use this interface in c++ code.
1355
1356 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1357
1358         * s12z-opc.c (bm_decode): Handle bit map operations with the
1359         "reserved0" mode.
1360
1361 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1362
1363         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1364         specifier.  Add entries for VLDR and VSTR of system registers.
1365         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1366         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1367         of %J and %K format specifier.
1368
1369 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1370
1371         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1372         Add new entries for VSCCLRM instruction.
1373         (print_insn_coprocessor): Handle new %C format control code.
1374
1375 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1376
1377         * arm-dis.c (enum isa): New enum.
1378         (struct sopcode32): New structure.
1379         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1380         set isa field of all current entries to ANY.
1381         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1382         Only match an entry if its isa field allows the current mode.
1383
1384 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1385
1386         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1387         CLRM.
1388         (print_insn_thumb32): Add logic to print %n CLRM register list.
1389
1390 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1391
1392         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1393         and %Q patterns.
1394
1395 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1396
1397         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1398         (print_insn_thumb32): Edit the switch case for %Z.
1399
1400 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1401
1402         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1403
1404 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1405
1406         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1407
1408 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1409
1410         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1411
1412 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1413
1414         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1415         Arm register with r13 and r15 unpredictable.
1416         (thumb32_opcodes): New instructions for bfx and bflx.
1417
1418 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1419
1420         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1421
1422 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1423
1424         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1425
1426 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1427
1428         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1429
1430 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1431
1432         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1433
1434 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1435
1436         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1437         "optr". ("operator" is a reserved word in c++).
1438
1439 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1440
1441         * aarch64-opc.c (aarch64_print_operand): Add case for
1442         AARCH64_OPND_Rt_SP.
1443         (verify_constraints): Likewise.
1444         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1445         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1446         to accept Rt|SP as first operand.
1447         (AARCH64_OPERANDS): Add new Rt_SP.
1448         * aarch64-asm-2.c: Regenerated.
1449         * aarch64-dis-2.c: Regenerated.
1450         * aarch64-opc-2.c: Regenerated.
1451
1452 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1453
1454         * aarch64-asm-2.c: Regenerated.
1455         * aarch64-dis-2.c: Likewise.
1456         * aarch64-opc-2.c: Likewise.
1457         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1458
1459 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1460
1461         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1462
1463 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1464
1465         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1466         * i386-init.h: Regenerated.
1467
1468 2019-04-07  Alan Modra  <amodra@gmail.com>
1469
1470         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1471         op_separator to control printing of spaces, comma and parens
1472         rather than need_comma, need_paren and spaces vars.
1473
1474 2019-04-07  Alan Modra  <amodra@gmail.com>
1475
1476         PR 24421
1477         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1478         (print_insn_neon, print_insn_arm): Likewise.
1479
1480 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1481
1482         * i386-dis-evex.h (evex_table): Updated to support BF16
1483         instructions.
1484         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1485         and EVEX_W_0F3872_P_3.
1486         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1487         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1488         * i386-opc.h (enum): Add CpuAVX512_BF16.
1489         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1490         * i386-opc.tbl: Add AVX512 BF16 instructions.
1491         * i386-init.h: Regenerated.
1492         * i386-tbl.h: Likewise.
1493
1494 2019-04-05  Alan Modra  <amodra@gmail.com>
1495
1496         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1497         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1498         to favour printing of "-" branch hint when using the "y" bit.
1499         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1500
1501 2019-04-05  Alan Modra  <amodra@gmail.com>
1502
1503         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1504         opcode until first operand is output.
1505
1506 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1507
1508         PR gas/24349
1509         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1510         (valid_bo_post_v2): Add support for 'at' branch hints.
1511         (insert_bo): Only error on branch on ctr.
1512         (get_bo_hint_mask): New function.
1513         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1514         for inserting 'at' branch hints.
1515         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1516         for extracting 'at' branch hints.
1517         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1518         (BOE): Delete operand.
1519         (BOM, BOP): New operands.
1520         (RM): Update value.
1521         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1522         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1523         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1524         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1525         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1526         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1527         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1528         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1529         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1530         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1531         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1532         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1533         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1534         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1535         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1536         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1537         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1538         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1539         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1540         bttarl+>: New extended mnemonics.
1541
1542 2019-03-28  Alan Modra  <amodra@gmail.com>
1543
1544         PR 24390
1545         * ppc-opc.c (BTF): Define.
1546         (powerpc_opcodes): Use for mtfsb*.
1547         * ppc-dis.c (print_insn_powerpc): Print fields with both
1548         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1549
1550 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1551
1552         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1553         (mapping_symbol_for_insn): Implement new algorithm.
1554         (print_insn): Remove duplicate code.
1555
1556 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1557
1558         * aarch64-dis.c (print_insn_aarch64):
1559         Implement override.
1560
1561 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1562
1563         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1564         order.
1565
1566 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1567
1568         * aarch64-dis.c (last_stop_offset): New.
1569         (print_insn_aarch64): Use stop_offset.
1570
1571 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1572
1573         PR gas/24359
1574         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1575         CPU_ANY_AVX2_FLAGS.
1576         * i386-init.h: Regenerated.
1577
1578 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1579
1580         PR gas/24348
1581         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1582         vmovdqu16, vmovdqu32 and vmovdqu64.
1583         * i386-tbl.h: Regenerated.
1584
1585 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1586
1587         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1588         from vstrszb, vstrszh, and vstrszf.
1589
1590 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1591
1592         * s390-opc.txt: Add instruction descriptions.
1593
1594 2019-02-08  Jim Wilson  <jimw@sifive.com>
1595
1596         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1597         <bne>: Likewise.
1598
1599 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1600
1601         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1602
1603 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1604
1605         PR binutils/23212
1606         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1607         * aarch64-opc.c (verify_elem_sd): New.
1608         (fields): Add FLD_sz entr.
1609         * aarch64-tbl.h (_SIMD_INSN): New.
1610         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1611         fmulx scalar and vector by element isns.
1612
1613 2019-02-07  Nick Clifton  <nickc@redhat.com>
1614
1615         * po/sv.po: Updated Swedish translation.
1616
1617 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1618
1619         * s390-mkopc.c (main): Accept arch13 as cpu string.
1620         * s390-opc.c: Add new instruction formats and instruction opcode
1621         masks.
1622         * s390-opc.txt: Add new arch13 instructions.
1623
1624 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1625
1626         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1627         (aarch64_opcode): Change encoding for stg, stzg
1628         st2g and st2zg.
1629         * aarch64-asm-2.c: Regenerated.
1630         * aarch64-dis-2.c: Regenerated.
1631         * aarch64-opc-2.c: Regenerated.
1632
1633 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1634
1635         * aarch64-asm-2.c: Regenerated.
1636         * aarch64-dis-2.c: Likewise.
1637         * aarch64-opc-2.c: Likewise.
1638         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1639
1640 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1641             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1642
1643         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1644         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1645         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1646         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1647         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1648         case for ldstgv_indexed.
1649         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1650         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1651         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1652         * aarch64-asm-2.c: Regenerated.
1653         * aarch64-dis-2.c: Regenerated.
1654         * aarch64-opc-2.c: Regenerated.
1655
1656 2019-01-23  Nick Clifton  <nickc@redhat.com>
1657
1658         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1659
1660 2019-01-21  Nick Clifton  <nickc@redhat.com>
1661
1662         * po/de.po: Updated German translation.
1663         * po/uk.po: Updated Ukranian translation.
1664
1665 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1666         * mips-dis.c (mips_arch_choices): Fix typo in
1667         gs464, gs464e and gs264e descriptors.
1668
1669 2019-01-19  Nick Clifton  <nickc@redhat.com>
1670
1671         * configure: Regenerate.
1672         * po/opcodes.pot: Regenerate.
1673
1674 2018-06-24  Nick Clifton  <nickc@redhat.com>
1675
1676         2.32 branch created.
1677
1678 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1679
1680         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1681         if it is null.
1682         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1683         zero.
1684
1685 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1686
1687         * configure: Regenerate.
1688
1689 2019-01-07  Alan Modra  <amodra@gmail.com>
1690
1691         * configure: Regenerate.
1692         * po/POTFILES.in: Regenerate.
1693
1694 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1695
1696         * s12z-opc.c: New file.
1697         * s12z-opc.h: New file.
1698         * s12z-dis.c: Removed all code not directly related to display
1699         of instructions.  Used the interface provided by the new files
1700         instead.
1701         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1702         * Makefile.in: Regenerate.
1703         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1704         * configure: Regenerate.
1705
1706 2019-01-01  Alan Modra  <amodra@gmail.com>
1707
1708         Update year range in copyright notice of all files.
1709
1710 For older changes see ChangeLog-2018
1711 \f
1712 Copyright (C) 2019 Free Software Foundation, Inc.
1713
1714 Copying and distribution of this file, with or without modification,
1715 are permitted in any medium without royalty provided the copyright
1716 notice and this notice are preserved.
1717
1718 Local Variables:
1719 mode: change-log
1720 left-margin: 8
1721 fill-column: 74
1722 version-control: never
1723 End: