opcodes/ChangeLog

   1 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (cpu_flag_init): Replace CpuABM with
   4         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
   5         CPU_POPCNT_FLAGS.
   6         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
   7         * i386-opc.h (CpuABM): Removed.
   8         (CpuPOPCNT): New.
   9         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  10         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  11         popcnt.  Remove CpuABM from lzcnt.
  12         * i386-init.h: Regenerated.
  13         * i386-tbl.h: Likewise.
  14
  15 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  18         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  19         VexW1 instead of open-coding them.
  20         * i386-tbl.h: Re-generate.
  21
  22 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (AddrPrefixOpReg): Define.
  25         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  26         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  27         templates. Drop NoRex64.
  28         * i386-tbl.h: Re-generate.
  29
  30 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  31
  32         PR gas/6518
  33         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  34         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  35         into Intel syntax instance (with Unpsecified) and AT&T one
  36         (without).
  37         (vcvtneps2bf16): Likewise, along with folding the two so far
  38         separate ones.
  39         * i386-tbl.h: Re-generate.
  40
  41 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  44         CPU_ANY_SSE4A_FLAGS.
  45
  46 2020-02-17  Alan Modra  <amodra@gmail.com>
  47
  48         * i386-gen.c (cpu_flag_init): Correct last change.
  49
  50 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  53         CPU_ANY_SSE4_FLAGS.
  54
  55 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  58         (movzx): Likewise.
  59
  60 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  61
  62         PR gas/25438
  63         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  64         destination for Cpu64-only variant.
  65         (movzx): Fold patterns.
  66         * i386-tbl.h: Re-generate.
  67
  68 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  71         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  72         CPU_ANY_SSE4_FLAGS entry.
  73         * i386-init.h: Re-generate.
  74
  75 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  78         with Unspecified, making the present one AT&T syntax only.
  79         * i386-tbl.h: Re-generate.
  80
  81 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  84         * i386-tbl.h: Re-generate.
  85
  86 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  87
  88         PR gas/24546
  89         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  90         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  91         Amd64 and Intel64 templates.
  92         (call, jmp): Likewise for far indirect variants. Dro
  93         Unspecified.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  99         * i386-opc.h (ShortForm): Delete.
 100         (struct i386_opcode_modifier): Remove shortform field.
 101         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 102         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 103         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 104         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 105         Drop ShortForm.
 106         * i386-tbl.h: Re-generate.
 107
 108 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 111         fucompi): Drop ShortForm from operand-less templates.
 112         * i386-tbl.h: Re-generate.
 113
 114 2020-02-11  Alan Modra  <amodra@gmail.com>
 115
 116         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 117         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 118         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 119         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 120         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 121
 122 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 123
 124         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 125         (cde_opcodes): Add VCX* instructions.
 126
 127 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 128             Matthew Malcomson  <matthew.malcomson@arm.com>
 129
 130         * arm-dis.c (struct cdeopcode32): New.
 131         (CDE_OPCODE): New macro.
 132         (cde_opcodes): New disassembly table.
 133         (regnames): New option to table.
 134         (cde_coprocs): New global variable.
 135         (print_insn_cde): New
 136         (print_insn_thumb32): Use print_insn_cde.
 137         (parse_arm_disassembler_options): Parse coprocN args.
 138
 139 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 140
 141         PR gas/25516
 142         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 143         with ISA64.
 144         * i386-opc.h (AMD64): Removed.
 145         (Intel64): Likewose.
 146         (AMD64): New.
 147         (INTEL64): Likewise.
 148         (INTEL64ONLY): Likewise.
 149         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 150         * i386-opc.tbl (Amd64): New.
 151         (Intel64): Likewise.
 152         (Intel64Only): Likewise.
 153         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 154         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 155         * i386-tbl.h: Regenerated.
 156
 157 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 158
 159         PR 25469
 160         * z80-dis.c: Add support for GBZ80 opcodes.
 161
 162 2020-02-04  Alan Modra  <amodra@gmail.com>
 163
 164         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 165
 166 2020-02-03  Alan Modra  <amodra@gmail.com>
 167
 168         * m32c-ibld.c: Regenerate.
 169
 170 2020-02-01  Alan Modra  <amodra@gmail.com>
 171
 172         * frv-ibld.c: Regenerate.
 173
 174 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 177         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 178         (OP_E_memory): Replace xmm_mdq_mode case label by
 179         vex_scalar_w_dq_mode one.
 180         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 181
 182 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 185         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 186         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 187         (intel_operand_size): Drop vex_w_dq_mode case label.
 188
 189 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 190
 191         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 192         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 193
 194 2020-01-30  Alan Modra  <amodra@gmail.com>
 195
 196         * m32c-ibld.c: Regenerate.
 197
 198 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 199
 200         * bpf-opc.c: Regenerate.
 201
 202 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 205         (dis386): Use them to replace C2/C3 table entries.
 206         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 207         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 208         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 209         * i386-tbl.h: Re-generate.
 210
 211 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 214         forms.
 215         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 216         DefaultSize.
 217         * i386-tbl.h: Re-generate.
 218
 219 2020-01-30  Alan Modra  <amodra@gmail.com>
 220
 221         * tic4x-dis.c (tic4x_dp): Make unsigned.
 222
 223 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 224             Jan Beulich  <jbeulich@suse.com>
 225
 226         PR binutils/25445
 227         * i386-dis.c (MOVSXD_Fixup): New function.
 228         (movsxd_mode): New enum.
 229         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 230         (intel_operand_size): Handle movsxd_mode.
 231         (OP_E_register): Likewise.
 232         (OP_G): Likewise.
 233         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 234         register on movsxd.  Add movsxd with 16-bit destination register
 235         for AMD64 and Intel64 ISAs.
 236         * i386-tbl.h: Regenerated.
 237
 238 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 239
 240         PR 25403
 241         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 242         * aarch64-asm-2.c: Regenerate
 243         * aarch64-dis-2.c: Likewise.
 244         * aarch64-opc-2.c: Likewise.
 245
 246 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-opc.tbl (sysret): Drop DefaultSize.
 249         * i386-tbl.h: Re-generate.
 250
 251 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 254         Dword.
 255         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 256         * i386-tbl.h: Re-generate.
 257
 258 2020-01-20  Nick Clifton  <nickc@redhat.com>
 259
 260         * po/de.po: Updated German translation.
 261         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 262         * po/uk.po: Updated Ukranian translation.
 263
 264 2020-01-20  Alan Modra  <amodra@gmail.com>
 265
 266         * hppa-dis.c (fput_const): Remove useless cast.
 267
 268 2020-01-20  Alan Modra  <amodra@gmail.com>
 269
 270         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 271
 272 2020-01-18  Nick Clifton  <nickc@redhat.com>
 273
 274         * configure: Regenerate.
 275         * po/opcodes.pot: Regenerate.
 276
 277 2020-01-18  Nick Clifton  <nickc@redhat.com>
 278
 279         Binutils 2.34 branch created.
 280
 281 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 282
 283         * opintl.h: Fix spelling error (seperate).
 284
 285 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 286
 287         * i386-opc.tbl: Add {vex} pseudo prefix.
 288         * i386-tbl.h: Regenerated.
 289
 290 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 291
 292         PR 25376
 293         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 294         (neon_opcodes): Likewise.
 295         (select_arm_features): Make sure we enable MVE bits when selecting
 296         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 297         any architecture.
 298
 299 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-opc.tbl: Drop stale comment from XOP section.
 302
 303 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 306         (extractps): Add VexWIG to SSE2AVX forms.
 307         * i386-tbl.h: Re-generate.
 308
 309 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 312         Size64 from and use VexW1 on SSE2AVX forms.
 313         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 314         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 315         * i386-tbl.h: Re-generate.
 316
 317 2020-01-15  Alan Modra  <amodra@gmail.com>
 318
 319         * tic4x-dis.c (tic4x_version): Make unsigned long.
 320         (optab, optab_special, registernames): New file scope vars.
 321         (tic4x_print_register): Set up registernames rather than
 322         malloc'd registertable.
 323         (tic4x_disassemble): Delete optable and optable_special.  Use
 324         optab and optab_special instead.  Throw away old optab,
 325         optab_special and registernames when info->mach changes.
 326
 327 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 328
 329         PR 25377
 330         * z80-dis.c (suffix): Use .db instruction to generate double
 331         prefix.
 332
 333 2020-01-14  Alan Modra  <amodra@gmail.com>
 334
 335         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 336         values to unsigned before shifting.
 337
 338 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 339
 340         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 341         flow instructions.
 342         (print_insn_thumb16, print_insn_thumb32): Likewise.
 343         (print_insn): Initialize the insn info.
 344         * i386-dis.c (print_insn): Initialize the insn info fields, and
 345         detect jumps.
 346
 347 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 348
 349         * arc-opc.c (C_NE): Make it required.
 350
 351 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 352
 353         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 354         reserved register name.
 355
 356 2020-01-13  Alan Modra  <amodra@gmail.com>
 357
 358         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 359         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 360
 361 2020-01-13  Alan Modra  <amodra@gmail.com>
 362
 363         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 364         result of wasm_read_leb128 in a uint64_t and check that bits
 365         are not lost when copying to other locals.  Use uint32_t for
 366         most locals.  Use PRId64 when printing int64_t.
 367
 368 2020-01-13  Alan Modra  <amodra@gmail.com>
 369
 370         * score-dis.c: Formatting.
 371         * score7-dis.c: Formatting.
 372
 373 2020-01-13  Alan Modra  <amodra@gmail.com>
 374
 375         * score-dis.c (print_insn_score48): Use unsigned variables for
 376         unsigned values.  Don't left shift negative values.
 377         (print_insn_score32): Likewise.
 378         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 379
 380 2020-01-13  Alan Modra  <amodra@gmail.com>
 381
 382         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 383
 384 2020-01-13  Alan Modra  <amodra@gmail.com>
 385
 386         * fr30-ibld.c: Regenerate.
 387
 388 2020-01-13  Alan Modra  <amodra@gmail.com>
 389
 390         * xgate-dis.c (print_insn): Don't left shift signed value.
 391         (ripBits): Formatting, use 1u.
 392
 393 2020-01-10  Alan Modra  <amodra@gmail.com>
 394
 395         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 396         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 397
 398 2020-01-10  Alan Modra  <amodra@gmail.com>
 399
 400         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 401         and XRREG value earlier to avoid a shift with negative exponent.
 402         * m10200-dis.c (disassemble): Similarly.
 403
 404 2020-01-09  Nick Clifton  <nickc@redhat.com>
 405
 406         PR 25224
 407         * z80-dis.c (ld_ii_ii): Use correct cast.
 408
 409 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 410
 411         PR 25224
 412         * z80-dis.c (ld_ii_ii): Use character constant when checking
 413         opcode byte value.
 414
 415 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-dis.c (SEP_Fixup): New.
 418         (SEP): Define.
 419         (dis386_twobyte): Use it for sysenter/sysexit.
 420         (enum x86_64_isa): Change amd64 enumerator to value 1.
 421         (OP_J): Compare isa64 against intel64 instead of amd64.
 422         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 423         forms.
 424         * i386-tbl.h: Re-generate.
 425
 426 2020-01-08  Alan Modra  <amodra@gmail.com>
 427
 428         * z8k-dis.c: Include libiberty.h
 429         (instr_data_s): Make max_fetched unsigned.
 430         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 431         Don't exceed byte_info bounds.
 432         (output_instr): Make num_bytes unsigned.
 433         (unpack_instr): Likewise for nibl_count and loop.
 434         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 435         idx unsigned.
 436         * z8k-opc.h: Regenerate.
 437
 438 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 439
 440         * arc-tbl.h (llock): Use 'LLOCK' as class.
 441         (llockd): Likewise.
 442         (scond): Use 'SCOND' as class.
 443         (scondd): Likewise.
 444         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 445         (scondd): Likewise.
 446
 447 2020-01-06  Alan Modra  <amodra@gmail.com>
 448
 449         * m32c-ibld.c: Regenerate.
 450
 451 2020-01-06  Alan Modra  <amodra@gmail.com>
 452
 453         PR 25344
 454         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 455         Peek at next byte to prevent recursion on repeated prefix bytes.
 456         Ensure uninitialised "mybuf" is not accessed.
 457         (print_insn_z80): Don't zero n_fetch and n_used here,..
 458         (print_insn_z80_buf): ..do it here instead.
 459
 460 2020-01-04  Alan Modra  <amodra@gmail.com>
 461
 462         * m32r-ibld.c: Regenerate.
 463
 464 2020-01-04  Alan Modra  <amodra@gmail.com>
 465
 466         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 467
 468 2020-01-04  Alan Modra  <amodra@gmail.com>
 469
 470         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 471
 472 2020-01-04  Alan Modra  <amodra@gmail.com>
 473
 474         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 475
 476 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 477
 478         * aarch64-tbl.h (aarch64_opcode_table): Use
 479         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 480
 481 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 482
 483         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 484         forms of SUDOT and USDOT.
 485
 486 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 487
 488         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 489         uzip{1,2}.
 490         * opcodes/aarch64-dis-2.c: Re-generate.
 491
 492 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 493
 494         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 495         FMMLA encoding.
 496         * opcodes/aarch64-dis-2.c: Re-generate.
 497
 498 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 499
 500         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 501
 502 2020-01-01  Alan Modra  <amodra@gmail.com>
 503
 504         Update year range in copyright notice of all files.
 505
 506 For older changes see ChangeLog-2019
 507 \f
 508 Copyright (C) 2020 Free Software Foundation, Inc.
 509
 510 Copying and distribution of this file, with or without modification,
 511 are permitted in any medium without royalty provided the copyright
 512 notice and this notice are preserved.
 513
 514 Local Variables:
 515 mode: change-log
 516 left-margin: 8
 517 fill-column: 74
 518 version-control: never
 519 End: