1 2016-12-20 Andrew Waterman <andrew@sifive.com>
3 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
4 XLEN when none is provided.
6 2016-12-20 Andrew Waterman <andrew@sifive.com>
8 * riscv-opc.c: Formatting fixes.
10 2016-12-20 Alan Modra <amodra@gmail.com>
12 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
13 * Makefile.in: Regenerate.
14 * po/POTFILES.in: Regenerate.
16 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
18 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
19 Only examine ELF file structures here.
21 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
23 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
24 `bfd_mips_elf_get_abiflags' here.
26 2016-12-16 Nick Clifton <nickc@redhat.com>
28 * arm-dis.c (print_insn_thumb32): Fix compile time warning
29 computing value_in_comment.
31 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
33 * mips-dis.c (mips_convert_abiflags_ases): New function.
34 (set_default_mips_dis_options): Also infer ASE flags from ELF
37 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
39 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
40 header flag interpretation code.
42 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
44 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
45 `pinfo2' with SP-relative "sd" entries.
47 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
49 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
52 2016-12-13 Renlin Li <renlin.li@arm.com>
54 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
56 (operand_general_constraint_met_p): Remove case for CP_REG.
57 (aarch64_print_operand): Print CRn, CRm operand using imm field.
58 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
60 (aarch64_opcode_table): Change CRn, CRm operand class and type.
61 * aarch64-opc-2.c : Regenerate.
62 * aarch64-asm-2.c : Likewise.
63 * aarch64-dis-2.c : Likewise.
65 2016-12-12 Yao Qi <yao.qi@linaro.org>
67 * rx-dis.c: Include <setjmp.h>
68 (struct private): New.
69 (rx_get_byte): Check return value of read_memory_func, and
70 call memory_error_func and OPCODES_SIGLONGJMP on error.
71 (print_insn_rx): Call OPCODES_SIGSETJMP.
73 2016-12-12 Yao Qi <yao.qi@linaro.org>
75 * rl78-dis.c: Include <setjmp.h>.
76 (struct private): New.
77 (rl78_get_byte): Check return value of read_memory_func, and
78 call memory_error_func and OPCODES_SIGLONGJMP on error.
79 (print_insn_rl78_common): Call OPCODES_SIGJMP.
81 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
83 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
85 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
87 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
90 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
92 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
93 to separate `extend' and its uninterpreted argument output.
94 Separate hexadecimal halves of undecoded extended instructions
97 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
99 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
100 indentation space across.
102 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
104 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
105 adjustment for PC-relative operations following MIPS16e compact
106 jumps or undefined RR/J(AL)R(C) encodings.
108 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
110 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
111 variable to `reglane_index'.
113 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
115 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
117 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
119 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
121 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
123 * mips16-opc.c (mips16_opcodes): Update comment naming structure
126 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
128 * mips-dis.c (print_mips_disassembler_options): Reformat output.
130 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
132 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
133 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
135 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
137 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
139 2016-12-01 Nick Clifton <nickc@redhat.com>
142 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
145 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
147 * arc-opc.c (insert_ra_chk): New function.
148 (insert_rb_chk): Likewise.
149 (insert_rad): Update text error message.
150 (insert_rcd): Likewise.
151 (insert_rhv2): Likewise.
152 (insert_r0): Likewise.
153 (insert_r1): Likewise.
154 (insert_r2): Likewise.
155 (insert_r3): Likewise.
156 (insert_sp): Likewise.
157 (insert_gp): Likewise.
158 (insert_pcl): Likewise.
159 (insert_blink): Likewise.
160 (insert_ilink1): Likewise.
161 (insert_ilink2): Likewise.
162 (insert_ras): Likewise.
163 (insert_rbs): Likewise.
164 (insert_rcs): Likewise.
165 (insert_simm3s): Likewise.
166 (insert_rrange): Likewise.
167 (insert_fpel): Likewise.
168 (insert_blinkel): Likewise.
169 (insert_pcel): Likewise.
170 (insert_nps_3bit_dst): Likewise.
171 (insert_nps_3bit_dst_short): Likewise.
172 (insert_nps_3bit_src2_short): Likewise.
173 (insert_nps_bitop_size_2b): Likewise.
174 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
179 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
180 * arc-tbl.h (div, divu): All instructions are DIVREM class.
181 Change first insn argument to check for LP_COUNT usage.
183 (ld, ldd): All instructions are LOAD class. Change first insn
184 argument to check for LP_COUNT usage.
185 (st, std): All instructions are STORE class.
186 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
187 Change first insn argument to check for LP_COUNT usage.
188 (mov): All instructions are MOVE class. Change first insn
189 argument to check for LP_COUNT usage.
191 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
193 * arc-dis.c (is_compatible_p): Remove function.
194 (skip_this_opcode): Don't add any decoding class to decode list.
196 (find_format_from_table): Go through all opcodes, and warn if we
197 use a guessed mnemonic.
199 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
200 Amit Pawar <amit.pawar@amd.com>
203 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
206 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
208 * configure: Regenerate.
210 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
212 * sparc-opc.c (HWS_V8): Definition moved from
213 gas/config/tc-sparc.c.
223 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
226 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
228 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
231 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
233 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
234 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
235 (aarch64_opcode_table): Add fcmla and fcadd.
236 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
237 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
238 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
239 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
240 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
241 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
242 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
243 (operand_general_constraint_met_p): Rotate and index range check.
244 (aarch64_print_operand): Handle rotate operand.
245 * aarch64-asm-2.c: Regenerate.
246 * aarch64-dis-2.c: Likewise.
247 * aarch64-opc-2.c: Likewise.
249 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
251 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
252 * aarch64-asm-2.c: Regenerate.
253 * aarch64-dis-2.c: Regenerate.
254 * aarch64-opc-2.c: Regenerate.
256 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
258 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
259 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
260 * aarch64-asm-2.c: Regenerate.
261 * aarch64-dis-2.c: Regenerate.
262 * aarch64-opc-2.c: Regenerate.
264 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
266 * aarch64-tbl.h (QL_X1NIL): New.
267 (arch64_opcode_table): Add ldraa, ldrab.
268 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
269 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
270 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
271 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
272 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
273 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
274 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
275 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
276 (aarch64_print_operand): Likewise.
277 * aarch64-asm-2.c: Regenerate.
278 * aarch64-dis-2.c: Regenerate.
279 * aarch64-opc-2.c: Regenerate.
281 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
283 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
284 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
285 * aarch64-asm-2.c: Regenerate.
286 * aarch64-dis-2.c: Regenerate.
287 * aarch64-opc-2.c: Regenerate.
289 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
291 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
292 (AARCH64_OPERANDS): Add Rm_SP.
293 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
294 * aarch64-asm-2.c: Regenerate.
295 * aarch64-dis-2.c: Regenerate.
296 * aarch64-opc-2.c: Regenerate.
298 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
300 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
301 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
302 autdzb, xpaci, xpacd.
303 * aarch64-asm-2.c: Regenerate.
304 * aarch64-dis-2.c: Regenerate.
305 * aarch64-opc-2.c: Regenerate.
307 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
309 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
310 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
311 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
312 (aarch64_sys_reg_supported_p): Add feature test for new registers.
314 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
316 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
317 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
318 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
320 * aarch64-asm-2.c: Regenerate.
321 * aarch64-dis-2.c: Regenerate.
323 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
325 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
327 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
330 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
331 * i386-dis.c (EdqwS): Removed.
332 (dqw_swap_mode): Likewise.
333 (intel_operand_size): Don't check dqw_swap_mode.
334 (OP_E_register): Likewise.
335 (OP_E_memory): Likewise.
338 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
339 * i386-tbl.h: Regerated.
341 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
343 * i386-opc.tbl: Merge AVX512F vmovq.
344 * i386-tbl.h: Regerated.
346 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
349 * i386-dis.c (THREE_BYTE_0F7A): Removed.
350 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
351 (three_byte_table): Remove THREE_BYTE_0F7A.
353 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
356 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
357 (FGRPd9_4): Replace 1 with 2.
358 (FGRPd9_5): Replace 2 with 3.
359 (FGRPd9_6): Replace 3 with 4.
360 (FGRPd9_7): Replace 4 with 5.
361 (FGRPda_5): Replace 5 with 6.
362 (FGRPdb_4): Replace 6 with 7.
363 (FGRPde_3): Replace 7 with 8.
364 (FGRPdf_4): Replace 8 with 9.
365 (fgrps): Add an entry for Bad_Opcode.
367 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
369 * arc-opc.c (arc_flag_operands): Add F_DI14.
370 (arc_flag_classes): Add C_DI14.
371 * arc-nps400-tbl.h: Add new exc instructions.
373 2016-11-03 Graham Markall <graham.markall@embecosm.com>
375 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
377 * arc-nps-400-tbl.h: Add dcmac instruction.
378 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
379 (insert_nps_rbdouble_64): Added.
380 (extract_nps_rbdouble_64): Added.
381 (insert_nps_proto_size): Added.
382 (extract_nps_proto_size): Added.
384 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
386 * arc-dis.c (struct arc_operand_iterator): Remove all fields
387 relating to long instruction processing, add new limm field.
388 (OPCODE): Rename to...
389 (OPCODE_32BIT_INSN): ...this.
391 (skip_this_opcode): Handle different instruction lengths, update
393 (special_flag_p): Update parameter type.
394 (find_format_from_table): Update for more instruction lengths.
395 (find_format_long_instructions): Delete.
396 (find_format): Update for more instruction lengths.
397 (arc_insn_length): Likewise.
398 (extract_operand_value): Update for more instruction lengths.
399 (operand_iterator_next): Remove code relating to long
401 (arc_opcode_to_insn_type): New function.
402 (print_insn_arc):Update for more instructions lengths.
403 * arc-ext.c (extInstruction_t): Change argument type.
404 * arc-ext.h (extInstruction_t): Change argument type.
405 * arc-fxi.h: Change type unsigned to unsigned long long
406 extensively throughout.
407 * arc-nps400-tbl.h: Add long instructions taken from
408 arc_long_opcodes table in arc-opc.c.
409 * arc-opc.c: Update parameter types on insert/extract handlers.
410 (arc_long_opcodes): Delete.
411 (arc_num_long_opcodes): Delete.
412 (arc_opcode_len): Update for more instruction lengths.
414 2016-11-03 Graham Markall <graham.markall@embecosm.com>
416 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
418 2016-11-03 Graham Markall <graham.markall@embecosm.com>
420 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
422 (find_format_long_instructions): Likewise.
423 * arc-opc.c (arc_opcode_len): New function.
425 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
427 * arc-nps400-tbl.h: Fix some instruction masks.
429 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
431 * i386-dis.c (REG_82): Removed.
432 (X86_64_82_REG_0): Likewise.
433 (X86_64_82_REG_1): Likewise.
434 (X86_64_82_REG_2): Likewise.
435 (X86_64_82_REG_3): Likewise.
436 (X86_64_82_REG_4): Likewise.
437 (X86_64_82_REG_5): Likewise.
438 (X86_64_82_REG_6): Likewise.
439 (X86_64_82_REG_7): Likewise.
441 (dis386): Use X86_64_82 instead of REG_82.
442 (reg_table): Remove REG_82.
443 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
444 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
445 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
448 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
451 * i386-dis.c (REG_82): New.
452 (X86_64_82_REG_0): Likewise.
453 (X86_64_82_REG_1): Likewise.
454 (X86_64_82_REG_2): Likewise.
455 (X86_64_82_REG_3): Likewise.
456 (X86_64_82_REG_4): Likewise.
457 (X86_64_82_REG_5): Likewise.
458 (X86_64_82_REG_6): Likewise.
459 (X86_64_82_REG_7): Likewise.
460 (dis386): Use REG_82.
461 (reg_table): Add REG_82.
462 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
463 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
464 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
466 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
468 * i386-dis.c (REG_82): Renamed to ...
471 (reg_table): Likewise.
473 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
475 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
476 * i386-dis-evex.h (evex_table): Updated.
477 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
478 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
479 (cpu_flags): Add CpuAVX512_4VNNIW.
480 * i386-opc.h (enum): (AVX512_4VNNIW): New.
481 (i386_cpu_flags): Add cpuavx512_4vnniw.
482 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
483 * i386-init.h: Regenerate.
486 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
488 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
489 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
490 * i386-dis-evex.h (evex_table): Updated.
491 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
492 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
493 (cpu_flags): Add CpuAVX512_4FMAPS.
494 (opcode_modifiers): Add ImplicitQuadGroup modifier.
495 * i386-opc.h (AVX512_4FMAP): New.
496 (i386_cpu_flags): Add cpuavx512_4fmaps.
497 (ImplicitQuadGroup): New.
498 (i386_opcode_modifier): Add implicitquadgroup.
499 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
500 * i386-init.h: Regenerate.
503 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
504 Andrew Waterman <andrew@sifive.com>
506 Add support for RISC-V architecture.
507 * configure.ac: Add entry for bfd_riscv_arch.
508 * configure: Regenerate.
509 * disassemble.c (disassembler): Add support for riscv.
510 (disassembler_usage): Likewise.
511 * riscv-dis.c: New file.
512 * riscv-opc.c: New file.
514 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
516 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
517 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
518 (rm_table): Update the RM_0FAE_REG_7 entry.
519 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
520 (cpu_flags): Remove CpuPCOMMIT.
521 * i386-opc.h (CpuPCOMMIT): Removed.
522 (i386_cpu_flags): Remove cpupcommit.
523 * i386-opc.tbl: Remove pcommit.
524 * i386-init.h: Regenerated.
525 * i386-tbl.h: Likewise.
527 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
531 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
532 32-bit mode. Don't check vex.register_specifier in 32-bit
534 (OP_VEX): Check for invalid mask registers.
536 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
542 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
545 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
547 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
549 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
550 local variable to `index_regno'.
552 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
554 * arc-tbl.h: Removed any "inv.+" instructions from the table.
556 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
558 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
561 2016-10-11 Jiong Wang <jiong.wang@arm.com>
564 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
566 2016-10-07 Jiong Wang <jiong.wang@arm.com>
569 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
572 2016-10-07 Alan Modra <amodra@gmail.com>
574 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
576 2016-10-06 Alan Modra <amodra@gmail.com>
578 * aarch64-opc.c: Spell fall through comments consistently.
579 * i386-dis.c: Likewise.
580 * aarch64-dis.c: Add missing fall through comments.
581 * aarch64-opc.c: Likewise.
582 * arc-dis.c: Likewise.
583 * arm-dis.c: Likewise.
584 * i386-dis.c: Likewise.
585 * m68k-dis.c: Likewise.
586 * mep-asm.c: Likewise.
587 * ns32k-dis.c: Likewise.
588 * sh-dis.c: Likewise.
589 * tic4x-dis.c: Likewise.
590 * tic6x-dis.c: Likewise.
591 * vax-dis.c: Likewise.
593 2016-10-06 Alan Modra <amodra@gmail.com>
595 * arc-ext.c (create_map): Add missing break.
596 * msp430-decode.opc (encode_as): Likewise.
597 * msp430-decode.c: Regenerate.
599 2016-10-06 Alan Modra <amodra@gmail.com>
601 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
602 * crx-dis.c (print_insn_crx): Likewise.
604 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
607 * i386-dis.c (putop): Don't assign alt twice.
609 2016-09-29 Jiong Wang <jiong.wang@arm.com>
612 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
614 2016-09-29 Alan Modra <amodra@gmail.com>
616 * ppc-opc.c (L): Make compulsory.
617 (LOPT): New, optional form of L.
618 (HTM_R): Define as LOPT.
620 (L32OPT): New, optional for 32-bit L.
621 (L2OPT): New, 2-bit L for dcbf.
624 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
625 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
627 <tlbiel, tlbie>: Use LOPT.
628 <wclr, wclrall>: Use L2.
630 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
632 * Makefile.in: Regenerate.
633 * configure: Likewise.
635 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
637 * arc-ext-tbl.h (EXTINSN2OPF): Define.
638 (EXTINSN2OP): Use EXTINSN2OPF.
639 (bspeekm, bspop, modapp): New extension instructions.
640 * arc-opc.c (F_DNZ_ND): Define.
645 * arc-tbl.h (dbnz): New instruction.
646 (prealloc): Allow it for ARC EM.
649 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
651 * aarch64-opc.c (print_immediate_offset_address): Print spaces
652 after commas in addresses.
653 (aarch64_print_operand): Likewise.
655 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
657 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
658 rather than "should be" or "expected to be" in error messages.
660 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
662 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
663 (print_mnemonic_name): ...here.
664 (print_comment): New function.
665 (print_aarch64_insn): Call it.
666 * aarch64-opc.c (aarch64_conds): Add SVE names.
667 (aarch64_print_operand): Print alternative condition names in
670 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
672 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
673 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
674 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
675 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
676 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
677 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
678 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
679 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
680 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
681 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
682 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
683 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
684 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
685 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
686 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
687 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
688 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
689 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
690 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
691 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
692 (OP_SVE_XWU, OP_SVE_XXU): New macros.
693 (aarch64_feature_sve): New variable.
695 (_SVE_INSN): Likewise.
696 (aarch64_opcode_table): Add SVE instructions.
697 * aarch64-opc.h (extract_fields): Declare.
698 * aarch64-opc-2.c: Regenerate.
699 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
700 * aarch64-asm-2.c: Regenerate.
701 * aarch64-dis.c (extract_fields): Make global.
702 (do_misc_decoding): Handle the new SVE aarch64_ops.
703 * aarch64-dis-2.c: Regenerate.
705 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
707 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
708 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
710 * aarch64-opc.c (fields): Add corresponding entries.
711 * aarch64-asm.c (aarch64_get_variant): New function.
712 (aarch64_encode_variant_using_iclass): Likewise.
713 (aarch64_opcode_encode): Call it.
714 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
715 (aarch64_opcode_decode): Call it.
717 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
719 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
720 and FP register operands.
721 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
722 (FLD_SVE_Vn): New aarch64_field_kinds.
723 * aarch64-opc.c (fields): Add corresponding entries.
724 (aarch64_print_operand): Handle the new SVE core and FP register
726 * aarch64-opc-2.c: Regenerate.
727 * aarch64-asm-2.c: Likewise.
728 * aarch64-dis-2.c: Likewise.
730 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
732 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
734 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
735 * aarch64-opc.c (fields): Add corresponding entry.
736 (operand_general_constraint_met_p): Handle the new SVE FP immediate
738 (aarch64_print_operand): Likewise.
739 * aarch64-opc-2.c: Regenerate.
740 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
741 (ins_sve_float_zero_one): New inserters.
742 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
743 (aarch64_ins_sve_float_half_two): Likewise.
744 (aarch64_ins_sve_float_zero_one): Likewise.
745 * aarch64-asm-2.c: Regenerate.
746 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
747 (ext_sve_float_zero_one): New extractors.
748 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
749 (aarch64_ext_sve_float_half_two): Likewise.
750 (aarch64_ext_sve_float_zero_one): Likewise.
751 * aarch64-dis-2.c: Regenerate.
753 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
755 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
756 integer immediate operands.
757 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
758 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
759 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
760 * aarch64-opc.c (fields): Add corresponding entries.
761 (operand_general_constraint_met_p): Handle the new SVE integer
763 (aarch64_print_operand): Likewise.
764 (aarch64_sve_dupm_mov_immediate_p): New function.
765 * aarch64-opc-2.c: Regenerate.
766 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
767 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
768 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
769 (aarch64_ins_limm): ...here.
770 (aarch64_ins_inv_limm): New function.
771 (aarch64_ins_sve_aimm): Likewise.
772 (aarch64_ins_sve_asimm): Likewise.
773 (aarch64_ins_sve_limm_mov): Likewise.
774 (aarch64_ins_sve_shlimm): Likewise.
775 (aarch64_ins_sve_shrimm): Likewise.
776 * aarch64-asm-2.c: Regenerate.
777 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
778 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
779 * aarch64-dis.c (decode_limm): New function, split out from...
780 (aarch64_ext_limm): ...here.
781 (aarch64_ext_inv_limm): New function.
782 (decode_sve_aimm): Likewise.
783 (aarch64_ext_sve_aimm): Likewise.
784 (aarch64_ext_sve_asimm): Likewise.
785 (aarch64_ext_sve_limm_mov): Likewise.
786 (aarch64_top_bit): Likewise.
787 (aarch64_ext_sve_shlimm): Likewise.
788 (aarch64_ext_sve_shrimm): Likewise.
789 * aarch64-dis-2.c: Regenerate.
791 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
793 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
795 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
796 the AARCH64_MOD_MUL_VL entry.
797 (value_aligned_p): Cope with non-power-of-two alignments.
798 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
799 (print_immediate_offset_address): Likewise.
800 (aarch64_print_operand): Likewise.
801 * aarch64-opc-2.c: Regenerate.
802 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
803 (ins_sve_addr_ri_s9xvl): New inserters.
804 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
805 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
806 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
807 * aarch64-asm-2.c: Regenerate.
808 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
809 (ext_sve_addr_ri_s9xvl): New extractors.
810 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
811 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
812 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
813 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
814 * aarch64-dis-2.c: Regenerate.
816 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
818 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
820 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
821 (FLD_SVE_xs_22): New aarch64_field_kinds.
822 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
823 (get_operand_specific_data): New function.
824 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
825 FLD_SVE_xs_14 and FLD_SVE_xs_22.
826 (operand_general_constraint_met_p): Handle the new SVE address
828 (sve_reg): New array.
829 (get_addr_sve_reg_name): New function.
830 (aarch64_print_operand): Handle the new SVE address operands.
831 * aarch64-opc-2.c: Regenerate.
832 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
833 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
834 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
835 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
836 (aarch64_ins_sve_addr_rr_lsl): Likewise.
837 (aarch64_ins_sve_addr_rz_xtw): Likewise.
838 (aarch64_ins_sve_addr_zi_u5): Likewise.
839 (aarch64_ins_sve_addr_zz): Likewise.
840 (aarch64_ins_sve_addr_zz_lsl): Likewise.
841 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
842 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
843 * aarch64-asm-2.c: Regenerate.
844 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
845 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
846 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
847 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
848 (aarch64_ext_sve_addr_ri_u6): Likewise.
849 (aarch64_ext_sve_addr_rr_lsl): Likewise.
850 (aarch64_ext_sve_addr_rz_xtw): Likewise.
851 (aarch64_ext_sve_addr_zi_u5): Likewise.
852 (aarch64_ext_sve_addr_zz): Likewise.
853 (aarch64_ext_sve_addr_zz_lsl): Likewise.
854 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
855 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
856 * aarch64-dis-2.c: Regenerate.
858 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
860 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
861 AARCH64_OPND_SVE_PATTERN_SCALED.
862 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
863 * aarch64-opc.c (fields): Add a corresponding entry.
864 (set_multiplier_out_of_range_error): New function.
865 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
866 (operand_general_constraint_met_p): Handle
867 AARCH64_OPND_SVE_PATTERN_SCALED.
868 (print_register_offset_address): Use PRIi64 to print the
870 (aarch64_print_operand): Likewise. Handle
871 AARCH64_OPND_SVE_PATTERN_SCALED.
872 * aarch64-opc-2.c: Regenerate.
873 * aarch64-asm.h (ins_sve_scale): New inserter.
874 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
875 * aarch64-asm-2.c: Regenerate.
876 * aarch64-dis.h (ext_sve_scale): New inserter.
877 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
878 * aarch64-dis-2.c: Regenerate.
880 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
882 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
883 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
884 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
885 (FLD_SVE_prfop): Likewise.
886 * aarch64-opc.c: Include libiberty.h.
887 (aarch64_sve_pattern_array): New variable.
888 (aarch64_sve_prfop_array): Likewise.
889 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
890 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
891 AARCH64_OPND_SVE_PRFOP.
892 * aarch64-asm-2.c: Regenerate.
893 * aarch64-dis-2.c: Likewise.
894 * aarch64-opc-2.c: Likewise.
896 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
898 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
899 AARCH64_OPND_QLF_P_[ZM].
900 (aarch64_print_operand): Print /z and /m where appropriate.
902 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
904 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
905 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
906 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
907 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
908 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
909 * aarch64-opc.c (fields): Add corresponding entries here.
910 (operand_general_constraint_met_p): Check that SVE register lists
911 have the correct length. Check the ranges of SVE index registers.
912 Check for cases where p8-p15 are used in 3-bit predicate fields.
913 (aarch64_print_operand): Handle the new SVE operands.
914 * aarch64-opc-2.c: Regenerate.
915 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
916 * aarch64-asm.c (aarch64_ins_sve_index): New function.
917 (aarch64_ins_sve_reglist): Likewise.
918 * aarch64-asm-2.c: Regenerate.
919 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
920 * aarch64-dis.c (aarch64_ext_sve_index): New function.
921 (aarch64_ext_sve_reglist): Likewise.
922 * aarch64-dis-2.c: Regenerate.
924 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
926 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
927 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
928 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
929 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
932 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
934 * aarch64-opc.c (get_offset_int_reg_name): New function.
935 (print_immediate_offset_address): Likewise.
936 (print_register_offset_address): Take the base and offset
937 registers as parameters.
938 (aarch64_print_operand): Update caller accordingly. Use
939 print_immediate_offset_address.
941 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
943 * aarch64-opc.c (BANK): New macro.
944 (R32, R64): Take a register number as argument
947 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
949 * aarch64-opc.c (print_register_list): Add a prefix parameter.
950 (aarch64_print_operand): Update accordingly.
952 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
954 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
956 * aarch64-asm.h (ins_fpimm): New inserter.
957 * aarch64-asm.c (aarch64_ins_fpimm): New function.
958 * aarch64-asm-2.c: Regenerate.
959 * aarch64-dis.h (ext_fpimm): New extractor.
960 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
961 (aarch64_ext_fpimm): New function.
962 * aarch64-dis-2.c: Regenerate.
964 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
966 * aarch64-asm.c: Include libiberty.h.
967 (insert_fields): New function.
968 (aarch64_ins_imm): Use it.
969 * aarch64-dis.c (extract_fields): New function.
970 (aarch64_ext_imm): Use it.
972 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
974 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
975 with an esize parameter.
976 (operand_general_constraint_met_p): Update accordingly.
977 Fix misindented code.
978 * aarch64-asm.c (aarch64_ins_limm): Update call to
979 aarch64_logical_immediate_p.
981 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
983 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
985 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
987 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
989 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
991 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
993 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
995 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
996 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
997 xor3>: Delete mnemonics.
998 <cp_abort>: Rename mnemonic from ...
999 <cpabort>: ...to this.
1000 <setb>: Change to a X form instruction.
1001 <sync>: Change to 1 operand form.
1002 <copy>: Delete mnemonic.
1003 <copy_first>: Rename mnemonic from ...
1005 <paste, paste.>: Delete mnemonics.
1006 <paste_last>: Rename mnemonic from ...
1007 <paste.>: ...to this.
1009 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1011 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1013 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1015 * s390-mkopc.c (main): Support alternate arch strings.
1017 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1019 * s390-opc.txt: Fix kmctr instruction type.
1021 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1023 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1024 * i386-init.h: Regenerated.
1026 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1028 * opcodes/arc-dis.c (print_insn_arc): Changed.
1030 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1032 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1035 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1037 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1038 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1039 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1041 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1043 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1044 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1045 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1046 PREFIX_MOD_3_0FAE_REG_4.
1047 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1048 PREFIX_MOD_3_0FAE_REG_4.
1049 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1050 (cpu_flags): Add CpuPTWRITE.
1051 * i386-opc.h (CpuPTWRITE): New.
1052 (i386_cpu_flags): Add cpuptwrite.
1053 * i386-opc.tbl: Add ptwrite instruction.
1054 * i386-init.h: Regenerated.
1055 * i386-tbl.h: Likewise.
1057 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1059 * arc-dis.h: Wrap around in extern "C".
1061 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1063 * aarch64-tbl.h (V8_2_INSN): New macro.
1064 (aarch64_opcode_table): Use it.
1066 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1068 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1069 CORE_INSN, __FP_INSN and SIMD_INSN.
1071 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1073 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1074 (aarch64_opcode_table): Update uses accordingly.
1076 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1077 Kwok Cheung Yeung <kcy@codesourcery.com>
1080 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1081 'e_cmplwi' to 'e_cmpli' instead.
1082 (OPVUPRT, OPVUPRT_MASK): Define.
1083 (powerpc_opcodes): Add E200Z4 insns.
1084 (vle_opcodes): Add context save/restore insns.
1086 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1088 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1089 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1092 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1094 * arc-nps400-tbl.h: Change block comments to GNU format.
1095 * arc-dis.c: Add new globals addrtypenames,
1096 addrtypenames_max, and addtypeunknown.
1097 (get_addrtype): New function.
1098 (print_insn_arc): Print colons and address types when
1100 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1101 define insert and extract functions for all address types.
1102 (arc_operands): Add operands for colon and all address
1104 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1105 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1106 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1107 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1108 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1109 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1111 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1113 * configure: Regenerated.
1115 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1117 * arc-dis.c (skipclass): New structure.
1118 (decodelist): New variable.
1119 (is_compatible_p): New function.
1120 (new_element): Likewise.
1121 (skip_class_p): Likewise.
1122 (find_format_from_table): Use skip_class_p function.
1123 (find_format): Decode first the extension instructions.
1124 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1126 (parse_option): New function.
1127 (parse_disassembler_options): Likewise.
1128 (print_arc_disassembler_options): Likewise.
1129 (print_insn_arc): Use parse_disassembler_options function. Proper
1130 select ARCv2 cpu variant.
1131 * disassemble.c (disassembler_usage): Add ARC disassembler
1134 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1136 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1137 annotation from the "nal" entry and reorder it beyond "bltzal".
1139 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1141 * sparc-opc.c (ldtxa): New macro.
1142 (sparc_opcodes): Use the macro defined above to add entries for
1143 the LDTXA instructions.
1144 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1147 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1149 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1152 2016-07-01 Jan Beulich <jbeulich@suse.com>
1154 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1155 (movzb): Adjust to cover all permitted suffixes.
1157 * i386-tbl.h: Re-generate.
1159 2016-07-01 Jan Beulich <jbeulich@suse.com>
1161 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1162 (lgdt): Remove Tbyte from non-64-bit variant.
1163 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1164 xsaves64, xsavec64): Remove Disp16.
1165 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1166 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1168 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1169 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1170 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1172 * i386-tbl.h: Re-generate.
1174 2016-07-01 Jan Beulich <jbeulich@suse.com>
1176 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1177 * i386-tbl.h: Re-generate.
1179 2016-06-30 Yao Qi <yao.qi@linaro.org>
1181 * arm-dis.c (print_insn): Fix typo in comment.
1183 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1185 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1186 range of ldst_elemlist operands.
1187 (print_register_list): Use PRIi64 to print the index.
1188 (aarch64_print_operand): Likewise.
1190 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1192 * mcore-opc.h: Remove sentinal.
1193 * mcore-dis.c (print_insn_mcore): Adjust.
1195 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1197 * arc-opc.c: Correct description of availability of NPS400
1200 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1202 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1203 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1204 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1205 xor3>: New mnemonics.
1206 <setb>: Change to a VX form instruction.
1207 (insert_sh6): Add support for rldixor.
1208 (extract_sh6): Likewise.
1210 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1212 * arc-ext.h: Wrap in extern C.
1214 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1216 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1217 Use same method for determining instruction length on ARC700 and
1219 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1220 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1221 with the NPS400 subclass.
1222 * arc-opc.c: Likewise.
1224 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1226 * sparc-opc.c (rdasr): New macro.
1232 (sparc_opcodes): Use the macros above to fix and expand the
1233 definition of read/write instructions from/to
1234 asr/privileged/hyperprivileged instructions.
1235 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1236 %hva_mask_nz. Prefer softint_set and softint_clear over
1237 set_softint and clear_softint.
1238 (print_insn_sparc): Support %ver in Rd.
1240 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1242 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1243 architecture according to the hardware capabilities they require.
1245 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1247 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1248 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1249 bfd_mach_sparc_v9{c,d,e,v,m}.
1250 * sparc-opc.c (MASK_V9C): Define.
1251 (MASK_V9D): Likewise.
1252 (MASK_V9E): Likewise.
1253 (MASK_V9V): Likewise.
1254 (MASK_V9M): Likewise.
1255 (v6): Add MASK_V9{C,D,E,V,M}.
1256 (v6notlet): Likewise.
1260 (v9andleon): Likewise.
1268 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1270 2016-06-15 Nick Clifton <nickc@redhat.com>
1272 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1273 constants to match expected behaviour.
1274 (nds32_parse_opcode): Likewise. Also for whitespace.
1276 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1278 * arc-opc.c (extract_rhv1): Extract value from insn.
1280 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1282 * arc-nps400-tbl.h: Add ldbit instruction.
1283 * arc-opc.c: Add flag classes required for ldbit.
1285 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1287 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1288 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1289 support the above instructions.
1291 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1293 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1294 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1295 csma, cbba, zncv, and hofs.
1296 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1297 support the above instructions.
1299 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1301 * arc-nps400-tbl.h: Add andab and orab instructions.
1303 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1305 * arc-nps400-tbl.h: Add addl-like instructions.
1307 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1309 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1311 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1313 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1316 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1318 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1320 (init_disasm): Handle new command line option "insnlength".
1321 (print_s390_disassembler_options): Mention new option in help
1323 (print_insn_s390): Use the encoded insn length when dumping
1324 unknown instructions.
1326 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1328 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1329 to the address and set as symbol address for LDS/ STS immediate operands.
1331 2016-06-07 Alan Modra <amodra@gmail.com>
1333 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1334 cpu for "vle" to e500.
1335 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1336 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1337 (PPCNONE): Delete, substitute throughout.
1338 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1339 except for major opcode 4 and 31.
1340 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1342 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1344 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1345 ARM_EXT_RAS in relevant entries.
1347 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1350 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1353 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1356 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1357 (indir_v_mode): New.
1358 Add comments for '&'.
1359 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1360 (putop): Handle '&'.
1361 (intel_operand_size): Handle indir_v_mode.
1362 (OP_E_register): Likewise.
1363 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1364 64-bit indirect call/jmp for AMD64.
1365 * i386-tbl.h: Regenerated
1367 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1369 * arc-dis.c (struct arc_operand_iterator): New structure.
1370 (find_format_from_table): All the old content from find_format,
1371 with some minor adjustments, and parameter renaming.
1372 (find_format_long_instructions): New function.
1373 (find_format): Rewritten.
1374 (arc_insn_length): Add LSB parameter.
1375 (extract_operand_value): New function.
1376 (operand_iterator_next): New function.
1377 (print_insn_arc): Use new functions to find opcode, and iterator
1379 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1380 (extract_nps_3bit_dst_short): New function.
1381 (insert_nps_3bit_src2_short): New function.
1382 (extract_nps_3bit_src2_short): New function.
1383 (insert_nps_bitop1_size): New function.
1384 (extract_nps_bitop1_size): New function.
1385 (insert_nps_bitop2_size): New function.
1386 (extract_nps_bitop2_size): New function.
1387 (insert_nps_bitop_mod4_msb): New function.
1388 (extract_nps_bitop_mod4_msb): New function.
1389 (insert_nps_bitop_mod4_lsb): New function.
1390 (extract_nps_bitop_mod4_lsb): New function.
1391 (insert_nps_bitop_dst_pos3_pos4): New function.
1392 (extract_nps_bitop_dst_pos3_pos4): New function.
1393 (insert_nps_bitop_ins_ext): New function.
1394 (extract_nps_bitop_ins_ext): New function.
1395 (arc_operands): Add new operands.
1396 (arc_long_opcodes): New global array.
1397 (arc_num_long_opcodes): New global.
1398 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1400 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1402 * nds32-asm.h: Add extern "C".
1403 * sh-opc.h: Likewise.
1405 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1407 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1408 0,b,limm to the rflt instruction.
1410 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1412 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1415 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1418 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1419 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1420 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1421 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1422 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1423 * i386-init.h: Regenerated.
1425 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1428 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1429 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1430 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1431 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1432 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1433 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1434 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1435 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1436 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1437 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1438 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1439 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1440 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1441 CpuRegMask for AVX512.
1442 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1444 (set_bitfield_from_cpu_flag_init): New function.
1445 (set_bitfield): Remove const on f. Call
1446 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1447 * i386-opc.h (CpuRegMMX): New.
1448 (CpuRegXMM): Likewise.
1449 (CpuRegYMM): Likewise.
1450 (CpuRegZMM): Likewise.
1451 (CpuRegMask): Likewise.
1452 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1454 * i386-init.h: Regenerated.
1455 * i386-tbl.h: Likewise.
1457 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1460 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1461 (opcode_modifiers): Add AMD64 and Intel64.
1462 (main): Properly verify CpuMax.
1463 * i386-opc.h (CpuAMD64): Removed.
1464 (CpuIntel64): Likewise.
1465 (CpuMax): Set to CpuNo64.
1466 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1468 (Intel64): Likewise.
1469 (i386_opcode_modifier): Add amd64 and intel64.
1470 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1472 * i386-init.h: Regenerated.
1473 * i386-tbl.h: Likewise.
1475 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1478 * i386-gen.c (main): Fail if CpuMax is incorrect.
1479 * i386-opc.h (CpuMax): Set to CpuIntel64.
1480 * i386-tbl.h: Regenerated.
1482 2016-05-27 Nick Clifton <nickc@redhat.com>
1485 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1486 (msp430dis_opcode_unsigned): New function.
1487 (msp430dis_opcode_signed): New function.
1488 (msp430_singleoperand): Use the new opcode reading functions.
1489 Only disassenmble bytes if they were successfully read.
1490 (msp430_doubleoperand): Likewise.
1491 (msp430_branchinstr): Likewise.
1492 (msp430x_callx_instr): Likewise.
1493 (print_insn_msp430): Check that it is safe to read bytes before
1494 attempting disassembly. Use the new opcode reading functions.
1496 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1498 * ppc-opc.c (CY): New define. Document it.
1499 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1501 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1503 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1504 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1505 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1506 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1508 * i386-init.h: Regenerated.
1510 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1513 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1514 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1515 * i386-init.h: Regenerated.
1517 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1519 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1520 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1521 * i386-init.h: Regenerated.
1523 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1525 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1527 (print_insn_arc): Set insn_type information.
1528 * arc-opc.c (C_CC): Add F_CLASS_COND.
1529 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1530 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1531 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1532 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1533 (brne, brne_s, jeq_s, jne_s): Likewise.
1535 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1537 * arc-tbl.h (neg): New instruction variant.
1539 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1541 * arc-dis.c (find_format, find_format, get_auxreg)
1542 (print_insn_arc): Changed.
1543 * arc-ext.h (INSERT_XOP): Likewise.
1545 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1547 * tic54x-dis.c (sprint_mmr): Adjust.
1548 * tic54x-opc.c: Likewise.
1550 2016-05-19 Alan Modra <amodra@gmail.com>
1552 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1554 2016-05-19 Alan Modra <amodra@gmail.com>
1556 * ppc-opc.c: Formatting.
1557 (NSISIGNOPT): Define.
1558 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1560 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1562 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1563 replacing references to `micromips_ase' throughout.
1564 (_print_insn_mips): Don't use file-level microMIPS annotation to
1565 determine the disassembly mode with the symbol table.
1567 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1569 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1571 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1573 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1575 * mips-opc.c (D34): New macro.
1576 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1578 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1580 * i386-dis.c (prefix_table): Add RDPID instruction.
1581 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1582 (cpu_flags): Add RDPID bitfield.
1583 * i386-opc.h (enum): Add RDPID element.
1584 (i386_cpu_flags): Add RDPID field.
1585 * i386-opc.tbl: Add RDPID instruction.
1586 * i386-init.h: Regenerate.
1587 * i386-tbl.h: Regenerate.
1589 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1591 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1592 branch type of a symbol.
1593 (print_insn): Likewise.
1595 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1597 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1598 Mainline Security Extensions instructions.
1599 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1600 Extensions instructions.
1601 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1603 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1606 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1608 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1610 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1612 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1613 (arcExtMap_genOpcode): Likewise.
1614 * arc-opc.c (arg_32bit_rc): Define new variable.
1615 (arg_32bit_u6): Likewise.
1616 (arg_32bit_limm): Likewise.
1618 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1620 * aarch64-gen.c (VERIFIER): Define.
1621 * aarch64-opc.c (VERIFIER): Define.
1622 (verify_ldpsw): Use static linkage.
1623 * aarch64-opc.h (verify_ldpsw): Remove.
1624 * aarch64-tbl.h: Use VERIFIER for verifiers.
1626 2016-04-28 Nick Clifton <nickc@redhat.com>
1629 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1630 * aarch64-opc.c (verify_ldpsw): New function.
1631 * aarch64-opc.h (verify_ldpsw): New prototype.
1632 * aarch64-tbl.h: Add initialiser for verifier field.
1633 (LDPSW): Set verifier to verify_ldpsw.
1635 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1639 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1640 smaller than address size.
1642 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1644 * alpha-dis.c: Regenerate.
1645 * crx-dis.c: Likewise.
1646 * disassemble.c: Likewise.
1647 * epiphany-opc.c: Likewise.
1648 * fr30-opc.c: Likewise.
1649 * frv-opc.c: Likewise.
1650 * ip2k-opc.c: Likewise.
1651 * iq2000-opc.c: Likewise.
1652 * lm32-opc.c: Likewise.
1653 * lm32-opinst.c: Likewise.
1654 * m32c-opc.c: Likewise.
1655 * m32r-opc.c: Likewise.
1656 * m32r-opinst.c: Likewise.
1657 * mep-opc.c: Likewise.
1658 * mt-opc.c: Likewise.
1659 * or1k-opc.c: Likewise.
1660 * or1k-opinst.c: Likewise.
1661 * tic80-opc.c: Likewise.
1662 * xc16x-opc.c: Likewise.
1663 * xstormy16-opc.c: Likewise.
1665 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1667 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1668 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1669 calcsd, and calcxd instructions.
1670 * arc-opc.c (insert_nps_bitop_size): Delete.
1671 (extract_nps_bitop_size): Delete.
1672 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1673 (extract_nps_qcmp_m3): Define.
1674 (extract_nps_qcmp_m2): Define.
1675 (extract_nps_qcmp_m1): Define.
1676 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1677 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1678 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1679 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1680 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1683 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1685 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1687 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1689 * Makefile.in: Regenerated with automake 1.11.6.
1690 * aclocal.m4: Likewise.
1692 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1694 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1696 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1697 (extract_nps_cmem_uimm16): New function.
1698 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1700 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1702 * arc-dis.c (arc_insn_length): New function.
1703 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1704 (find_format): Change insnLen parameter to unsigned.
1706 2016-04-13 Nick Clifton <nickc@redhat.com>
1709 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1710 the LD.B and LD.BU instructions.
1712 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1714 * arc-dis.c (find_format): Check for extension flags.
1715 (print_flags): New function.
1716 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1718 * arc-ext.c (arcExtMap_coreRegName): Use
1719 LAST_EXTENSION_CORE_REGISTER.
1720 (arcExtMap_coreReadWrite): Likewise.
1721 (dump_ARC_extmap): Update printing.
1722 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1723 (arc_aux_regs): Add cpu field.
1724 * arc-regs.h: Add cpu field, lower case name aux registers.
1726 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1728 * arc-tbl.h: Add rtsc, sleep with no arguments.
1730 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1732 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1734 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1735 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1736 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1737 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1738 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1739 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1740 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1741 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1742 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1743 (arc_opcode arc_opcodes): Null terminate the array.
1744 (arc_num_opcodes): Remove.
1745 * arc-ext.h (INSERT_XOP): Define.
1746 (extInstruction_t): Likewise.
1747 (arcExtMap_instName): Delete.
1748 (arcExtMap_insn): New function.
1749 (arcExtMap_genOpcode): Likewise.
1750 * arc-ext.c (ExtInstruction): Remove.
1751 (create_map): Zero initialize instruction fields.
1752 (arcExtMap_instName): Remove.
1753 (arcExtMap_insn): New function.
1754 (dump_ARC_extmap): More info while debuging.
1755 (arcExtMap_genOpcode): New function.
1756 * arc-dis.c (find_format): New function.
1757 (print_insn_arc): Use find_format.
1758 (arc_get_disassembler): Enable dump_ARC_extmap only when
1761 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1763 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1764 instruction bits out.
1766 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1768 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1769 * arc-opc.c (arc_flag_operands): Add new flags.
1770 (arc_flag_classes): Add new classes.
1772 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1774 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1776 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1778 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1779 encode1, rflt, crc16, and crc32 instructions.
1780 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1781 (arc_flag_classes): Add C_NPS_R.
1782 (insert_nps_bitop_size_2b): New function.
1783 (extract_nps_bitop_size_2b): Likewise.
1784 (insert_nps_bitop_uimm8): Likewise.
1785 (extract_nps_bitop_uimm8): Likewise.
1786 (arc_operands): Add new operand entries.
1788 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1790 * arc-regs.h: Add a new subclass field. Add double assist
1791 accumulator register values.
1792 * arc-tbl.h: Use DPA subclass to mark the double assist
1793 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1794 * arc-opc.c (RSP): Define instead of SP.
1795 (arc_aux_regs): Add the subclass field.
1797 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1799 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1801 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1803 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1806 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1808 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1809 issues. No functional changes.
1811 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1813 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1814 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1815 (RTT): Remove duplicate.
1816 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1817 (PCT_CONFIG*): Remove.
1818 (D1L, D1H, D2H, D2L): Define.
1820 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1822 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1824 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1826 * arc-tbl.h (invld07): Remove.
1827 * arc-ext-tbl.h: New file.
1828 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1829 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1831 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1833 Fix -Wstack-usage warnings.
1834 * aarch64-dis.c (print_operands): Substitute size.
1835 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1837 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1839 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1840 to get a proper diagnostic when an invalid ASR register is used.
1842 2016-03-22 Nick Clifton <nickc@redhat.com>
1844 * configure: Regenerate.
1846 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1848 * arc-nps400-tbl.h: New file.
1849 * arc-opc.c: Add top level comment.
1850 (insert_nps_3bit_dst): New function.
1851 (extract_nps_3bit_dst): New function.
1852 (insert_nps_3bit_src2): New function.
1853 (extract_nps_3bit_src2): New function.
1854 (insert_nps_bitop_size): New function.
1855 (extract_nps_bitop_size): New function.
1856 (arc_flag_operands): Add nps400 entries.
1857 (arc_flag_classes): Add nps400 entries.
1858 (arc_operands): Add nps400 entries.
1859 (arc_opcodes): Add nps400 include.
1861 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1863 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1864 the new class enum values.
1866 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1868 * arc-dis.c (print_insn_arc): Handle nps400.
1870 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1872 * arc-opc.c (BASE): Delete.
1874 2016-03-18 Nick Clifton <nickc@redhat.com>
1877 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1878 of MOV insn that aliases an ORR insn.
1880 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1882 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1884 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1886 * mcore-opc.h: Add const qualifiers.
1887 * microblaze-opc.h (struct op_code_struct): Likewise.
1888 * sh-opc.h: Likewise.
1889 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1890 (tic4x_print_op): Likewise.
1892 2016-03-02 Alan Modra <amodra@gmail.com>
1894 * or1k-desc.h: Regenerate.
1895 * fr30-ibld.c: Regenerate.
1896 * rl78-decode.c: Regenerate.
1898 2016-03-01 Nick Clifton <nickc@redhat.com>
1901 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1903 2016-02-24 Renlin Li <renlin.li@arm.com>
1905 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1906 (print_insn_coprocessor): Support fp16 instructions.
1908 2016-02-24 Renlin Li <renlin.li@arm.com>
1910 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1911 vminnm, vrint(mpna).
1913 2016-02-24 Renlin Li <renlin.li@arm.com>
1915 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1916 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1918 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1920 * i386-dis.c (print_insn): Parenthesize expression to prevent
1921 truncated addresses.
1924 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1925 Janek van Oirschot <jvanoirs@synopsys.com>
1927 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1930 2016-02-04 Nick Clifton <nickc@redhat.com>
1933 * msp430-dis.c (print_insn_msp430): Add a special case for
1934 decoding an RRC instruction with the ZC bit set in the extension
1937 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1939 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1940 * epiphany-ibld.c: Regenerate.
1941 * fr30-ibld.c: Regenerate.
1942 * frv-ibld.c: Regenerate.
1943 * ip2k-ibld.c: Regenerate.
1944 * iq2000-ibld.c: Regenerate.
1945 * lm32-ibld.c: Regenerate.
1946 * m32c-ibld.c: Regenerate.
1947 * m32r-ibld.c: Regenerate.
1948 * mep-ibld.c: Regenerate.
1949 * mt-ibld.c: Regenerate.
1950 * or1k-ibld.c: Regenerate.
1951 * xc16x-ibld.c: Regenerate.
1952 * xstormy16-ibld.c: Regenerate.
1954 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1956 * epiphany-dis.c: Regenerated from latest cpu files.
1958 2016-02-01 Michael McConville <mmcco@mykolab.com>
1960 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1963 2016-01-25 Renlin Li <renlin.li@arm.com>
1965 * arm-dis.c (mapping_symbol_for_insn): New function.
1966 (find_ifthen_state): Call mapping_symbol_for_insn().
1968 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1970 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1971 of MSR UAO immediate operand.
1973 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1975 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1976 instruction support.
1978 2016-01-17 Alan Modra <amodra@gmail.com>
1980 * configure: Regenerate.
1982 2016-01-14 Nick Clifton <nickc@redhat.com>
1984 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1985 instructions that can support stack pointer operations.
1986 * rl78-decode.c: Regenerate.
1987 * rl78-dis.c: Fix display of stack pointer in MOVW based
1990 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1992 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1993 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1994 erxtatus_el1 and erxaddr_el1.
1996 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1998 * arm-dis.c (arm_opcodes): Add "esb".
1999 (thumb_opcodes): Likewise.
2001 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2003 * ppc-opc.c <xscmpnedp>: Delete.
2004 <xvcmpnedp>: Likewise.
2005 <xvcmpnedp.>: Likewise.
2006 <xvcmpnesp>: Likewise.
2007 <xvcmpnesp.>: Likewise.
2009 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2012 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2015 2016-01-01 Alan Modra <amodra@gmail.com>
2017 Update year range in copyright notice of all files.
2019 For older changes see ChangeLog-2015
2021 Copyright (C) 2016 Free Software Foundation, Inc.
2023 Copying and distribution of this file, with or without modification,
2024 are permitted in any medium without royalty provided the copyright
2025 notice and this notice are preserved.
2031 version-control: never