opcodes/ChangeLog

   1 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
   2
   3         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
   4         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
   5         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
   6         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
   7         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
   8         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
   9         (WR_s): Update macro.
  10         (micromips_opcodes): Update register use flags of: "addiu",
  11         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
  12         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
  13         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
  14         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
  15         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
  16         "swm" and "xor" instructions.
  17
  18 2011-08-05  David S. Miller  <davem@davemloft.net>
  19
  20         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
  21         (X_RS3): New macro.
  22         (print_insn_sparc): Handle '4', '5', and '(' format codes.
  23         Accept %asr numbers below 28.
  24         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
  25         instructions.
  26
  27 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
  28
  29         * i386-dis.c (xop_table): Remove spurious bextr insn.
  30
  31 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
  32
  33         PR ld/13048
  34         * i386-dis.c (print_insn): Optimize info->mach check.
  35
  36 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
  37
  38         PR gas/13046
  39         * i386-opc.tbl: Add Disp32S to 64bit call.
  40         * i386-tbl.h: Regenerated.
  41
  42 2011-07-24  Chao-ying Fu  <fu@mips.com>
  43             Maciej W. Rozycki  <macro@codesourcery.com>
  44
  45         * micromips-opc.c: New file.
  46         * mips-dis.c (micromips_to_32_reg_b_map): New array.
  47         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
  48         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
  49         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
  50         (micromips_to_32_reg_q_map): Likewise.
  51         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
  52         (micromips_ase): New variable.
  53         (is_micromips): New function.
  54         (set_default_mips_dis_options): Handle microMIPS ASE.
  55         (print_insn_micromips): New function.
  56         (is_compressed_mode_p): Likewise.
  57         (_print_insn_mips): Handle microMIPS instructions.
  58         * Makefile.am (CFILES): Add micromips-opc.c.
  59         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
  60         * Makefile.in: Regenerate.
  61         * configure: Regenerate.
  62
  63         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
  64         (micromips_to_32_reg_i_map): Likewise.
  65         (micromips_to_32_reg_m_map): Likewise.
  66         (micromips_to_32_reg_n_map): New macro.
  67
  68 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
  69
  70         * mips-opc.c (NODS): New macro.
  71         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
  72         (DSP_VOLA): Likewise.
  73         (mips_builtin_opcodes): Add NODS annotation to "deret" and
  74         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
  75         place of TRAP for "wait", "waiti" and "yield".
  76         * mips16-opc.c (NODS): New macro.
  77         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
  78         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
  79         "restore" and "save".
  80
  81 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * configure.in: Handle bfd_k1om_arch.
  84         * configure: Regenerated.
  85
  86         * disassemble.c (disassembler): Handle bfd_k1om_arch.
  87
  88         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
  89         bfd_mach_k1om_intel_syntax.
  90
  91         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
  92         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
  93         (cpu_flags): Add CpuK1OM.
  94
  95         * i386-opc.h (CpuK1OM): New.
  96         (i386_cpu_flags): Add cpuk1om.
  97
  98         * i386-init.h: Regenerated.
  99         * i386-tbl.h: Likewise.
 100
 101 2011-07-12  Nick Clifton  <nickc@redhat.com>
 102
 103         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 104         accidental change.
 105
 106 2011-07-01  Nick Clifton  <nickc@redhat.com>
 107
 108         PR binutils/12329
 109         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 110         insns using post-increment addressing.
 111
 112 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * i386-dis.c (vex_len_table): Update rorxS.
 115
 116 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 117
 118         AVX Programming Reference (June, 2011)
 119         * i386-dis.c (vex_len_table): Correct rorxS.
 120
 121         * i386-opc.tbl: Correct rorx.
 122         * i386-tbl.h: Regenerated.
 123
 124 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 127         * tilepro-opc.c (find_opcode): Likewise.
 128
 129 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 130
 131         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 132
 133 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 136         PREFIX_VEX_0F388E.
 137
 138 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 139
 140         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 141         (MOSTLYCLEANFILES): ... here.
 142         * Makefile.in: Regenerate.
 143
 144 2011-06-14  Alan Modra  <amodra@gmail.com>
 145
 146         * Makefile.in: Regenerate.
 147
 148 2011-06-13  Walter Lee  <walt@tilera.com>
 149
 150         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 151         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 152         * Makefile.in: Regenerate.
 153         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 154         * configure: Regenerate.
 155         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 156         * po/POTFILES.in: Regenerate.
 157         * tilegx-dis.c: New file.
 158         * tilegx-opc.c: New file.
 159         * tilepro-dis.c: New file.
 160         * tilepro-opc.c: New file.
 161
 162 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         AVX Programming Reference (June, 2011)
 165         * i386-dis.c (XMGatherQ): New.
 166         * i386-dis.c (EXxmm_mb): New.
 167         (EXxmm_mb): Likewise.
 168         (EXxmm_mw): Likewise.
 169         (EXxmm_md): Likewise.
 170         (EXxmm_mq): Likewise.
 171         (EXxmmdw): Likewise.
 172         (EXxmmqd): Likewise.
 173         (VexGatherQ): Likewise.
 174         (MVexVSIBDWpX): Likewise.
 175         (MVexVSIBQWpX): Likewise.
 176         (xmm_mb_mode): Likewise.
 177         (xmm_mw_mode): Likewise.
 178         (xmm_md_mode): Likewise.
 179         (xmm_mq_mode): Likewise.
 180         (xmmdw_mode): Likewise.
 181         (xmmqd_mode): Likewise.
 182         (ymmxmm_mode): Likewise.
 183         (vex_vsib_d_w_dq_mode): Likewise.
 184         (vex_vsib_q_w_dq_mode): Likewise.
 185         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 186         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 187         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 188         (PREFIX_0F3882): Likewise.
 189         (PREFIX_VEX_0F3816): Likewise.
 190         (PREFIX_VEX_0F3836): Likewise.
 191         (PREFIX_VEX_0F3845): Likewise.
 192         (PREFIX_VEX_0F3846): Likewise.
 193         (PREFIX_VEX_0F3847): Likewise.
 194         (PREFIX_VEX_0F3858): Likewise.
 195         (PREFIX_VEX_0F3859): Likewise.
 196         (PREFIX_VEX_0F385A): Likewise.
 197         (PREFIX_VEX_0F3878): Likewise.
 198         (PREFIX_VEX_0F3879): Likewise.
 199         (PREFIX_VEX_0F388C): Likewise.
 200         (PREFIX_VEX_0F388E): Likewise.
 201         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 202         (PREFIX_VEX_0F38F5): Likewise.
 203         (PREFIX_VEX_0F38F6): Likewise.
 204         (PREFIX_VEX_0F3A00): Likewise.
 205         (PREFIX_VEX_0F3A01): Likewise.
 206         (PREFIX_VEX_0F3A02): Likewise.
 207         (PREFIX_VEX_0F3A38): Likewise.
 208         (PREFIX_VEX_0F3A39): Likewise.
 209         (PREFIX_VEX_0F3A46): Likewise.
 210         (PREFIX_VEX_0F3AF0): Likewise.
 211         (VEX_LEN_0F3816_P_2): Likewise.
 212         (VEX_LEN_0F3819_P_2): Likewise.
 213         (VEX_LEN_0F3836_P_2): Likewise.
 214         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 215         (VEX_LEN_0F38F5_P_0): Likewise.
 216         (VEX_LEN_0F38F5_P_1): Likewise.
 217         (VEX_LEN_0F38F5_P_3): Likewise.
 218         (VEX_LEN_0F38F6_P_3): Likewise.
 219         (VEX_LEN_0F38F7_P_1): Likewise.
 220         (VEX_LEN_0F38F7_P_2): Likewise.
 221         (VEX_LEN_0F38F7_P_3): Likewise.
 222         (VEX_LEN_0F3A00_P_2): Likewise.
 223         (VEX_LEN_0F3A01_P_2): Likewise.
 224         (VEX_LEN_0F3A38_P_2): Likewise.
 225         (VEX_LEN_0F3A39_P_2): Likewise.
 226         (VEX_LEN_0F3A46_P_2): Likewise.
 227         (VEX_LEN_0F3AF0_P_3): Likewise.
 228         (VEX_W_0F3816_P_2): Likewise.
 229         (VEX_W_0F3818_P_2): Likewise.
 230         (VEX_W_0F3819_P_2): Likewise.
 231         (VEX_W_0F3836_P_2): Likewise.
 232         (VEX_W_0F3846_P_2): Likewise.
 233         (VEX_W_0F3858_P_2): Likewise.
 234         (VEX_W_0F3859_P_2): Likewise.
 235         (VEX_W_0F385A_P_2_M_0): Likewise.
 236         (VEX_W_0F3878_P_2): Likewise.
 237         (VEX_W_0F3879_P_2): Likewise.
 238         (VEX_W_0F3A00_P_2): Likewise.
 239         (VEX_W_0F3A01_P_2): Likewise.
 240         (VEX_W_0F3A02_P_2): Likewise.
 241         (VEX_W_0F3A38_P_2): Likewise.
 242         (VEX_W_0F3A39_P_2): Likewise.
 243         (VEX_W_0F3A46_P_2): Likewise.
 244         (MOD_VEX_0F3818_PREFIX_2): Removed.
 245         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 246         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 247         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 248         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 249         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 250         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 251         (VEX_LEN_0F3A0E_P_2): Likewise.
 252         (VEX_LEN_0F3A0F_P_2): Likewise.
 253         (VEX_LEN_0F3A42_P_2): Likewise.
 254         (VEX_LEN_0F3A4C_P_2): Likewise.
 255         (VEX_W_0F3818_P_2_M_0): Likewise.
 256         (VEX_W_0F3819_P_2_M_0): Likewise.
 257         (prefix_table): Updated.
 258         (three_byte_table): Likewise.
 259         (vex_table): Likewise.
 260         (vex_len_table): Likewise.
 261         (vex_w_table): Likewise.
 262         (mod_table): Likewise.
 263         (putop): Handle "LW".
 264         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 265         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 266         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 267         (OP_EX): Likewise.
 268         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 269         vex_vsib_q_w_dq_mode.
 270         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 271         (OP_VEX): Likewise.
 272
 273         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 274         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 275         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 276         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 277         (opcode_modifiers): Add VecSIB.
 278
 279         * i386-opc.h (CpuAVX2): New.
 280         (CpuBMI2): Likewise.
 281         (CpuLZCNT): Likewise.
 282         (CpuINVPCID): Likewise.
 283         (VecSIB128): Likewise.
 284         (VecSIB256): Likewise.
 285         (VecSIB): Likewise.
 286         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 287         (i386_opcode_modifier): Add vecsib.
 288
 289         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 290         * i386-init.h: Regenerated.
 291         * i386-tbl.h: Likewise.
 292
 293 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 294
 295         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 296         * i386-init.h: Regenerated.
 297
 298 2011-06-03  Nick Clifton  <nickc@redhat.com>
 299
 300         PR binutils/12752
 301         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 302         computing address offsets.
 303         (print_arm_address): Likewise.
 304         (print_insn_arm): Likewise.
 305         (print_insn_thumb16): Likewise.
 306         (print_insn_thumb32): Likewise.
 307
 308 2011-06-02  Jie Zhang <jie@codesourcery.com>
 309             Nathan Sidwell <nathan@codesourcery.com>
 310             Maciej Rozycki <macro@codesourcery.com>
 311
 312         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 313         as address offset.
 314         (print_arm_address): Likewise. Elide positive #0 appropriately.
 315         (print_insn_arm): Likewise.
 316
 317 2011-06-02  Nick Clifton  <nickc@redhat.com>
 318
 319         PR gas/12752
 320         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 321         passed to print_address_func.
 322
 323 2011-06-02  Nick Clifton  <nickc@redhat.com>
 324
 325         * arm-dis.c: Fix spelling mistakes.
 326         * op/opcodes.pot: Regenerate.
 327
 328 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 329
 330         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 331         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 332         * s390-opc.txt: Fix cxr instruction type.
 333
 334 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 335
 336         * s390-opc.c: Add new instruction types marking register pair
 337         operands.
 338         * s390-opc.txt: Match instructions having register pair operands
 339         to the new instruction types.
 340
 341 2011-05-19  Nick Clifton  <nickc@redhat.com>
 342
 343         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 344         operands.
 345
 346 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 347
 348         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 349         * i386-init.h: Regenerated.
 350
 351 2011-04-27  Nick Clifton  <nickc@redhat.com>
 352
 353         * po/da.po: Updated Danish translation.
 354
 355 2011-04-26  Anton Blanchard  <anton@samba.org>
 356
 357         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 358
 359 2011-04-21  DJ Delorie  <dj@redhat.com>
 360
 361         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 362         * rx-decode.c: Regenerate.
 363
 364 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 365
 366         * i386-init.h: Regenerated.
 367
 368 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 369
 370         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 371         from bdver1 flags.
 372
 373 2011-04-13  Nick Clifton  <nickc@redhat.com>
 374
 375         * v850-dis.c (disassemble): Always print a closing square brace if
 376         an opening square brace was printed.
 377
 378 2011-04-12  Nick Clifton  <nickc@redhat.com>
 379
 380         PR binutils/12534
 381         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 382         patterns.
 383         (print_insn_thumb32): Handle %L.
 384
 385 2011-04-11  Julian Brown  <julian@codesourcery.com>
 386
 387         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 388         (print_insn_thumb32): Add APSR bitmask support.
 389
 390 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 391
 392         * arm-dis.c (print_insn): init vars moved into private_data structure.
 393
 394 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 395
 396         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 397
 398 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 399
 400         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 401         post-increment to support LPM Z+ instruction. Add support for 'E'
 402         constraint for DES instruction.
 403         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 404
 405 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 406
 407         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 408
 409 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 410
 411         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 412         Use branch types instead.
 413         (print_insn): Likewise.
 414
 415 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 416
 417         * mips-opc.c (mips_builtin_opcodes): Correct register use
 418         annotation of "alnv.ps".
 419
 420 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 421
 422         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 423
 424 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 425
 426         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 427
 428 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 429
 430         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 431
 432 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 433
 434         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 435         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 436         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 437         exception, end_of_registers, msize, memory, bfd_mach.
 438         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 439         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 440         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 441         (get_allreg): Change to new defines.  Fallback to abort().
 442
 443 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * bfin-dis.c: Add whitespace/parenthesis where needed.
 446
 447 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 448
 449         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 450         than 7.
 451
 452 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 453
 454         * configure: Regenerate.
 455
 456 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 457
 458         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 459
 460 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 461
 462         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 463         dregs only when P is set, and dregs_lo otherwise.
 464
 465 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 466
 467         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 468
 469 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 470
 471         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 472
 473 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 474
 475         * bfin-dis.c (machine_registers): Delete REG_GP.
 476         (reg_names): Delete "GP".
 477         (decode_allregs): Change REG_GP to REG_LASTREG.
 478
 479 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 480
 481         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 482         M_IH, M_IU): Delete.
 483
 484 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 485
 486         * bfin-dis.c (reg_names): Add const.
 487         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 488         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 489         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 490         decode_counters, decode_allregs): Likewise.
 491
 492 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 493
 494         * i386-dis.c (OP_J): Parenthesize expression to prevent
 495         truncated addresses.
 496         (print_insn): Fix indentation off-by-one.
 497
 498 2011-02-01  Nick Clifton  <nickc@redhat.com>
 499
 500         * po/da.po: Updated Danish translation.
 501
 502 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 503
 504         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 505
 506 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 507
 508         * i386-dis.c (sIbT): New.
 509         (b_T_mode): Likewise.
 510         (dis386): Replace sIb with sIbT on "pushT".
 511         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 512         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 513
 514 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 515
 516         * i386-init.h: Regenerated.
 517         * i386-tbl.h: Regenerated
 518
 519 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 520
 521         * i386-dis.c (REG_XOP_TBM_01): New.
 522         (REG_XOP_TBM_02): New.
 523         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 524         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 525         entries, and add bextr instruction.
 526
 527         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 528         (cpu_flags): Add CpuTBM.
 529
 530         * i386-opc.h (CpuTBM) New.
 531         (i386_cpu_flags): Add bit cputbm.
 532
 533         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 534         blcs, blsfill, blsic, t1mskc, and tzmsk.
 535
 536 2011-01-12  DJ Delorie  <dj@redhat.com>
 537
 538         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 539
 540 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 541
 542         * mips-dis.c (print_insn_args): Adjust the value to print the real
 543         offset for "+c" argument.
 544
 545 2011-01-10  Nick Clifton  <nickc@redhat.com>
 546
 547         * po/da.po: Updated Danish translation.
 548
 549 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 550
 551         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 552
 553 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         * i386-dis.c (REG_VEX_38F3): New.
 556         (PREFIX_0FBC): Likewise.
 557         (PREFIX_VEX_38F2): Likewise.
 558         (PREFIX_VEX_38F3_REG_1): Likewise.
 559         (PREFIX_VEX_38F3_REG_2): Likewise.
 560         (PREFIX_VEX_38F3_REG_3): Likewise.
 561         (PREFIX_VEX_38F7): Likewise.
 562         (VEX_LEN_38F2_P_0): Likewise.
 563         (VEX_LEN_38F3_R_1_P_0): Likewise.
 564         (VEX_LEN_38F3_R_2_P_0): Likewise.
 565         (VEX_LEN_38F3_R_3_P_0): Likewise.
 566         (VEX_LEN_38F7_P_0): Likewise.
 567         (dis386_twobyte): Use PREFIX_0FBC.
 568         (reg_table): Add REG_VEX_38F3.
 569         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 570         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 571         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 572         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 573         PREFIX_VEX_38F7.
 574         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 575         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 576         VEX_LEN_38F7_P_0.
 577
 578         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 579         (cpu_flags): Add CpuBMI.
 580
 581         * i386-opc.h (CpuBMI): New.
 582         (i386_cpu_flags): Add cpubmi.
 583
 584         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 585         * i386-init.h: Regenerated.
 586         * i386-tbl.h: Likewise.
 587
 588 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         * i386-dis.c (VexGdq): New.
 591         (OP_VEX): Handle dq_mode.
 592
 593 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * i386-gen.c (process_copyright): Update copyright to 2011.
 596
 597 For older changes see ChangeLog-2010
 598 \f
 599 Local Variables:
 600 mode: change-log
 601 left-margin: 8
 602 fill-column: 74
 603 version-control: never
 604 End: