opcodes/ChangeLog

   1 2019-12-05  Jan Beulich  <jbeulich@suse.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_crypto,
   4         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
   5         CRYPTO_V8_2_INSN): Delete.
   6
   7 2019-12-05  Alan Modra  <amodra@gmail.com>
   8
   9         PR 25249
  10         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
  11         (struct string_buf): New.
  12         (strbuf): New function.
  13         (get_field): Use strbuf rather than strdup of local temp.
  14         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
  15         (get_field_rfsl, get_field_imm15): Likewise.
  16         (get_field_rd, get_field_r1, get_field_r2): Update macros.
  17         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
  18         (print_insn_microblaze): Formatting.  Init and pass string_buf to
  19         get_field functions.
  20
  21 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
  24         * i386-tbl.h: Re-generate.
  25
  26 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
  29
  30 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
  33         forms.
  34         (xbegin): Drop DefaultSize.
  35         * i386-tbl.h: Re-generate.
  36
  37 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
  38
  39         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
  40         Change the coproc CRC conditions to use the extension
  41         feature set, second word, base on ARM_EXT2_CRC.
  42
  43 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
  46         * i386-tbl.h: Re-generate.
  47
  48 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
  51         JumpInterSegment, and JumpAbsolute entries.
  52         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
  53         JUMP_ABSOLUTE): Define.
  54         (struct i386_opcode_modifier): Extend jump field to 3 bits.
  55         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
  56         fields.
  57         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
  58         JumpInterSegment): Define.
  59         * i386-tbl.h: Re-generate.
  60
  61 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-gen.c (operand_type_init): Remove
  64         OPERAND_TYPE_JUMPABSOLUTE entry.
  65         (opcode_modifiers): Add JumpAbsolute entry.
  66         (operand_types): Remove JumpAbsolute entry.
  67         * i386-opc.h (JumpAbsolute): Move between enums.
  68         (struct i386_opcode_modifier): Add jumpabsolute field.
  69         (union i386_operand_type): Remove jumpabsolute field.
  70         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
  71         * i386-init.h, i386-tbl.h: Re-generate.
  72
  73 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-gen.c (opcode_modifiers): Add AnySize entry.
  76         (operand_types): Remove AnySize entry.
  77         * i386-opc.h (AnySize): Move between enums.
  78         (struct i386_opcode_modifier): Add anysize field.
  79         (OTUnused): Un-comment.
  80         (union i386_operand_type): Remove anysize field.
  81         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
  82         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
  83         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
  84         AnySize.
  85         * i386-tbl.h: Re-generate.
  86
  87 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
  88
  89         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
  90         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
  91         use the floating point register (FPR).
  92
  93 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
  94
  95         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
  96         cmode 1101.
  97         (is_mve_encoding_conflict): Update cmode conflict checks for
  98         MVE_VMVN_IMM.
  99
 100 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 103         entry.
 104         (operand_types): Remove EsSeg entry.
 105         (main): Replace stale use of OTMax.
 106         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 107         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 108         (EsSeg): Delete.
 109         (OTUnused): Comment out.
 110         (union i386_operand_type): Remove esseg field.
 111         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 112         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 113         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 114         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 115         * i386-init.h, i386-tbl.h: Re-generate.
 116
 117 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-gen.c (operand_instances): Add RegB entry.
 120         * i386-opc.h (enum operand_instance): Add RegB.
 121         * i386-opc.tbl (RegC, RegD, RegB): Define.
 122         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 123         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 124         monitorx, mwaitx): Drop ImmExt and convert encodings
 125         accordingly.
 126         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 127         (edx, rdx): Add Instance=RegD.
 128         (ebx, rbx): Add Instance=RegB.
 129         * i386-tbl.h: Re-generate.
 130
 131 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-gen.c (operand_type_init): Adjust
 134         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 135         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 136         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 137         (operand_instances): New.
 138         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 139         (output_operand_type): New parameter "instance". Process it.
 140         (process_i386_operand_type): New local variable "instance".
 141         (main): Adjust static assertions.
 142         * i386-opc.h (INSTANCE_WIDTH): Define.
 143         (enum operand_instance): New.
 144         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 145         (union i386_operand_type): Replace acc, inoutportreg, and
 146         shiftcount by instance.
 147         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 148         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 149         Add Instance=.
 150         * i386-init.h, i386-tbl.h: Re-generate.
 151
 152 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 153
 154         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 155         smaxp/sminp entries' "tied_operand" field to 2.
 156
 157 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 158
 159         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 160         "index" local variable by that of the already existing "num".
 161
 162 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         PR gas/25167
 165         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 166         * i386-tbl.h: Regenerated.
 167
 168 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-gen.c (operand_type_init): Add Class= to
 171         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 172         OPERAND_TYPE_REGBND entry.
 173         (operand_classes): Add RegMask and RegBND entries.
 174         (operand_types): Drop RegMask and RegBND entry.
 175         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 176         (RegMask, RegBND): Delete.
 177         (union i386_operand_type): Remove regmask and regbnd fields.
 178         * i386-opc.tbl (RegMask, RegBND): Define.
 179         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 180         Class=RegBND.
 181         * i386-init.h, i386-tbl.h: Re-generate.
 182
 183 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-gen.c (operand_type_init): Add Class= to
 186         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 187         OPERAND_TYPE_REGZMM entries.
 188         (operand_classes): Add RegMMX and RegSIMD entries.
 189         (operand_types): Drop RegMMX and RegSIMD entries.
 190         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 191         (RegMMX, RegSIMD): Delete.
 192         (union i386_operand_type): Remove regmmx and regsimd fields.
 193         * i386-opc.tbl (RegMMX): Define.
 194         (RegXMM, RegYMM, RegZMM): Add Class=.
 195         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 196         Class=RegSIMD.
 197         * i386-init.h, i386-tbl.h: Re-generate.
 198
 199 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-gen.c (operand_type_init): Add Class= to
 202         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 203         entries.
 204         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 205         (operand_types): Drop Control, Debug, and Test entries.
 206         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 207         (Control, Debug, Test): Delete.
 208         (union i386_operand_type): Remove control, debug, and test
 209         fields.
 210         * i386-opc.tbl (Control, Debug, Test): Define.
 211         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 212         Class=RegDR, and Test by Class=RegTR.
 213         * i386-init.h, i386-tbl.h: Re-generate.
 214
 215 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-gen.c (operand_type_init): Add Class= to
 218         OPERAND_TYPE_SREG entry.
 219         (operand_classes): Add SReg entry.
 220         (operand_types): Drop SReg entry.
 221         * i386-opc.h (enum operand_class): Add SReg.
 222         (SReg): Delete.
 223         (union i386_operand_type): Remove sreg field.
 224         * i386-opc.tbl (SReg): Define.
 225         * i386-reg.tbl: Replace SReg by Class=SReg.
 226         * i386-init.h, i386-tbl.h: Re-generate.
 227
 228 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 229
 230         * i386-gen.c (operand_type_init): Add Class=. New
 231         OPERAND_TYPE_ANYIMM entry.
 232         (operand_classes): New.
 233         (operand_types): Drop Reg entry.
 234         (output_operand_type): New parameter "class". Process it.
 235         (process_i386_operand_type): New local variable "class".
 236         (main): Adjust static assertions.
 237         * i386-opc.h (CLASS_WIDTH): Define.
 238         (enum operand_class): New.
 239         (Reg): Replace by Class. Adjust comment.
 240         (union i386_operand_type): Replace reg by class.
 241         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 242         Class=.
 243         * i386-reg.tbl: Replace Reg by Class=Reg.
 244         * i386-init.h: Re-generate.
 245
 246 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 247
 248         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 249         (aarch64_opcode_table): Add data gathering hint mnemonic.
 250         * opcodes/aarch64-dis-2.c: Account for new instruction.
 251
 252 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 253
 254         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 255
 256
 257 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 258
 259         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 260         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 261         aarch64_feature_f64mm): New feature sets.
 262         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 263         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 264         instructions.
 265         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 266         macros.
 267         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 268         (OP_SVE_QQQ): New qualifier.
 269         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 270         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 271         the movprfx constraint.
 272         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 273         (aarch64_opcode_table): Define new instructions smmla,
 274         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 275         uzip{1/2}, trn{1/2}.
 276         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 277         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 278         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 279         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 280         Account for new instructions.
 281         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 282         S4x32 operand.
 283         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 284
 285 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 286 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 287
 288         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 289         Armv8.6-A.
 290         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 291         (neon_opcodes): Add bfloat SIMD instructions.
 292         (print_insn_coprocessor): Add new control character %b to print
 293         condition code without checking cp_num.
 294         (print_insn_neon): Account for BFloat16 instructions that have no
 295         special top-byte handling.
 296
 297 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 298 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 299
 300         * arm-dis.c (print_insn_coprocessor,
 301         print_insn_generic_coprocessor): Create wrapper functions around
 302         the implementation of the print_insn_coprocessor control codes.
 303         (print_insn_coprocessor_1): Original print_insn_coprocessor
 304         function that now takes which array to look at as an argument.
 305         (print_insn_arm): Use both print_insn_coprocessor and
 306         print_insn_generic_coprocessor.
 307         (print_insn_thumb32): As above.
 308
 309 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 310 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 311
 312         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 313         in reglane special case.
 314         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 315         aarch64_find_next_opcode): Account for new instructions.
 316         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 317         in reglane special case.
 318         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 319         new AARCH64_OPND_QLF_S_2H qualifier.
 320         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 321         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 322         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 323         sets.
 324         (BFLOAT_SVE, BFLOAT): New feature set macros.
 325         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 326         instructions.
 327         (aarch64_opcode_table): Define new instructions bfdot,
 328         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 329         bfcvtn2, bfcvt.
 330
 331 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 332 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 333
 334         * aarch64-tbl.h (ARMV8_6): New macro.
 335
 336 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (prefix_table): Add mcommit.
 339         (rm_table): Add rdpru.
 340         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 341         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 342         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 343         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 344         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 345         * i386-opc.tbl (mcommit, rdpru): New.
 346         * i386-init.h, i386-tbl.h: Re-generate.
 347
 348 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 351         "names32" instead.
 352         (OP_Monitor): Drop local variable "op1_names", re-purpose
 353         "names" for it instead, and replace former "names" uses by
 354         "names32" ones.
 355
 356 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 357
 358         PR/gas 25167
 359         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 360         operand-less forms.
 361         * opcodes/i386-tbl.h: Re-generate.
 362
 363 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-dis.c (OP_Mwaitx): Delete.
 366         (prefix_table): Use OP_Mwait for mwaitx entry.
 367         (OP_Mwait): Also handle mwaitx.
 368
 369 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 372         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 373         (prefix_table): Add respective entries.
 374         (rm_table): Link to those entries.
 375
 376 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 379         (REG_0F1C_P_0_MOD_0): ... this.
 380         (REG_0F1E_MOD_3): Rename to ...
 381         (REG_0F1E_P_1_MOD_3): ... this.
 382         (RM_0F01_REG_5): Rename to ...
 383         (RM_0F01_REG_5_MOD_3): ... this.
 384         (RM_0F01_REG_7): Rename to ...
 385         (RM_0F01_REG_7_MOD_3): ... this.
 386         (RM_0F1E_MOD_3_REG_7): Rename to ...
 387         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 388         (RM_0FAE_REG_6): Rename to ...
 389         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 390         (RM_0FAE_REG_7): Rename to ...
 391         (RM_0FAE_REG_7_MOD_3): ... this.
 392         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 393         (PREFIX_0F01_REG_5_MOD_0): ... this.
 394         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 395         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 396         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 397         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 398         (PREFIX_0FAE_REG_0): Rename to ...
 399         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 400         (PREFIX_0FAE_REG_1): Rename to ...
 401         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 402         (PREFIX_0FAE_REG_2): Rename to ...
 403         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 404         (PREFIX_0FAE_REG_3): Rename to ...
 405         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 406         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 407         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 408         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 409         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 410         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 411         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 412         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 413         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 414         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 415         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 416         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 417         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 418         (PREFIX_0FAE_REG_7): Rename to ...
 419         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 420         (PREFIX_MOD_0_0FC3): Rename to ...
 421         (PREFIX_0FC3_MOD_0): ... this.
 422         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 423         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 424         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 425         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 426         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 427         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 428         (reg_table, prefix_table, mod_table, rm_table): Adjust
 429         accordingly.
 430
 431 2019-11-04  Nick Clifton  <nickc@redhat.com>
 432
 433         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 434         of a v850 system register.  Move the v850_sreg_names array into
 435         this function.
 436         (get_v850_reg_name): Likewise for ordinary register names.
 437         (get_v850_vreg_name): Likewise for vector register names.
 438         (get_v850_cc_name): Likewise for condition codes.
 439         * get_v850_float_cc_name): Likewise for floating point condition
 440         codes.
 441         (get_v850_cacheop_name): Likewise for cache-ops.
 442         (get_v850_prefop_name): Likewise for pref-ops.
 443         (disassemble): Use the new accessor functions.
 444
 445 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 446
 447         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 448         immediate for the writeback form of ldraa/ldrab if it is 0.
 449         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 450         * aarch64-opc-2.c: Regenerated.
 451
 452 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-gen.c (operand_type_shorthands): Delete.
 455         (operand_type_init): Expand previous shorthands.
 456         (set_bitfield_from_shorthand): Rename back to ...
 457         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 458         of operand_type_init[].
 459         (set_bitfield): Adjust call to the above function.
 460         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 461         RegXMM, RegYMM, RegZMM): Define.
 462         * i386-reg.tbl: Expand prior shorthands.
 463
 464 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-gen.c (output_i386_opcode): Change order of fields
 467         emitted to output.
 468         * i386-opc.h (struct insn_template): Move operands field.
 469         Convert extension_opcode field to unsigned short.
 470         * i386-tbl.h: Re-generate.
 471
 472 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 475         of W.
 476         * i386-opc.h (W): Extend comment.
 477         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 478         general purpose variants not allowing for byte operands.
 479         * i386-tbl.h: Re-generate.
 480
 481 2019-10-29  Nick Clifton  <nickc@redhat.com>
 482
 483         * tic30-dis.c (print_branch): Correct size of operand array.
 484
 485 2019-10-29  Nick Clifton  <nickc@redhat.com>
 486
 487         * d30v-dis.c (print_insn): Check that operand index is valid
 488         before attempting to access the operands array.
 489
 490 2019-10-29  Nick Clifton  <nickc@redhat.com>
 491
 492         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 493         locating the bit to be tested.
 494
 495 2019-10-29  Nick Clifton  <nickc@redhat.com>
 496
 497         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 498         values.
 499         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 500         (print_insn_s12z):  Check for illegal size values.
 501
 502 2019-10-28  Nick Clifton  <nickc@redhat.com>
 503
 504         * csky-dis.c (csky_chars_to_number): Check for a negative
 505         count. Use an unsigned integer to construct the return value.
 506
 507 2019-10-28  Nick Clifton  <nickc@redhat.com>
 508
 509         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 510         operand buffer.  Set value to 15 not 13.
 511         (get_register_operand): Use OPERAND_BUFFER_LEN.
 512         (get_indirect_operand): Likewise.
 513         (print_two_operand): Likewise.
 514         (print_three_operand): Likewise.
 515         (print_oar_insn): Likewise.
 516
 517 2019-10-28  Nick Clifton  <nickc@redhat.com>
 518
 519         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 520         (bit_extract_simple): Likewise.
 521         (bit_copy): Likewise.
 522         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 523         index_offset array are not accessed.
 524
 525 2019-10-28  Nick Clifton  <nickc@redhat.com>
 526
 527         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 528         operand.
 529
 530 2019-10-25  Nick Clifton  <nickc@redhat.com>
 531
 532         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 533         access to opcodes.op array element.
 534
 535 2019-10-23  Nick Clifton  <nickc@redhat.com>
 536
 537         * rx-dis.c (get_register_name): Fix spelling typo in error
 538         message.
 539         (get_condition_name, get_flag_name, get_double_register_name)
 540         (get_double_register_high_name, get_double_register_low_name)
 541         (get_double_control_register_name, get_double_condition_name)
 542         (get_opsize_name, get_size_name): Likewise.
 543
 544 2019-10-22  Nick Clifton  <nickc@redhat.com>
 545
 546         * rx-dis.c (get_size_name): New function.  Provides safe
 547         access to name array.
 548         (get_opsize_name): Likewise.
 549         (print_insn_rx): Use the accessor functions.
 550
 551 2019-10-16  Nick Clifton  <nickc@redhat.com>
 552
 553         * rx-dis.c (get_register_name): New function.  Provides safe
 554         access to name array.
 555         (get_condition_name, get_flag_name, get_double_register_name)
 556         (get_double_register_high_name, get_double_register_low_name)
 557         (get_double_control_register_name, get_double_condition_name):
 558         Likewise.
 559         (print_insn_rx): Use the accessor functions.
 560
 561 2019-10-09  Nick Clifton  <nickc@redhat.com>
 562
 563         PR 25041
 564         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 565         instructions.
 566
 567 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 568
 569         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 570         (cmpsd): Likewise. Move EsSeg to other operand.
 571         * opcodes/i386-tbl.h: Re-generate.
 572
 573 2019-09-23  Alan Modra  <amodra@gmail.com>
 574
 575         * m68k-dis.c: Include cpu-m68k.h
 576
 577 2019-09-23  Alan Modra  <amodra@gmail.com>
 578
 579         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 580         "elf/mips.h" earlier.
 581
 582 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 583
 584         PR gas/25012
 585         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 586         with SReg operand.
 587         * i386-tbl.h: Re-generate.
 588
 589 2019-09-18  Alan Modra  <amodra@gmail.com>
 590
 591         * arc-ext.c: Update throughout for bfd section macro changes.
 592
 593 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 594
 595         * Makefile.in: Re-generate.
 596         * configure: Re-generate.
 597
 598 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 599
 600         * riscv-opc.c (riscv_opcodes): Change subset field
 601         to insn_class field for all instructions.
 602         (riscv_insn_types): Likewise.
 603
 604 2019-09-16  Phil Blundell  <pb@pbcl.net>
 605
 606         * configure: Regenerated.
 607
 608 2019-09-10  Miod Vallat  <miod@online.fr>
 609
 610         PR 24982
 611         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 612
 613 2019-09-09  Phil Blundell  <pb@pbcl.net>
 614
 615         binutils 2.33 branch created.
 616
 617 2019-09-03  Nick Clifton  <nickc@redhat.com>
 618
 619         PR 24961
 620         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 621         greater than zero before indexing via (bufcnt -1).
 622
 623 2019-09-03  Nick Clifton  <nickc@redhat.com>
 624
 625         PR 24958
 626         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 627         (MAX_SPEC_REG_NAME_LEN): Define.
 628         (struct mmix_dis_info): Use defined constants for array lengths.
 629         (get_reg_name): New function.
 630         (get_sprec_reg_name): New function.
 631         (print_insn_mmix): Use new functions.
 632
 633 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 634
 635         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 636         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 637         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 638
 639 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 640
 641         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 642         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 643         (aarch64_sys_reg_supported_p): Update checks for the above.
 644
 645 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 646
 647         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 648         cases MVE_SQRSHRL and MVE_UQRSHLL.
 649         (print_insn_mve): Add case for specifier 'k' to check
 650         specific bit of the instruction.
 651
 652 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 653
 654         PR 24854
 655         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 656         encountering an unknown machine type.
 657         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 658         cases return -1 rather than calling abort.
 659
 660 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 663         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 664         IgnoreSize.
 665         * i386-tbl.h: Re-generate.
 666
 667 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 668
 669         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 670         instructions.
 671
 672 2019-07-30  Mel Chen <mel.chen@sifive.com>
 673
 674         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 675         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 676
 677         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 678         fscsr.
 679
 680 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 681
 682         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 683         and MPY class instructions.
 684         (parse_option): Add nps400 option.
 685         (print_arc_disassembler_options): Add nps400 info.
 686
 687 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 688
 689         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 690         (bspop): Likewise.
 691         (modapp): Likewise.
 692         * arc-opc.c (RAD_CHK): Add.
 693         * arc-tbl.h: Regenerate.
 694
 695 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 696
 697         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 698         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 699
 700 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 701
 702         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 703         instructions as UNPREDICTABLE.
 704
 705 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 706
 707         * bpf-desc.c: Regenerated.
 708
 709 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-gen.c (static_assert): Define.
 712         (main): Use it.
 713         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 714         (Opcode_Modifier_Num): ... this.
 715         (Mem): Delete.
 716
 717 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-gen.c (operand_types): Move RegMem ...
 720         (opcode_modifiers): ... here.
 721         * i386-opc.h (RegMem): Move to opcode modifer enum.
 722         (union i386_operand_type): Move regmem field ...
 723         (struct i386_opcode_modifier): ... here.
 724         * i386-opc.tbl (RegMem): Define.
 725         (mov, movq): Move RegMem on segment, control, debug, and test
 726         register flavors.
 727         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 728         to non-SSE2AVX flavor.
 729         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 730         Move RegMem on register only flavors. Drop IgnoreSize from
 731         legacy encoding flavors.
 732         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 733         flavors.
 734         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 735         register only flavors.
 736         (vmovd): Move RegMem and drop IgnoreSize on register only
 737         flavor. Change opcode and operand order to store form.
 738         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 739
 740 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 743         entries.
 744         * i386-opc.h (SReg2, SReg3): Replace by ...
 745         (SReg): ... this.
 746         (union i386_operand_type): Replace sreg fields.
 747         * i386-opc.tbl (mov, ): Use SReg.
 748         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 749         register flavors.
 750         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 751         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 752
 753 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 754
 755         * bpf-desc.c: Regenerate.
 756         * bpf-opc.c: Likewise.
 757         * bpf-opc.h: Likewise.
 758
 759 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 760
 761         * bpf-desc.c: Regenerate.
 762         * bpf-opc.c: Likewise.
 763
 764 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 765
 766         * arm-dis.c (print_insn_coprocessor): Rename index to
 767         index_operand.
 768
 769 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 770
 771         * riscv-opc.c (riscv_insn_types): Add r4 type.
 772
 773         * riscv-opc.c (riscv_insn_types): Add b and j type.
 774
 775         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 776         format for sb type and correct s type.
 777
 778 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 779
 780         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 781         SVE FMOV alias of FCPY.
 782
 783 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 784
 785         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 786         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 787
 788 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 789
 790         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 791         registers in an instruction prefixed by MOVPRFX.
 792
 793 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 794
 795         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 796         sve_size_13 icode to account for variant behaviour of
 797         pmull{t,b}.
 798         * aarch64-dis-2.c: Regenerate.
 799         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 800         sve_size_13 icode to account for variant behaviour of
 801         pmull{t,b}.
 802         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 803         (OP_SVE_VVV_Q_D): Add new qualifier.
 804         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 805         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 806         AES and those not.
 807
 808 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 809
 810         * opcodes/i386-gen.c (operand_type_init): Remove
 811         OPERAND_TYPE_VEC_IMM4 entry.
 812         (operand_types): Remove Vec_Imm4.
 813         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 814         (union i386_operand_type): Remove vec_imm4.
 815         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 816         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 817
 818 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 821         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 822         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 823         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 824         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 825         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 826         * i386-tbl.h: Re-generate.
 827
 828 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 831         register operands.
 832         * i386-tbl.h: Re-generate.
 833
 834 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl (C): New.
 837         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 838         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 839         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 840         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 841         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 842         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 843         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 844         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 845         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 846         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 847         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 848         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 849         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 850         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 851         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 852         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 853         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 854         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 855         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 856         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 857         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 858         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 859         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 860         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 861         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 862         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 863         flavors.
 864         * i386-tbl.h: Re-generate.
 865
 866 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 869         register operands.
 870         * i386-tbl.h: Re-generate.
 871
 872 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 875         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 876         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 877         * i386-tbl.h: Re-generate.
 878
 879 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 882         Disp8MemShift from register only templates.
 883         * i386-tbl.h: Re-generate.
 884
 885 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 886
 887         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 888         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 889         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 890         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 891         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 892         EVEX_W_0F11_P_3_M_1): Delete.
 893         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 894         EVEX_W_0F11_P_3): New.
 895         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 896         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 897         MOD_EVEX_0F11_PREFIX_3 table entries.
 898         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 899         PREFIX_EVEX_0F11 table entries.
 900         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 901         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 902         EVEX_W_0F11_P_3_M_{0,1} table entries.
 903
 904 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 907         Delete.
 908
 909 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         PR binutils/24719
 912         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 913         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 914         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 915         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 916         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 917         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 918         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 919         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 920         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 921         PREFIX_EVEX_0F38C6_REG_6 entries.
 922         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 923         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 924         EVEX_W_0F38C7_R_6_P_2 entries.
 925         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 926         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 927         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 928         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 929         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 930         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 931         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 932
 933 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 936         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 937         VEX_LEN_0F2D_P_3): Delete.
 938         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 939         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 940         (prefix_table): ... here.
 941
 942 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-dis.c (Iq): Delete.
 945         (Id): New.
 946         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 947         TBM insns.
 948         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 949         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 950         (OP_E_memory): Also honor needindex when deciding whether an
 951         address size prefix needs printing.
 952         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 953
 954 2019-06-26  Jim Wilson  <jimw@sifive.com>
 955
 956         PR binutils/24739
 957         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 958         Set info->display_endian to info->endian_code.
 959
 960 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 963         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 964         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 965         OPERAND_TYPE_ACC64 entries.
 966         * i386-init.h: Re-generate.
 967
 968 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 971         Delete.
 972         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 973         of dqa_mode.
 974         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 975         entries here.
 976         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 977         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 978
 979 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 982         variables.
 983
 984 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 985
 986         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 987         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 988         movnti.
 989         * i386-opc.tbl (movnti): Add IgnoreSize.
 990         * i386-tbl.h: Re-generate.
 991
 992 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 995         * i386-tbl.h: Re-generate.
 996
 997 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 998
 999         * i386-dis-evex.h: Break into ...
1000         * i386-dis-evex-len.h: New file.
1001         * i386-dis-evex-mod.h: Likewise.
1002         * i386-dis-evex-prefix.h: Likewise.
1003         * i386-dis-evex-reg.h: Likewise.
1004         * i386-dis-evex-w.h: Likewise.
1005         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1006         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1007         i386-dis-evex-mod.h.
1008
1009 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1010
1011         PR binutils/24700
1012         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1013         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1014         EVEX_W_0F385B_P_2.
1015         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1016         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1017         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1018         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1019         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1020         EVEX_LEN_0F385B_P_2_W_1.
1021         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1022         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1023         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1024         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1025         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1026         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1027         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1028         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1029         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1030         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1031
1032 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1033
1034         PR binutils/24691
1035         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1036         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1037         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1038         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1039         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1040         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1041         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1042         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1043         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1044         EVEX_LEN_0F3A43_P_2_W_1.
1045         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1046         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1047         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1048         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1049         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1050         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1051         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1052         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1053         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1054         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1055         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1056         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1057
1058 2019-06-14  Nick Clifton  <nickc@redhat.com>
1059
1060         * po/fr.po; Updated French translation.
1061
1062 2019-06-13  Stafford Horne  <shorne@gmail.com>
1063
1064         * or1k-asm.c: Regenerated.
1065         * or1k-desc.c: Regenerated.
1066         * or1k-desc.h: Regenerated.
1067         * or1k-dis.c: Regenerated.
1068         * or1k-ibld.c: Regenerated.
1069         * or1k-opc.c: Regenerated.
1070         * or1k-opc.h: Regenerated.
1071         * or1k-opinst.c: Regenerated.
1072
1073 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1074
1075         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1076
1077 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1078
1079         PR binutils/24633
1080         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1081         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1082         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1083         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1084         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1085         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1086         EVEX_LEN_0F3A1B_P_2_W_1.
1087         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1088         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1089         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1090         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1091         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1092         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1093         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1094         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1095
1096 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1097
1098         PR binutils/24626
1099         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1100         EVEX.vvvv when disassembling VEX and EVEX instructions.
1101         (OP_VEX): Set vex.register_specifier to 0 after readding
1102         vex.register_specifier.
1103         (OP_Vex_2src_1): Likewise.
1104         (OP_Vex_2src_2): Likewise.
1105         (OP_LWP_E): Likewise.
1106         (OP_EX_Vex): Don't check vex.register_specifier.
1107         (OP_XMM_Vex): Likewise.
1108
1109 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1110             Lili Cui  <lili.cui@intel.com>
1111
1112         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1113         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1114         instructions.
1115         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1116         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1117         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1118         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1119         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1120         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1121         * i386-init.h: Regenerated.
1122         * i386-tbl.h: Likewise.
1123
1124 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1125             Lili Cui  <lili.cui@intel.com>
1126
1127         * doc/c-i386.texi: Document enqcmd.
1128         * testsuite/gas/i386/enqcmd-intel.d: New file.
1129         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1130         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1131         * testsuite/gas/i386/enqcmd.d: Likewise.
1132         * testsuite/gas/i386/enqcmd.s: Likewise.
1133         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1134         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1135         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1136         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1137         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1138         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1139         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1140         and x86-64-enqcmd.
1141
1142 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1143
1144         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1145
1146 2019-06-03  Alan Modra  <amodra@gmail.com>
1147
1148         * ppc-dis.c (prefix_opcd_indices): Correct size.
1149
1150 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         PR gas/24625
1153         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1154         Disp8ShiftVL.
1155         * i386-tbl.h: Regenerated.
1156
1157 2019-05-24  Alan Modra  <amodra@gmail.com>
1158
1159         * po/POTFILES.in: Regenerate.
1160
1161 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1162             Alan Modra  <amodra@gmail.com>
1163
1164         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1165         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1166         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1167         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1168         XTOP>): Define and add entries.
1169         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1170         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1171         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1172         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1173
1174 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1175             Alan Modra  <amodra@gmail.com>
1176
1177         * ppc-dis.c (ppc_opts): Add "future" entry.
1178         (PREFIX_OPCD_SEGS): Define.
1179         (prefix_opcd_indices): New array.
1180         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1181         (lookup_prefix): New function.
1182         (print_insn_powerpc): Handle 64-bit prefix instructions.
1183         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1184         (PMRR, POWERXX): Define.
1185         (prefix_opcodes): New instruction table.
1186         (prefix_num_opcodes): New constant.
1187
1188 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1189
1190         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1191         * configure: Regenerated.
1192         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1193         and cpu/bpf.opc.
1194         (HFILES): Add bpf-desc.h and bpf-opc.h.
1195         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1196         bpf-ibld.c and bpf-opc.c.
1197         (BPF_DEPS): Define.
1198         * Makefile.in: Regenerated.
1199         * disassemble.c (ARCH_bpf): Define.
1200         (disassembler): Add case for bfd_arch_bpf.
1201         (disassemble_init_for_target): Likewise.
1202         (enum epbf_isa_attr): Define.
1203         * disassemble.h: extern print_insn_bpf.
1204         * bpf-asm.c: Generated.
1205         * bpf-opc.h: Likewise.
1206         * bpf-opc.c: Likewise.
1207         * bpf-ibld.c: Likewise.
1208         * bpf-dis.c: Likewise.
1209         * bpf-desc.h: Likewise.
1210         * bpf-desc.c: Likewise.
1211
1212 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1213
1214         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1215         and VMSR with the new operands.
1216
1217 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1218
1219         * arm-dis.c (enum mve_instructions): New enum
1220         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1221         and cneg.
1222         (mve_opcodes): New instructions as above.
1223         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1224         csneg and csel.
1225         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1226
1227 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1228
1229         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1230         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1231         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1232         uqshl, urshrl and urshr.
1233         (is_mve_okay_in_it): Add new instructions to TRUE list.
1234         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1235         (print_insn_mve): Updated to accept new %j,
1236         %<bitfield>m and %<bitfield>n patterns.
1237
1238 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1239
1240         * mips-opc.c (mips_builtin_opcodes): Change source register
1241         constraint for DAUI.
1242
1243 2019-05-20  Nick Clifton  <nickc@redhat.com>
1244
1245         * po/fr.po: Updated French translation.
1246
1247 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1248             Michael Collison <michael.collison@arm.com>
1249
1250         * arm-dis.c (thumb32_opcodes): Add new instructions.
1251         (enum mve_instructions): Likewise.
1252         (enum mve_undefined): Add new reasons.
1253         (is_mve_encoding_conflict): Handle new instructions.
1254         (is_mve_undefined): Likewise.
1255         (is_mve_unpredictable): Likewise.
1256         (print_mve_undefined): Likewise.
1257         (print_mve_size): Likewise.
1258
1259 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1260             Michael Collison <michael.collison@arm.com>
1261
1262         * arm-dis.c (thumb32_opcodes): Add new instructions.
1263         (enum mve_instructions): Likewise.
1264         (is_mve_encoding_conflict): Handle new instructions.
1265         (is_mve_undefined): Likewise.
1266         (is_mve_unpredictable): Likewise.
1267         (print_mve_size): Likewise.
1268
1269 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1270             Michael Collison <michael.collison@arm.com>
1271
1272         * arm-dis.c (thumb32_opcodes): Add new instructions.
1273         (enum mve_instructions): Likewise.
1274         (is_mve_encoding_conflict): Likewise.
1275         (is_mve_unpredictable): Likewise.
1276         (print_mve_size): Likewise.
1277
1278 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1279             Michael Collison <michael.collison@arm.com>
1280
1281         * arm-dis.c (thumb32_opcodes): Add new instructions.
1282         (enum mve_instructions): Likewise.
1283         (is_mve_encoding_conflict): Handle new instructions.
1284         (is_mve_undefined): Likewise.
1285         (is_mve_unpredictable): Likewise.
1286         (print_mve_size): Likewise.
1287
1288 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1289             Michael Collison <michael.collison@arm.com>
1290
1291         * arm-dis.c (thumb32_opcodes): Add new instructions.
1292         (enum mve_instructions): Likewise.
1293         (is_mve_encoding_conflict): Handle new instructions.
1294         (is_mve_undefined): Likewise.
1295         (is_mve_unpredictable): Likewise.
1296         (print_mve_size): Likewise.
1297         (print_insn_mve): Likewise.
1298
1299 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1300             Michael Collison <michael.collison@arm.com>
1301
1302         * arm-dis.c (thumb32_opcodes): Add new instructions.
1303         (print_insn_thumb32): Handle new instructions.
1304
1305 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1306             Michael Collison <michael.collison@arm.com>
1307
1308         * arm-dis.c (enum mve_instructions): Add new instructions.
1309         (enum mve_undefined): Add new reasons.
1310         (is_mve_encoding_conflict): Handle new instructions.
1311         (is_mve_undefined): Likewise.
1312         (is_mve_unpredictable): Likewise.
1313         (print_mve_undefined): Likewise.
1314         (print_mve_size): Likewise.
1315         (print_mve_shift_n): Likewise.
1316         (print_insn_mve): Likewise.
1317
1318 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1319             Michael Collison <michael.collison@arm.com>
1320
1321         * arm-dis.c (enum mve_instructions): Add new instructions.
1322         (is_mve_encoding_conflict): Handle new instructions.
1323         (is_mve_unpredictable): Likewise.
1324         (print_mve_rotate): Likewise.
1325         (print_mve_size): Likewise.
1326         (print_insn_mve): Likewise.
1327
1328 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1329             Michael Collison <michael.collison@arm.com>
1330
1331         * arm-dis.c (enum mve_instructions): Add new instructions.
1332         (is_mve_encoding_conflict): Handle new instructions.
1333         (is_mve_unpredictable): Likewise.
1334         (print_mve_size): Likewise.
1335         (print_insn_mve): Likewise.
1336
1337 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1338             Michael Collison <michael.collison@arm.com>
1339
1340         * arm-dis.c (enum mve_instructions): Add new instructions.
1341         (enum mve_undefined): Add new reasons.
1342         (is_mve_encoding_conflict): Handle new instructions.
1343         (is_mve_undefined): Likewise.
1344         (is_mve_unpredictable): Likewise.
1345         (print_mve_undefined): Likewise.
1346         (print_mve_size): Likewise.
1347         (print_insn_mve): Likewise.
1348
1349 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1350             Michael Collison <michael.collison@arm.com>
1351
1352         * arm-dis.c (enum mve_instructions): Add new instructions.
1353         (is_mve_encoding_conflict): Handle new instructions.
1354         (is_mve_undefined): Likewise.
1355         (is_mve_unpredictable): Likewise.
1356         (print_mve_size): Likewise.
1357         (print_insn_mve): Likewise.
1358
1359 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1360             Michael Collison <michael.collison@arm.com>
1361
1362         * arm-dis.c (enum mve_instructions): Add new instructions.
1363         (enum mve_unpredictable): Add new reasons.
1364         (enum mve_undefined): Likewise.
1365         (is_mve_okay_in_it): Handle new isntructions.
1366         (is_mve_encoding_conflict): Likewise.
1367         (is_mve_undefined): Likewise.
1368         (is_mve_unpredictable): Likewise.
1369         (print_mve_vmov_index): Likewise.
1370         (print_simd_imm8): Likewise.
1371         (print_mve_undefined): Likewise.
1372         (print_mve_unpredictable): Likewise.
1373         (print_mve_size): Likewise.
1374         (print_insn_mve): Likewise.
1375
1376 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1377             Michael Collison <michael.collison@arm.com>
1378
1379         * arm-dis.c (enum mve_instructions): Add new instructions.
1380         (enum mve_unpredictable): Add new reasons.
1381         (enum mve_undefined): Likewise.
1382         (is_mve_encoding_conflict): Handle new instructions.
1383         (is_mve_undefined): Likewise.
1384         (is_mve_unpredictable): Likewise.
1385         (print_mve_undefined): Likewise.
1386         (print_mve_unpredictable): Likewise.
1387         (print_mve_rounding_mode): Likewise.
1388         (print_mve_vcvt_size): Likewise.
1389         (print_mve_size): Likewise.
1390         (print_insn_mve): Likewise.
1391
1392 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1393             Michael Collison <michael.collison@arm.com>
1394
1395         * arm-dis.c (enum mve_instructions): Add new instructions.
1396         (enum mve_unpredictable): Add new reasons.
1397         (enum mve_undefined): Likewise.
1398         (is_mve_undefined): Handle new instructions.
1399         (is_mve_unpredictable): Likewise.
1400         (print_mve_undefined): Likewise.
1401         (print_mve_unpredictable): Likewise.
1402         (print_mve_size): Likewise.
1403         (print_insn_mve): Likewise.
1404
1405 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1406             Michael Collison <michael.collison@arm.com>
1407
1408         * arm-dis.c (enum mve_instructions): Add new instructions.
1409         (enum mve_undefined): Add new reasons.
1410         (insns): Add new instructions.
1411         (is_mve_encoding_conflict):
1412         (print_mve_vld_str_addr): New print function.
1413         (is_mve_undefined): Handle new instructions.
1414         (is_mve_unpredictable): Likewise.
1415         (print_mve_undefined): Likewise.
1416         (print_mve_size): Likewise.
1417         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1418         (print_insn_mve):  Handle new operands.
1419
1420 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1421             Michael Collison <michael.collison@arm.com>
1422
1423         * arm-dis.c (enum mve_instructions): Add new instructions.
1424         (enum mve_unpredictable): Add new reasons.
1425         (is_mve_encoding_conflict): Handle new instructions.
1426         (is_mve_unpredictable): Likewise.
1427         (mve_opcodes): Add new instructions.
1428         (print_mve_unpredictable): Handle new reasons.
1429         (print_mve_register_blocks): New print function.
1430         (print_mve_size): Handle new instructions.
1431         (print_insn_mve): Likewise.
1432
1433 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1434             Michael Collison <michael.collison@arm.com>
1435
1436         * arm-dis.c (enum mve_instructions): Add new instructions.
1437         (enum mve_unpredictable): Add new reasons.
1438         (enum mve_undefined): Likewise.
1439         (is_mve_encoding_conflict): Handle new instructions.
1440         (is_mve_undefined): Likewise.
1441         (is_mve_unpredictable): Likewise.
1442         (coprocessor_opcodes): Move NEON VDUP from here...
1443         (neon_opcodes): ... to here.
1444         (mve_opcodes): Add new instructions.
1445         (print_mve_undefined):  Handle new reasons.
1446         (print_mve_unpredictable): Likewise.
1447         (print_mve_size): Handle new instructions.
1448         (print_insn_neon): Handle vdup.
1449         (print_insn_mve): Handle new operands.
1450
1451 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1452             Michael Collison <michael.collison@arm.com>
1453
1454         * arm-dis.c (enum mve_instructions): Add new instructions.
1455         (enum mve_unpredictable): Add new values.
1456         (mve_opcodes): Add new instructions.
1457         (vec_condnames): New array with vector conditions.
1458         (mve_predicatenames): New array with predicate suffixes.
1459         (mve_vec_sizename): New array with vector sizes.
1460         (enum vpt_pred_state): New enum with vector predication states.
1461         (struct vpt_block): New struct type for vpt blocks.
1462         (vpt_block_state): Global struct to keep track of state.
1463         (mve_extract_pred_mask): New helper function.
1464         (num_instructions_vpt_block): Likewise.
1465         (mark_outside_vpt_block): Likewise.
1466         (mark_inside_vpt_block): Likewise.
1467         (invert_next_predicate_state): Likewise.
1468         (update_next_predicate_state): Likewise.
1469         (update_vpt_block_state): Likewise.
1470         (is_vpt_instruction): Likewise.
1471         (is_mve_encoding_conflict): Add entries for new instructions.
1472         (is_mve_unpredictable): Likewise.
1473         (print_mve_unpredictable): Handle new cases.
1474         (print_instruction_predicate): Likewise.
1475         (print_mve_size): New function.
1476         (print_vec_condition): New function.
1477         (print_insn_mve): Handle vpt blocks and new print operands.
1478
1479 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1480
1481         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1482         8, 14 and 15 for Armv8.1-M Mainline.
1483
1484 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1485             Michael Collison <michael.collison@arm.com>
1486
1487         * arm-dis.c (enum mve_instructions): New enum.
1488         (enum mve_unpredictable): Likewise.
1489         (enum mve_undefined): Likewise.
1490         (struct mopcode32): New struct.
1491         (is_mve_okay_in_it): New function.
1492         (is_mve_architecture): Likewise.
1493         (arm_decode_field): Likewise.
1494         (arm_decode_field_multiple): Likewise.
1495         (is_mve_encoding_conflict): Likewise.
1496         (is_mve_undefined): Likewise.
1497         (is_mve_unpredictable): Likewise.
1498         (print_mve_undefined): Likewise.
1499         (print_mve_unpredictable): Likewise.
1500         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1501         (print_insn_mve): New function.
1502         (print_insn_thumb32): Handle MVE architecture.
1503         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1504
1505 2019-05-10  Nick Clifton  <nickc@redhat.com>
1506
1507         PR 24538
1508         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1509         end of the table prematurely.
1510
1511 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1512
1513         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1514         macros for R6.
1515
1516 2019-05-11  Alan Modra  <amodra@gmail.com>
1517
1518         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1519         when -Mraw is in effect.
1520
1521 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1522
1523         * aarch64-dis-2.c: Regenerate.
1524         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1525         (OP_SVE_BBB): New variant set.
1526         (OP_SVE_DDDD): New variant set.
1527         (OP_SVE_HHH): New variant set.
1528         (OP_SVE_HHHU): New variant set.
1529         (OP_SVE_SSS): New variant set.
1530         (OP_SVE_SSSU): New variant set.
1531         (OP_SVE_SHH): New variant set.
1532         (OP_SVE_SBBU): New variant set.
1533         (OP_SVE_DSS): New variant set.
1534         (OP_SVE_DHHU): New variant set.
1535         (OP_SVE_VMV_HSD_BHS): New variant set.
1536         (OP_SVE_VVU_HSD_BHS): New variant set.
1537         (OP_SVE_VVVU_SD_BH): New variant set.
1538         (OP_SVE_VVVU_BHSD): New variant set.
1539         (OP_SVE_VVV_QHD_DBS): New variant set.
1540         (OP_SVE_VVV_HSD_BHS): New variant set.
1541         (OP_SVE_VVV_HSD_BHS2): New variant set.
1542         (OP_SVE_VVV_BHS_HSD): New variant set.
1543         (OP_SVE_VV_BHS_HSD): New variant set.
1544         (OP_SVE_VVV_SD): New variant set.
1545         (OP_SVE_VVU_BHS_HSD): New variant set.
1546         (OP_SVE_VZVV_SD): New variant set.
1547         (OP_SVE_VZVV_BH): New variant set.
1548         (OP_SVE_VZV_SD): New variant set.
1549         (aarch64_opcode_table): Add sve2 instructions.
1550
1551 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1552
1553         * aarch64-asm-2.c: Regenerated.
1554         * aarch64-dis-2.c: Regenerated.
1555         * aarch64-opc-2.c: Regenerated.
1556         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1557         for SVE_SHLIMM_UNPRED_22.
1558         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1559         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1560         operand.
1561
1562 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1563
1564         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1565         sve_size_tsz_bhs iclass encode.
1566         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1567         sve_size_tsz_bhs iclass decode.
1568
1569 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1570
1571         * aarch64-asm-2.c: Regenerated.
1572         * aarch64-dis-2.c: Regenerated.
1573         * aarch64-opc-2.c: Regenerated.
1574         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1575         for SVE_Zm4_11_INDEX.
1576         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1577         (fields): Handle SVE_i2h field.
1578         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1579         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1580
1581 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1582
1583         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1584         sve_shift_tsz_bhsd iclass encode.
1585         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1586         sve_shift_tsz_bhsd iclass decode.
1587
1588 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1589
1590         * aarch64-asm-2.c: Regenerated.
1591         * aarch64-dis-2.c: Regenerated.
1592         * aarch64-opc-2.c: Regenerated.
1593         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1594         (aarch64_encode_variant_using_iclass): Handle
1595         sve_shift_tsz_hsd iclass encode.
1596         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1597         sve_shift_tsz_hsd iclass decode.
1598         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1599         for SVE_SHRIMM_UNPRED_22.
1600         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1601         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1602         operand.
1603
1604 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1605
1606         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1607         sve_size_013 iclass encode.
1608         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1609         sve_size_013 iclass decode.
1610
1611 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1612
1613         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1614         sve_size_bh iclass encode.
1615         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1616         sve_size_bh iclass decode.
1617
1618 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1619
1620         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1621         sve_size_sd2 iclass encode.
1622         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1623         sve_size_sd2 iclass decode.
1624         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1625         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1626
1627 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1628
1629         * aarch64-asm-2.c: Regenerated.
1630         * aarch64-dis-2.c: Regenerated.
1631         * aarch64-opc-2.c: Regenerated.
1632         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1633         for SVE_ADDR_ZX.
1634         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1635         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1636
1637 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1638
1639         * aarch64-asm-2.c: Regenerated.
1640         * aarch64-dis-2.c: Regenerated.
1641         * aarch64-opc-2.c: Regenerated.
1642         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1643         for SVE_Zm3_11_INDEX.
1644         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1645         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1646         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1647         fields.
1648         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1649
1650 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1651
1652         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1653         sve_size_hsd2 iclass encode.
1654         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1655         sve_size_hsd2 iclass decode.
1656         * aarch64-opc.c (fields): Handle SVE_size field.
1657         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1658
1659 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1660
1661         * aarch64-asm-2.c: Regenerated.
1662         * aarch64-dis-2.c: Regenerated.
1663         * aarch64-opc-2.c: Regenerated.
1664         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1665         for SVE_IMM_ROT3.
1666         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1667         (fields): Handle SVE_rot3 field.
1668         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1669         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1670
1671 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1672
1673         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1674         instructions.
1675
1676 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1677
1678         * aarch64-tbl.h
1679         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1680         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1681         aarch64_feature_sve2bitperm): New feature sets.
1682         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1683         for feature set addresses.
1684         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1685         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1686
1687 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1688             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1689
1690         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1691         argument and set ASE_EVA_R6 appropriately.
1692         (set_default_mips_dis_options): Pass ISA to above.
1693         (parse_mips_dis_option): Likewise.
1694         * mips-opc.c (EVAR6): New macro.
1695         (mips_builtin_opcodes): Add llwpe, scwpe.
1696
1697 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1698
1699         * aarch64-asm-2.c: Regenerated.
1700         * aarch64-dis-2.c: Regenerated.
1701         * aarch64-opc-2.c: Regenerated.
1702         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1703         AARCH64_OPND_TME_UIMM16.
1704         (aarch64_print_operand): Likewise.
1705         * aarch64-tbl.h (QL_IMM_NIL): New.
1706         (TME): New.
1707         (_TME_INSN): New.
1708         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1709
1710 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1711
1712         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1713
1714 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1715             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1716
1717         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1718
1719 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1720
1721         * s12z-opc.h: Add extern "C" bracketing to help
1722         users who wish to use this interface in c++ code.
1723
1724 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1725
1726         * s12z-opc.c (bm_decode): Handle bit map operations with the
1727         "reserved0" mode.
1728
1729 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1730
1731         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1732         specifier.  Add entries for VLDR and VSTR of system registers.
1733         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1734         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1735         of %J and %K format specifier.
1736
1737 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1738
1739         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1740         Add new entries for VSCCLRM instruction.
1741         (print_insn_coprocessor): Handle new %C format control code.
1742
1743 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1744
1745         * arm-dis.c (enum isa): New enum.
1746         (struct sopcode32): New structure.
1747         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1748         set isa field of all current entries to ANY.
1749         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1750         Only match an entry if its isa field allows the current mode.
1751
1752 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1753
1754         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1755         CLRM.
1756         (print_insn_thumb32): Add logic to print %n CLRM register list.
1757
1758 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1759
1760         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1761         and %Q patterns.
1762
1763 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1764
1765         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1766         (print_insn_thumb32): Edit the switch case for %Z.
1767
1768 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1769
1770         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1771
1772 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1773
1774         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1775
1776 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1777
1778         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1779
1780 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1781
1782         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1783         Arm register with r13 and r15 unpredictable.
1784         (thumb32_opcodes): New instructions for bfx and bflx.
1785
1786 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1787
1788         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1789
1790 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1791
1792         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1793
1794 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1795
1796         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1797
1798 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1799
1800         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1801
1802 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1803
1804         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1805         "optr". ("operator" is a reserved word in c++).
1806
1807 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1808
1809         * aarch64-opc.c (aarch64_print_operand): Add case for
1810         AARCH64_OPND_Rt_SP.
1811         (verify_constraints): Likewise.
1812         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1813         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1814         to accept Rt|SP as first operand.
1815         (AARCH64_OPERANDS): Add new Rt_SP.
1816         * aarch64-asm-2.c: Regenerated.
1817         * aarch64-dis-2.c: Regenerated.
1818         * aarch64-opc-2.c: Regenerated.
1819
1820 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1821
1822         * aarch64-asm-2.c: Regenerated.
1823         * aarch64-dis-2.c: Likewise.
1824         * aarch64-opc-2.c: Likewise.
1825         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1826
1827 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1828
1829         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1830
1831 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1832
1833         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1834         * i386-init.h: Regenerated.
1835
1836 2019-04-07  Alan Modra  <amodra@gmail.com>
1837
1838         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1839         op_separator to control printing of spaces, comma and parens
1840         rather than need_comma, need_paren and spaces vars.
1841
1842 2019-04-07  Alan Modra  <amodra@gmail.com>
1843
1844         PR 24421
1845         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1846         (print_insn_neon, print_insn_arm): Likewise.
1847
1848 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1849
1850         * i386-dis-evex.h (evex_table): Updated to support BF16
1851         instructions.
1852         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1853         and EVEX_W_0F3872_P_3.
1854         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1855         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1856         * i386-opc.h (enum): Add CpuAVX512_BF16.
1857         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1858         * i386-opc.tbl: Add AVX512 BF16 instructions.
1859         * i386-init.h: Regenerated.
1860         * i386-tbl.h: Likewise.
1861
1862 2019-04-05  Alan Modra  <amodra@gmail.com>
1863
1864         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1865         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1866         to favour printing of "-" branch hint when using the "y" bit.
1867         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1868
1869 2019-04-05  Alan Modra  <amodra@gmail.com>
1870
1871         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1872         opcode until first operand is output.
1873
1874 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1875
1876         PR gas/24349
1877         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1878         (valid_bo_post_v2): Add support for 'at' branch hints.
1879         (insert_bo): Only error on branch on ctr.
1880         (get_bo_hint_mask): New function.
1881         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1882         for inserting 'at' branch hints.
1883         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1884         for extracting 'at' branch hints.
1885         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1886         (BOE): Delete operand.
1887         (BOM, BOP): New operands.
1888         (RM): Update value.
1889         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1890         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1891         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1892         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1893         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1894         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1895         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1896         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1897         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1898         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1899         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1900         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1901         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1902         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1903         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1904         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1905         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1906         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1907         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1908         bttarl+>: New extended mnemonics.
1909
1910 2019-03-28  Alan Modra  <amodra@gmail.com>
1911
1912         PR 24390
1913         * ppc-opc.c (BTF): Define.
1914         (powerpc_opcodes): Use for mtfsb*.
1915         * ppc-dis.c (print_insn_powerpc): Print fields with both
1916         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1917
1918 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1919
1920         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1921         (mapping_symbol_for_insn): Implement new algorithm.
1922         (print_insn): Remove duplicate code.
1923
1924 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1925
1926         * aarch64-dis.c (print_insn_aarch64):
1927         Implement override.
1928
1929 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1930
1931         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1932         order.
1933
1934 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1935
1936         * aarch64-dis.c (last_stop_offset): New.
1937         (print_insn_aarch64): Use stop_offset.
1938
1939 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1940
1941         PR gas/24359
1942         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1943         CPU_ANY_AVX2_FLAGS.
1944         * i386-init.h: Regenerated.
1945
1946 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1947
1948         PR gas/24348
1949         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1950         vmovdqu16, vmovdqu32 and vmovdqu64.
1951         * i386-tbl.h: Regenerated.
1952
1953 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1954
1955         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1956         from vstrszb, vstrszh, and vstrszf.
1957
1958 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1959
1960         * s390-opc.txt: Add instruction descriptions.
1961
1962 2019-02-08  Jim Wilson  <jimw@sifive.com>
1963
1964         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1965         <bne>: Likewise.
1966
1967 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1968
1969         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1970
1971 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1972
1973         PR binutils/23212
1974         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1975         * aarch64-opc.c (verify_elem_sd): New.
1976         (fields): Add FLD_sz entr.
1977         * aarch64-tbl.h (_SIMD_INSN): New.
1978         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1979         fmulx scalar and vector by element isns.
1980
1981 2019-02-07  Nick Clifton  <nickc@redhat.com>
1982
1983         * po/sv.po: Updated Swedish translation.
1984
1985 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1986
1987         * s390-mkopc.c (main): Accept arch13 as cpu string.
1988         * s390-opc.c: Add new instruction formats and instruction opcode
1989         masks.
1990         * s390-opc.txt: Add new arch13 instructions.
1991
1992 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1993
1994         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1995         (aarch64_opcode): Change encoding for stg, stzg
1996         st2g and st2zg.
1997         * aarch64-asm-2.c: Regenerated.
1998         * aarch64-dis-2.c: Regenerated.
1999         * aarch64-opc-2.c: Regenerated.
2000
2001 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2002
2003         * aarch64-asm-2.c: Regenerated.
2004         * aarch64-dis-2.c: Likewise.
2005         * aarch64-opc-2.c: Likewise.
2006         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2007
2008 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2009             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2010
2011         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2012         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2013         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2014         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2015         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2016         case for ldstgv_indexed.
2017         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2018         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2019         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2020         * aarch64-asm-2.c: Regenerated.
2021         * aarch64-dis-2.c: Regenerated.
2022         * aarch64-opc-2.c: Regenerated.
2023
2024 2019-01-23  Nick Clifton  <nickc@redhat.com>
2025
2026         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2027
2028 2019-01-21  Nick Clifton  <nickc@redhat.com>
2029
2030         * po/de.po: Updated German translation.
2031         * po/uk.po: Updated Ukranian translation.
2032
2033 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2034         * mips-dis.c (mips_arch_choices): Fix typo in
2035         gs464, gs464e and gs264e descriptors.
2036
2037 2019-01-19  Nick Clifton  <nickc@redhat.com>
2038
2039         * configure: Regenerate.
2040         * po/opcodes.pot: Regenerate.
2041
2042 2018-06-24  Nick Clifton  <nickc@redhat.com>
2043
2044         2.32 branch created.
2045
2046 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2047
2048         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2049         if it is null.
2050         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2051         zero.
2052
2053 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2054
2055         * configure: Regenerate.
2056
2057 2019-01-07  Alan Modra  <amodra@gmail.com>
2058
2059         * configure: Regenerate.
2060         * po/POTFILES.in: Regenerate.
2061
2062 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2063
2064         * s12z-opc.c: New file.
2065         * s12z-opc.h: New file.
2066         * s12z-dis.c: Removed all code not directly related to display
2067         of instructions.  Used the interface provided by the new files
2068         instead.
2069         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2070         * Makefile.in: Regenerate.
2071         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2072         * configure: Regenerate.
2073
2074 2019-01-01  Alan Modra  <amodra@gmail.com>
2075
2076         Update year range in copyright notice of all files.
2077
2078 For older changes see ChangeLog-2018
2079 \f
2080 Copyright (C) 2019 Free Software Foundation, Inc.
2081
2082 Copying and distribution of this file, with or without modification,
2083 are permitted in any medium without royalty provided the copyright
2084 notice and this notice are preserved.
2085
2086 Local Variables:
2087 mode: change-log
2088 left-margin: 8
2089 fill-column: 74
2090 version-control: never
2091 End: