1 2010-11-05 Tristan Gingold <gingold@adacore.com>
3 * po/opcodes.pot: Regenerate
5 2010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
7 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
9 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
11 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
13 2010-10-25 Chao-ying Fu <fu@mips.com>
15 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
17 2010-10-25 Nathan Sidwell <nathan@codesourcery.com>
19 * tic6x-dis.c: Add attribution.
21 2010-10-22 Alan Modra <amodra@gmail.com>
23 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
24 * Makefile.in: Regenerate.
26 2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
28 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
29 macros before their corresponding MIPS III hardware instructions.
31 2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
33 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
35 * i386-init.h: Regenerated.
37 2010-10-15 Mike Frysinger <vapier@gentoo.org>
39 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
41 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
43 * i386-opc.tbl: Remove CheckRegSize from movq.
44 * i386-tbl.h: Regenerated.
46 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
48 * i386-opc.tbl: Remove CheckRegSize from instructions with
49 0, 1 or fixed operands.
50 * i386-tbl.h: Regenerated.
52 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
54 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
56 * i386-opc.h (CheckRegSize): New.
57 (i386_opcode_modifier): Add checkregsize.
59 * i386-opc.tbl: Add CheckRegSize to instructions which
60 require register size check.
61 * i386-tbl.h: Regenerated.
63 2010-10-12 Andreas Schwab <schwab@linux-m68k.org>
65 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
67 2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
69 * s390-opc.c: Make the instruction masks for the load/store on
70 condition instructions to cover the condition code mask as well.
71 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
73 2010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
74 Jiang Jilin <freephp@gmail.com>
76 * Makefile.am (libopcodes_a_SOURCES): New as empty.
77 * Makefile.in: Regenerate.
79 2010-10-09 Matt Rice <ratmice@gmail.com>
81 * fr30-desc.h: Regenerate.
82 * frv-desc.h: Regenerate.
83 * ip2k-desc.h: Regenerate.
84 * iq2000-desc.h: Regenerate.
85 * lm32-desc.h: Regenerate.
86 * m32c-desc.h: Regenerate.
87 * m32r-desc.h: Regenerate.
88 * mep-desc.h: Regenerate.
89 * mep-opc.c: Regenerate.
90 * mt-desc.h: Regenerate.
91 * openrisc-desc.h: Regenerate.
92 * xc16x-desc.h: Regenerate.
93 * xstormy16-desc.h: Regenerate.
95 2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
97 Fix build with -DDEBUG=7
98 * frv-opc.c: Regenerate.
99 * or32-dis.c (DEBUG): Don't redefine.
100 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
101 Adapt DEBUG code to some type changes throughout.
102 * or32-opc.c (or32_extract): Likewise.
104 2010-10-07 Bernd Schmidt <bernds@codesourcery.com>
106 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
107 in SPKERNEL instructions.
109 2010-10-02 H.J. Lu <hongjiu.lu@intel.com>
112 * i386-dis.c (RMAL): Remove duplicate.
114 2010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
116 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
117 to parse all 6 parameters.
119 2010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
121 * s390-mkopc.c (main): Change description array size to 80.
122 Add maximum length of 79 to description parsing.
124 2010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
126 * configure: Regenerate.
128 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
130 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
131 (main): Recognize the new CPU string.
132 * s390-opc.c: Add new instruction formats and masks.
133 * s390-opc.txt: Add new z196 instructions.
135 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
137 * s390-dis.c (print_insn_s390): Pick instruction with most
139 * s390-opc.c: Add unused bits to the insn mask.
140 * s390-opc.txt: Reorder some instructions to prefer more recent
143 2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
145 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
146 correction to unaligned PCs while printing comment.
148 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
150 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
151 (thumb32_opcodes): Likewise.
152 (banked_regname): New function.
153 (print_insn_arm): Add Virtualization Extensions support.
154 (print_insn_thumb32): Likewise.
156 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
158 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
161 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
163 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
164 (thumb32_opcodes): Likewise.
166 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
168 * arm-dis.c (arm_opcodes): Add support for pldw.
169 (thumb32_opcodes): Likewise.
171 2010-09-22 Robin Getz <robin.getz@analog.com>
173 * bfin-dis.c (fmtconst): Cast address to 32bits.
175 2010-09-22 Mike Frysinger <vapier@gentoo.org>
177 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
179 2010-09-22 Robin Getz <robin.getz@analog.com>
181 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
182 Reject P6/P7 to TESTSET.
183 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
185 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
186 P/D fields match all the time.
187 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
188 are 0 for accumulator compares.
189 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
190 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
191 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
192 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
193 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
194 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
196 (decode_dagMODim_0): Verify br field for IREG ops.
197 (decode_LDST_0): Reject preg load into same preg.
198 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
199 (print_insn_bfin): Likewise.
201 2010-09-22 Mike Frysinger <vapier@gentoo.org>
203 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
205 2010-09-22 Robin Getz <robin.getz@analog.com>
207 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
209 2010-09-22 Mike Frysinger <vapier@gentoo.org>
211 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
213 2010-09-22 Robin Getz <robin.getz@analog.com>
215 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
216 register values greater than 8.
217 (IS_RESERVEDREG, allreg, mostreg): New helpers.
218 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
219 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
220 (decode_CC2dreg_0): Check valid CC register number.
222 2010-09-22 Robin Getz <robin.getz@analog.com>
224 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
226 2010-09-22 Robin Getz <robin.getz@analog.com>
228 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
229 (reg_names): Likewise.
230 (decode_statbits): Likewise; while reformatting to make manageable.
232 2010-09-22 Mike Frysinger <vapier@gentoo.org>
234 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
235 (decode_pseudoOChar_0): New function.
236 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
238 2010-09-22 Robin Getz <robin.getz@analog.com>
240 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
241 LSHIFT instead of SHIFT.
243 2010-09-22 Mike Frysinger <vapier@gentoo.org>
245 * bfin-dis.c (constant_formats): Constify the whole structure.
246 (fmtconst): Add const to return value.
247 (reg_names): Mark const.
248 (decode_multfunc): Mark s0/s1 as const.
249 (decode_macfunc): Mark a/sop as const.
251 2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
253 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
255 2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
257 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
258 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
260 2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
262 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
265 2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
268 * i386-dis.c (sIv): New.
269 (dis386): Replace Iq with sIv on "pushT".
270 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
271 (x86_64_table): Replace {T|}/{P|} with P.
272 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
273 (OP_sI): Update v_mode. Remove w_mode.
275 2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
277 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
280 2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
282 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
285 2010-08-06 Quentin Neill <quentin.neill@amd.com>
287 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
288 to processor flags for PENTIUMPRO processors and later.
289 * i386-opc.h (enum): Add CpuNop.
290 (i386_cpu_flags): Add cpunop bit.
291 * i386-opc.tbl: Change nop cpu_flags.
292 * i386-init.h: Regenerated.
293 * i386-tbl.h: Likewise.
295 2010-08-06 Quentin Neill <quentin.neill@amd.com>
297 * i386-opc.h (enum): Fix typos in comments.
299 2010-08-06 Alan Modra <amodra@gmail.com>
301 * disassemble.c: Formatting.
302 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
304 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
306 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
307 * i386-tbl.h: Regenerated.
309 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
311 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
313 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
314 * i386-tbl.h: Regenerated.
316 2010-07-29 DJ Delorie <dj@redhat.com>
318 * rx-decode.opc (SRR): New.
319 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
320 r0,r0) and NOP3 (max r0,r0) special cases.
321 * rx-decode.c: Regenerate.
323 2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
325 * i386-dis.c: Add 0F to VEX opcode enums.
327 2010-07-27 DJ Delorie <dj@redhat.com>
329 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
330 (rx_decode_opcode): Likewise.
331 * rx-decode.c: Regenerate.
333 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
334 Ina Pandit <ina.pandit@kpitcummins.com>
336 * v850-dis.c (v850_sreg_names): Updated structure for system
338 (float_cc_names): new structure for condition codes.
339 (print_value): Update the function that prints value.
340 (get_operand_value): New function to get the operand value.
341 (disassemble): Updated to handle the disassembly of instructions.
342 (print_insn_v850): Updated function to print instruction for different
344 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
345 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
346 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
347 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
348 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
349 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
350 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
351 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
352 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
353 (v850_operands): Update with the relocation name. Also update
354 the instructions with specific set of processors.
356 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
358 * arm-dis.c (print_insn_arm): Add cases for printing more
360 (print_insn_thumb32): Likewise.
362 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
364 * mips-dis.c (print_insn_mips): Correct branch instruction type
367 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
369 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
370 type and delay slot determination.
371 (print_insn_mips16): Extend branch instruction type and delay
372 slot determination to cover all instructions.
373 * mips16-opc.c (BR): Remove macro.
374 (UBR, CBR): New macros.
375 (mips16_opcodes): Update branch annotation for "b", "beqz",
376 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
379 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
381 AVX Programming Reference (June, 2010)
382 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
383 * i386-opc.tbl: Likewise.
384 * i386-tbl.h: Regenerated.
386 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
388 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
390 2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
392 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
393 ppc_cpu_t before inverting.
394 (ppc_parse_cpu): Likewise.
395 (print_insn_powerpc): Likewise.
397 2010-07-03 Alan Modra <amodra@gmail.com>
399 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
400 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
401 (PPC64, MFDEC2): Update.
402 (NON32, NO371): Define.
403 (powerpc_opcode): Update to not use old opcode flags, and avoid
406 2010-07-03 DJ Delorie <dj@delorie.com>
408 * m32c-ibld.c: Regenerate.
410 2010-07-03 Alan Modra <amodra@gmail.com>
412 * ppc-opc.c (PWR2COM): Define.
413 (PPCPWR2): Add PPC_OPCODE_COMMON.
414 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
415 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
418 2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
420 AVX Programming Reference (June, 2010)
421 * i386-dis.c (PREFIX_0FAE_REG_0): New.
422 (PREFIX_0FAE_REG_1): Likewise.
423 (PREFIX_0FAE_REG_2): Likewise.
424 (PREFIX_0FAE_REG_3): Likewise.
425 (PREFIX_VEX_3813): Likewise.
426 (PREFIX_VEX_3A1D): Likewise.
427 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
428 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
430 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
431 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
432 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
434 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
435 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
436 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
438 * i386-opc.h (CpuXsaveopt): New.
439 (CpuFSGSBase): Likewise.
440 (CpuRdRnd): Likewise.
442 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
445 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
446 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
447 * i386-init.h: Regenerated.
448 * i386-tbl.h: Likewise.
450 2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
452 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
455 2010-06-29 Alan Modra <amodra@gmail.com>
457 * maxq-dis.c: Delete file.
458 * Makefile.am: Remove references to maxq.
459 * configure.in: Likewise.
460 * disassemble.c: Likewise.
461 * Makefile.in: Regenerate.
462 * configure: Regenerate.
463 * po/POTFILES.in: Regenerate.
465 2010-06-29 Alan Modra <amodra@gmail.com>
467 * mep-dis.c: Regenerate.
469 2010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
471 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
473 2010-06-27 Alan Modra <amodra@gmail.com>
475 * arc-dis.c (arc_sprintf): Delete set but unused variables.
476 (decodeInstr): Likewise.
477 * dlx-dis.c (print_insn_dlx): Likewise.
478 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
479 * maxq-dis.c (check_move, print_insn): Likewise.
480 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
481 * msp430-dis.c (msp430_branchinstr): Likewise.
482 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
483 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
484 * sparc-dis.c (print_insn_sparc): Likewise.
485 * fr30-asm.c: Regenerate.
486 * frv-asm.c: Regenerate.
487 * ip2k-asm.c: Regenerate.
488 * iq2000-asm.c: Regenerate.
489 * lm32-asm.c: Regenerate.
490 * m32c-asm.c: Regenerate.
491 * m32r-asm.c: Regenerate.
492 * mep-asm.c: Regenerate.
493 * mt-asm.c: Regenerate.
494 * openrisc-asm.c: Regenerate.
495 * xc16x-asm.c: Regenerate.
496 * xstormy16-asm.c: Regenerate.
498 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
501 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
503 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
506 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
508 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
510 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
511 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
512 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
513 touch floating point regs and are enabled by COM, PPC or PPCCOM.
514 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
515 Treat lwsync as msync on e500.
517 2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
519 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
521 2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
523 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
524 constants is the same on 32-bit and 64-bit hosts.
526 2010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
528 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
529 .short directives so that they can be reassembled.
531 2010-05-26 Catherine Moore <clm@codesourcery.com>
532 David Ung <davidu@mips.com>
534 * mips-opc.c: Change membership to I1 for instructions ssnop and
537 2010-05-26 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-dis.c (sib): New.
541 (print_insn): Call get_sib.
542 OP_E_memory): Use sib.
544 2010-05-26 Catherine Moore <clm@codesoourcery.com>
546 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
547 * mips-opc.c (I16): Remove.
548 (mips_builtin_op): Reclassify jalx.
550 2010-05-19 Alan Modra <amodra@gmail.com>
552 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
553 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
555 2010-05-13 Alan Modra <amodra@gmail.com>
557 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
559 2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
561 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
563 (print_insn_thumb16): Add support for new %W format.
565 2010-05-07 Tristan Gingold <gingold@adacore.com>
567 * Makefile.in: Regenerate with automake 1.11.1.
570 2010-05-05 Nick Clifton <nickc@redhat.com>
572 * po/es.po: Updated Spanish translation.
574 2010-04-22 Nick Clifton <nickc@redhat.com>
576 * po/opcodes.pot: Updated by the Translation project.
577 * po/vi.po: Updated Vietnamese translation.
579 2010-04-16 H.J. Lu <hongjiu.lu@intel.com>
581 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
584 2010-04-09 Nick Clifton <nickc@redhat.com>
586 * i386-dis.c (print_insn): Remove unused variable op.
587 (OP_sI): Remove unused variable mask.
589 2010-04-07 Alan Modra <amodra@gmail.com>
591 * configure: Regenerate.
593 2010-04-06 Peter Bergner <bergner@vnet.ibm.com>
595 * ppc-opc.c (RBOPT): New define.
596 ("dccci"): Enable for PPCA2. Make operands optional.
597 ("iccci"): Likewise. Do not deprecate for PPC476.
599 2010-04-02 Masaki Muranaka <monaka@monami-software.com>
601 * cr16-opc.c (cr16_instruction): Fix typo in comment.
603 2010-03-25 Joseph Myers <joseph@codesourcery.com>
605 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
606 * Makefile.in: Regenerate.
607 * configure.in (bfd_tic6x_arch): New.
608 * configure: Regenerate.
609 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
610 (disassembler): Handle TI C6X.
613 2010-03-24 Mike Frysinger <vapier@gentoo.org>
615 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
617 2010-03-23 Joseph Myers <joseph@codesourcery.com>
619 * dis-buf.c (buffer_read_memory): Give error for reading just
620 before the start of memory.
622 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
623 Quentin Neill <quentin.neill@amd.com>
625 * i386-dis.c (OP_LWP_I): Removed.
626 (reg_table): Do not use OP_LWP_I, use Iq.
627 (OP_LWPCB_E): Remove use of names16.
629 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
630 should not set the Vex.length bit.
631 * i386-tbl.h: Regenerated.
633 2010-02-25 Edmar Wienskoski <edmar@freescale.com>
635 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
637 2010-02-24 Nick Clifton <nickc@redhat.com>
640 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
641 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
642 (thumb32_opcodes): Likewise.
644 2010-02-15 Nick Clifton <nickc@redhat.com>
646 * po/vi.po: Updated Vietnamese translation.
648 2010-02-12 Doug Evans <dje@sebabeach.org>
650 * lm32-opinst.c: Regenerate.
652 2010-02-11 Doug Evans <dje@sebabeach.org>
654 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
655 (print_address): Delete CGEN_PRINT_ADDRESS.
656 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
657 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
658 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
659 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
661 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
662 * frv-desc.c, * frv-desc.h, * frv-opc.c,
663 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
664 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
665 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
666 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
667 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
668 * mep-desc.c, * mep-desc.h, * mep-opc.c,
669 * mt-desc.c, * mt-desc.h, * mt-opc.c,
670 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
671 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
672 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
674 2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
676 * i386-dis.c: Update copyright.
677 * i386-gen.c: Likewise.
678 * i386-opc.h: Likewise.
679 * i386-opc.tbl: Likewise.
681 2010-02-10 Quentin Neill <quentin.neill@amd.com>
682 Sebastian Pop <sebastian.pop@amd.com>
684 * i386-dis.c (OP_EX_VexImmW): Reintroduced
685 function to handle 5th imm8 operand.
686 (PREFIX_VEX_3A48): Added.
687 (PREFIX_VEX_3A49): Added.
688 (VEX_W_3A48_P_2): Added.
689 (VEX_W_3A49_P_2): Added.
690 (prefix table): Added entries for PREFIX_VEX_3A48
692 (vex table): Added entries for VEX_W_3A48_P_2 and
694 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
695 for Vec_Imm4 operands.
696 * i386-opc.h (enum): Added Vec_Imm4.
697 (i386_operand_type): Added vec_imm4.
698 * i386-opc.tbl: Add entries for vpermilp[ds].
699 * i386-init.h: Regenerated.
700 * i386-tbl.h: Regenerated.
702 2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
704 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
705 and "pwr7". Move "a2" into alphabetical order.
707 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
709 * ppc-dis.c (ppc_opts): Add titan entry.
710 * ppc-opc.c (TITAN, MULHW): Define.
711 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
713 2010-02-03 Quentin Neill <quentin.neill@amd.com>
715 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
717 * i386-init.h: Regenerated.
719 2010-02-03 Anthony Green <green@moxielogic.com>
721 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
722 0x0f, and make 0x00 an illegal instruction.
724 2010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
726 * opcodes/arm-dis.c (struct arm_private_data): New.
727 (print_insn_coprocessor, print_insn_arm): Update to use struct
729 (is_mapping_symbol, get_map_sym_type): New functions.
730 (get_sym_code_type): Check the symbol's section. Do not check
732 (print_insn): Default to disassembling ARM mode code. Check
733 for mapping symbols separately from other symbols. Use
734 struct arm_private_data.
736 2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
738 * i386-dis.c (EXVexWdqScalar): New.
739 (vex_scalar_w_dq_mode): Likewise.
740 (prefix_table): Update entries for PREFIX_VEX_3899,
741 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
742 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
743 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
744 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
745 (intel_operand_size): Handle vex_scalar_w_dq_mode.
748 2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
750 * i386-dis.c (XMScalar): New.
751 (EXdScalar): Likewise.
752 (EXqScalar): Likewise.
753 (EXqScalarS): Likewise.
754 (VexScalar): Likewise.
755 (EXdVexScalarS): Likewise.
756 (EXqVexScalarS): Likewise.
757 (XMVexScalar): Likewise.
758 (scalar_mode): Likewise.
759 (d_scalar_mode): Likewise.
760 (d_scalar_swap_mode): Likewise.
761 (q_scalar_mode): Likewise.
762 (q_scalar_swap_mode): Likewise.
763 (vex_scalar_mode): Likewise.
764 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
765 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
766 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
767 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
768 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
769 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
770 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
771 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
772 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
773 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
774 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
775 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
776 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
777 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
778 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
779 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
780 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
781 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
782 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
783 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
784 q_scalar_mode, q_scalar_swap_mode.
785 (OP_XMM): Handle scalar_mode.
786 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
787 and q_scalar_swap_mode.
788 (OP_VEX): Handle vex_scalar_mode.
790 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
794 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
796 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
798 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
800 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
802 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
804 * i386-dis.c (Bad_Opcode): New.
805 (bad_opcode): Likewise.
806 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
807 (dis386_twobyte): Likewise.
808 (reg_table): Likewise.
809 (prefix_table): Likewise.
810 (x86_64_table): Likewise.
811 (vex_len_table): Likewise.
812 (vex_w_table): Likewise.
813 (mod_table): Likewise.
814 (rm_table): Likewise.
815 (float_reg): Likewise.
816 (reg_table): Remove trailing "(bad)" entries.
817 (prefix_table): Likewise.
818 (x86_64_table): Likewise.
819 (vex_len_table): Likewise.
820 (vex_w_table): Likewise.
821 (mod_table): Likewise.
822 (rm_table): Likewise.
823 (get_valid_dis386): Handle bytemode 0.
825 2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
827 * i386-opc.h (VEXScalar): New.
829 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
831 * i386-tbl.h: Regenerated.
833 2010-01-21 H.J. Lu <hongjiu.lu@intel.com>
835 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
837 * i386-opc.tbl: Add xsave64 and xrstor64.
838 * i386-tbl.h: Regenerated.
840 2010-01-20 Nick Clifton <nickc@redhat.com>
843 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
844 based post-indexed addressing.
846 2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
848 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
849 * i386-tbl.h: Regenerated.
851 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
853 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
856 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
858 * i386-dis.c (names_mm): New.
859 (intel_names_mm): Likewise.
860 (att_names_mm): Likewise.
861 (names_xmm): Likewise.
862 (intel_names_xmm): Likewise.
863 (att_names_xmm): Likewise.
864 (names_ymm): Likewise.
865 (intel_names_ymm): Likewise.
866 (att_names_ymm): Likewise.
867 (print_insn): Set names_mm, names_xmm and names_ymm.
868 (OP_MMX): Use names_mm, names_xmm and names_ymm.
874 (XMM_Fixup): Likewise.
876 (OP_EX_VexReg): Likewise.
877 (OP_Vex_2src): Likewise.
878 (OP_Vex_2src_1): Likewise.
879 (OP_Vex_2src_2): Likewise.
880 (OP_REG_VexI4): Likewise.
882 2010-01-13 H.J. Lu <hongjiu.lu@intel.com>
884 * i386-dis.c (print_insn): Update comments.
886 2010-01-12 H.J. Lu <hongjiu.lu@intel.com>
888 * i386-dis.c (rex_original): Removed.
889 (ckprefix): Remove rex_original.
890 (print_insn): Update comments.
892 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
894 * Makefile.in: Regenerate.
895 * configure: Regenerate.
897 2010-01-07 Doug Evans <dje@sebabeach.org>
899 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
900 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
901 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
902 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
903 * xstormy16-ibld.c: Regenerate.
905 2010-01-06 Quentin Neill <quentin.neill@amd.com>
907 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
908 * i386-init.h: Regenerated.
910 2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
912 * arm-dis.c (print_insn): Fixed search for next symbol and data
913 dumping condition, and the initial mapping symbol state.
915 2010-01-05 Doug Evans <dje@sebabeach.org>
917 * cgen-ibld.in: #include "cgen/basic-modes.h".
918 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
919 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
920 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
921 * xstormy16-ibld.c: Regenerate.
923 2010-01-04 Nick Clifton <nickc@redhat.com>
926 * arm-dis.c (print_insn_coprocessor): Initialise value.
928 2010-01-04 Edmar Wienskoski <edmar@freescale.com>
930 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
932 2010-01-02 Doug Evans <dje@sebabeach.org>
934 * cgen-asm.in: Update copyright year.
935 * cgen-dis.in: Update copyright year.
936 * cgen-ibld.in: Update copyright year.
937 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
938 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
939 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
940 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
941 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
942 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
943 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
944 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
945 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
946 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
947 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
948 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
949 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
950 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
951 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
952 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
953 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
954 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
955 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
956 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
957 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
959 For older changes see ChangeLog-2009
965 version-control: never