opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
   4         (SIGNBIT): New.
   5         (MASKBITS, SIGNEXTEND): Rewrite.
   6         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
   7         unsigned arithmetic, instead assign result of SIGNEXTEND back
   8         to x.
   9         (fmtconst_val): Use 1u in shift expression.
  10
  11 2019-12-11  Alan Modra  <amodra@gmail.com>
  12
  13         * arc-dis.c (find_format_from_table): Use ull constant when
  14         shifting by up to 32.
  15
  16 2019-12-11  Alan Modra  <amodra@gmail.com>
  17
  18         PR 25270
  19         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  20         false when field is zero for sve_size_tsz_bhs.
  21
  22 2019-12-11  Alan Modra  <amodra@gmail.com>
  23
  24         * epiphany-ibld.c: Regenerate.
  25
  26 2019-12-10  Alan Modra  <amodra@gmail.com>
  27
  28         PR 24960
  29         * disassemble.c (disassemble_free_target): New function.
  30
  31 2019-12-10  Alan Modra  <amodra@gmail.com>
  32
  33         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
  34         * disassemble.c (disassemble_init_for_target): Likewise.
  35         * bpf-dis.c: Regenerate.
  36         * epiphany-dis.c: Regenerate.
  37         * fr30-dis.c: Regenerate.
  38         * frv-dis.c: Regenerate.
  39         * ip2k-dis.c: Regenerate.
  40         * iq2000-dis.c: Regenerate.
  41         * lm32-dis.c: Regenerate.
  42         * m32c-dis.c: Regenerate.
  43         * m32r-dis.c: Regenerate.
  44         * mep-dis.c: Regenerate.
  45         * mt-dis.c: Regenerate.
  46         * or1k-dis.c: Regenerate.
  47         * xc16x-dis.c: Regenerate.
  48         * xstormy16-dis.c: Regenerate.
  49
  50 2019-12-10  Alan Modra  <amodra@gmail.com>
  51
  52         * ppc-dis.c (private): Delete variable.
  53         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
  54         (powerpc_init_dialect): Don't use global private.
  55
  56 2019-12-10  Alan Modra  <amodra@gmail.com>
  57
  58         * s12z-opc.c: Formatting.
  59
  60 2019-12-08  Alan Modra  <amodra@gmail.com>
  61
  62         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
  63         registers.
  64
  65 2019-12-05  Jan Beulich  <jbeulich@suse.com>
  66
  67         * aarch64-tbl.h (aarch64_feature_crypto,
  68         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
  69         CRYPTO_V8_2_INSN): Delete.
  70
  71 2019-12-05  Alan Modra  <amodra@gmail.com>
  72
  73         PR 25249
  74         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
  75         (struct string_buf): New.
  76         (strbuf): New function.
  77         (get_field): Use strbuf rather than strdup of local temp.
  78         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
  79         (get_field_rfsl, get_field_imm15): Likewise.
  80         (get_field_rd, get_field_r1, get_field_r2): Update macros.
  81         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
  82         (print_insn_microblaze): Formatting.  Init and pass string_buf to
  83         get_field functions.
  84
  85 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
  88         * i386-tbl.h: Re-generate.
  89
  90 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
  93
  94 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
  97         forms.
  98         (xbegin): Drop DefaultSize.
  99         * i386-tbl.h: Re-generate.
 100
 101 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 102
 103         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 104         Change the coproc CRC conditions to use the extension
 105         feature set, second word, base on ARM_EXT2_CRC.
 106
 107 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 110         * i386-tbl.h: Re-generate.
 111
 112 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 115         JumpInterSegment, and JumpAbsolute entries.
 116         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 117         JUMP_ABSOLUTE): Define.
 118         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 119         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 120         fields.
 121         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 122         JumpInterSegment): Define.
 123         * i386-tbl.h: Re-generate.
 124
 125 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-gen.c (operand_type_init): Remove
 128         OPERAND_TYPE_JUMPABSOLUTE entry.
 129         (opcode_modifiers): Add JumpAbsolute entry.
 130         (operand_types): Remove JumpAbsolute entry.
 131         * i386-opc.h (JumpAbsolute): Move between enums.
 132         (struct i386_opcode_modifier): Add jumpabsolute field.
 133         (union i386_operand_type): Remove jumpabsolute field.
 134         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 135         * i386-init.h, i386-tbl.h: Re-generate.
 136
 137 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 140         (operand_types): Remove AnySize entry.
 141         * i386-opc.h (AnySize): Move between enums.
 142         (struct i386_opcode_modifier): Add anysize field.
 143         (OTUnused): Un-comment.
 144         (union i386_operand_type): Remove anysize field.
 145         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 146         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 147         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 148         AnySize.
 149         * i386-tbl.h: Re-generate.
 150
 151 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 152
 153         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 154         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 155         use the floating point register (FPR).
 156
 157 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 158
 159         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 160         cmode 1101.
 161         (is_mve_encoding_conflict): Update cmode conflict checks for
 162         MVE_VMVN_IMM.
 163
 164 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 167         entry.
 168         (operand_types): Remove EsSeg entry.
 169         (main): Replace stale use of OTMax.
 170         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 171         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 172         (EsSeg): Delete.
 173         (OTUnused): Comment out.
 174         (union i386_operand_type): Remove esseg field.
 175         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 176         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 177         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 178         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 179         * i386-init.h, i386-tbl.h: Re-generate.
 180
 181 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-gen.c (operand_instances): Add RegB entry.
 184         * i386-opc.h (enum operand_instance): Add RegB.
 185         * i386-opc.tbl (RegC, RegD, RegB): Define.
 186         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 187         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 188         monitorx, mwaitx): Drop ImmExt and convert encodings
 189         accordingly.
 190         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 191         (edx, rdx): Add Instance=RegD.
 192         (ebx, rbx): Add Instance=RegB.
 193         * i386-tbl.h: Re-generate.
 194
 195 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-gen.c (operand_type_init): Adjust
 198         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 199         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 200         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 201         (operand_instances): New.
 202         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 203         (output_operand_type): New parameter "instance". Process it.
 204         (process_i386_operand_type): New local variable "instance".
 205         (main): Adjust static assertions.
 206         * i386-opc.h (INSTANCE_WIDTH): Define.
 207         (enum operand_instance): New.
 208         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 209         (union i386_operand_type): Replace acc, inoutportreg, and
 210         shiftcount by instance.
 211         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 212         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 213         Add Instance=.
 214         * i386-init.h, i386-tbl.h: Re-generate.
 215
 216 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 217
 218         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 219         smaxp/sminp entries' "tied_operand" field to 2.
 220
 221 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 222
 223         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 224         "index" local variable by that of the already existing "num".
 225
 226 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         PR gas/25167
 229         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 230         * i386-tbl.h: Regenerated.
 231
 232 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-gen.c (operand_type_init): Add Class= to
 235         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 236         OPERAND_TYPE_REGBND entry.
 237         (operand_classes): Add RegMask and RegBND entries.
 238         (operand_types): Drop RegMask and RegBND entry.
 239         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 240         (RegMask, RegBND): Delete.
 241         (union i386_operand_type): Remove regmask and regbnd fields.
 242         * i386-opc.tbl (RegMask, RegBND): Define.
 243         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 244         Class=RegBND.
 245         * i386-init.h, i386-tbl.h: Re-generate.
 246
 247 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-gen.c (operand_type_init): Add Class= to
 250         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 251         OPERAND_TYPE_REGZMM entries.
 252         (operand_classes): Add RegMMX and RegSIMD entries.
 253         (operand_types): Drop RegMMX and RegSIMD entries.
 254         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 255         (RegMMX, RegSIMD): Delete.
 256         (union i386_operand_type): Remove regmmx and regsimd fields.
 257         * i386-opc.tbl (RegMMX): Define.
 258         (RegXMM, RegYMM, RegZMM): Add Class=.
 259         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 260         Class=RegSIMD.
 261         * i386-init.h, i386-tbl.h: Re-generate.
 262
 263 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-gen.c (operand_type_init): Add Class= to
 266         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 267         entries.
 268         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 269         (operand_types): Drop Control, Debug, and Test entries.
 270         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 271         (Control, Debug, Test): Delete.
 272         (union i386_operand_type): Remove control, debug, and test
 273         fields.
 274         * i386-opc.tbl (Control, Debug, Test): Define.
 275         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 276         Class=RegDR, and Test by Class=RegTR.
 277         * i386-init.h, i386-tbl.h: Re-generate.
 278
 279 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-gen.c (operand_type_init): Add Class= to
 282         OPERAND_TYPE_SREG entry.
 283         (operand_classes): Add SReg entry.
 284         (operand_types): Drop SReg entry.
 285         * i386-opc.h (enum operand_class): Add SReg.
 286         (SReg): Delete.
 287         (union i386_operand_type): Remove sreg field.
 288         * i386-opc.tbl (SReg): Define.
 289         * i386-reg.tbl: Replace SReg by Class=SReg.
 290         * i386-init.h, i386-tbl.h: Re-generate.
 291
 292 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-gen.c (operand_type_init): Add Class=. New
 295         OPERAND_TYPE_ANYIMM entry.
 296         (operand_classes): New.
 297         (operand_types): Drop Reg entry.
 298         (output_operand_type): New parameter "class". Process it.
 299         (process_i386_operand_type): New local variable "class".
 300         (main): Adjust static assertions.
 301         * i386-opc.h (CLASS_WIDTH): Define.
 302         (enum operand_class): New.
 303         (Reg): Replace by Class. Adjust comment.
 304         (union i386_operand_type): Replace reg by class.
 305         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 306         Class=.
 307         * i386-reg.tbl: Replace Reg by Class=Reg.
 308         * i386-init.h: Re-generate.
 309
 310 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 311
 312         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 313         (aarch64_opcode_table): Add data gathering hint mnemonic.
 314         * opcodes/aarch64-dis-2.c: Account for new instruction.
 315
 316 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 317
 318         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 319
 320
 321 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 322
 323         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 324         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 325         aarch64_feature_f64mm): New feature sets.
 326         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 327         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 328         instructions.
 329         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 330         macros.
 331         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 332         (OP_SVE_QQQ): New qualifier.
 333         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 334         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 335         the movprfx constraint.
 336         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 337         (aarch64_opcode_table): Define new instructions smmla,
 338         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 339         uzip{1/2}, trn{1/2}.
 340         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 341         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 342         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 343         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 344         Account for new instructions.
 345         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 346         S4x32 operand.
 347         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 348
 349 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 350 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 351
 352         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 353         Armv8.6-A.
 354         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 355         (neon_opcodes): Add bfloat SIMD instructions.
 356         (print_insn_coprocessor): Add new control character %b to print
 357         condition code without checking cp_num.
 358         (print_insn_neon): Account for BFloat16 instructions that have no
 359         special top-byte handling.
 360
 361 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 362 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 363
 364         * arm-dis.c (print_insn_coprocessor,
 365         print_insn_generic_coprocessor): Create wrapper functions around
 366         the implementation of the print_insn_coprocessor control codes.
 367         (print_insn_coprocessor_1): Original print_insn_coprocessor
 368         function that now takes which array to look at as an argument.
 369         (print_insn_arm): Use both print_insn_coprocessor and
 370         print_insn_generic_coprocessor.
 371         (print_insn_thumb32): As above.
 372
 373 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 374 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 375
 376         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 377         in reglane special case.
 378         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 379         aarch64_find_next_opcode): Account for new instructions.
 380         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 381         in reglane special case.
 382         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 383         new AARCH64_OPND_QLF_S_2H qualifier.
 384         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 385         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 386         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 387         sets.
 388         (BFLOAT_SVE, BFLOAT): New feature set macros.
 389         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 390         instructions.
 391         (aarch64_opcode_table): Define new instructions bfdot,
 392         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 393         bfcvtn2, bfcvt.
 394
 395 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 396 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 397
 398         * aarch64-tbl.h (ARMV8_6): New macro.
 399
 400 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-dis.c (prefix_table): Add mcommit.
 403         (rm_table): Add rdpru.
 404         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 405         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 406         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 407         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 408         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 409         * i386-opc.tbl (mcommit, rdpru): New.
 410         * i386-init.h, i386-tbl.h: Re-generate.
 411
 412 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 415         "names32" instead.
 416         (OP_Monitor): Drop local variable "op1_names", re-purpose
 417         "names" for it instead, and replace former "names" uses by
 418         "names32" ones.
 419
 420 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 421
 422         PR/gas 25167
 423         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 424         operand-less forms.
 425         * opcodes/i386-tbl.h: Re-generate.
 426
 427 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-dis.c (OP_Mwaitx): Delete.
 430         (prefix_table): Use OP_Mwait for mwaitx entry.
 431         (OP_Mwait): Also handle mwaitx.
 432
 433 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 434
 435         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 436         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 437         (prefix_table): Add respective entries.
 438         (rm_table): Link to those entries.
 439
 440 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 443         (REG_0F1C_P_0_MOD_0): ... this.
 444         (REG_0F1E_MOD_3): Rename to ...
 445         (REG_0F1E_P_1_MOD_3): ... this.
 446         (RM_0F01_REG_5): Rename to ...
 447         (RM_0F01_REG_5_MOD_3): ... this.
 448         (RM_0F01_REG_7): Rename to ...
 449         (RM_0F01_REG_7_MOD_3): ... this.
 450         (RM_0F1E_MOD_3_REG_7): Rename to ...
 451         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 452         (RM_0FAE_REG_6): Rename to ...
 453         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 454         (RM_0FAE_REG_7): Rename to ...
 455         (RM_0FAE_REG_7_MOD_3): ... this.
 456         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 457         (PREFIX_0F01_REG_5_MOD_0): ... this.
 458         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 459         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 460         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 461         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 462         (PREFIX_0FAE_REG_0): Rename to ...
 463         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 464         (PREFIX_0FAE_REG_1): Rename to ...
 465         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 466         (PREFIX_0FAE_REG_2): Rename to ...
 467         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 468         (PREFIX_0FAE_REG_3): Rename to ...
 469         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 470         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 471         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 472         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 473         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 474         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 475         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 476         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 477         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 478         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 479         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 480         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 481         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 482         (PREFIX_0FAE_REG_7): Rename to ...
 483         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 484         (PREFIX_MOD_0_0FC3): Rename to ...
 485         (PREFIX_0FC3_MOD_0): ... this.
 486         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 487         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 488         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 489         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 490         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 491         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 492         (reg_table, prefix_table, mod_table, rm_table): Adjust
 493         accordingly.
 494
 495 2019-11-04  Nick Clifton  <nickc@redhat.com>
 496
 497         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 498         of a v850 system register.  Move the v850_sreg_names array into
 499         this function.
 500         (get_v850_reg_name): Likewise for ordinary register names.
 501         (get_v850_vreg_name): Likewise for vector register names.
 502         (get_v850_cc_name): Likewise for condition codes.
 503         * get_v850_float_cc_name): Likewise for floating point condition
 504         codes.
 505         (get_v850_cacheop_name): Likewise for cache-ops.
 506         (get_v850_prefop_name): Likewise for pref-ops.
 507         (disassemble): Use the new accessor functions.
 508
 509 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 510
 511         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 512         immediate for the writeback form of ldraa/ldrab if it is 0.
 513         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 514         * aarch64-opc-2.c: Regenerated.
 515
 516 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-gen.c (operand_type_shorthands): Delete.
 519         (operand_type_init): Expand previous shorthands.
 520         (set_bitfield_from_shorthand): Rename back to ...
 521         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 522         of operand_type_init[].
 523         (set_bitfield): Adjust call to the above function.
 524         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 525         RegXMM, RegYMM, RegZMM): Define.
 526         * i386-reg.tbl: Expand prior shorthands.
 527
 528 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-gen.c (output_i386_opcode): Change order of fields
 531         emitted to output.
 532         * i386-opc.h (struct insn_template): Move operands field.
 533         Convert extension_opcode field to unsigned short.
 534         * i386-tbl.h: Re-generate.
 535
 536 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 539         of W.
 540         * i386-opc.h (W): Extend comment.
 541         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 542         general purpose variants not allowing for byte operands.
 543         * i386-tbl.h: Re-generate.
 544
 545 2019-10-29  Nick Clifton  <nickc@redhat.com>
 546
 547         * tic30-dis.c (print_branch): Correct size of operand array.
 548
 549 2019-10-29  Nick Clifton  <nickc@redhat.com>
 550
 551         * d30v-dis.c (print_insn): Check that operand index is valid
 552         before attempting to access the operands array.
 553
 554 2019-10-29  Nick Clifton  <nickc@redhat.com>
 555
 556         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 557         locating the bit to be tested.
 558
 559 2019-10-29  Nick Clifton  <nickc@redhat.com>
 560
 561         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 562         values.
 563         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 564         (print_insn_s12z):  Check for illegal size values.
 565
 566 2019-10-28  Nick Clifton  <nickc@redhat.com>
 567
 568         * csky-dis.c (csky_chars_to_number): Check for a negative
 569         count. Use an unsigned integer to construct the return value.
 570
 571 2019-10-28  Nick Clifton  <nickc@redhat.com>
 572
 573         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 574         operand buffer.  Set value to 15 not 13.
 575         (get_register_operand): Use OPERAND_BUFFER_LEN.
 576         (get_indirect_operand): Likewise.
 577         (print_two_operand): Likewise.
 578         (print_three_operand): Likewise.
 579         (print_oar_insn): Likewise.
 580
 581 2019-10-28  Nick Clifton  <nickc@redhat.com>
 582
 583         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 584         (bit_extract_simple): Likewise.
 585         (bit_copy): Likewise.
 586         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 587         index_offset array are not accessed.
 588
 589 2019-10-28  Nick Clifton  <nickc@redhat.com>
 590
 591         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 592         operand.
 593
 594 2019-10-25  Nick Clifton  <nickc@redhat.com>
 595
 596         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 597         access to opcodes.op array element.
 598
 599 2019-10-23  Nick Clifton  <nickc@redhat.com>
 600
 601         * rx-dis.c (get_register_name): Fix spelling typo in error
 602         message.
 603         (get_condition_name, get_flag_name, get_double_register_name)
 604         (get_double_register_high_name, get_double_register_low_name)
 605         (get_double_control_register_name, get_double_condition_name)
 606         (get_opsize_name, get_size_name): Likewise.
 607
 608 2019-10-22  Nick Clifton  <nickc@redhat.com>
 609
 610         * rx-dis.c (get_size_name): New function.  Provides safe
 611         access to name array.
 612         (get_opsize_name): Likewise.
 613         (print_insn_rx): Use the accessor functions.
 614
 615 2019-10-16  Nick Clifton  <nickc@redhat.com>
 616
 617         * rx-dis.c (get_register_name): New function.  Provides safe
 618         access to name array.
 619         (get_condition_name, get_flag_name, get_double_register_name)
 620         (get_double_register_high_name, get_double_register_low_name)
 621         (get_double_control_register_name, get_double_condition_name):
 622         Likewise.
 623         (print_insn_rx): Use the accessor functions.
 624
 625 2019-10-09  Nick Clifton  <nickc@redhat.com>
 626
 627         PR 25041
 628         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 629         instructions.
 630
 631 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 632
 633         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 634         (cmpsd): Likewise. Move EsSeg to other operand.
 635         * opcodes/i386-tbl.h: Re-generate.
 636
 637 2019-09-23  Alan Modra  <amodra@gmail.com>
 638
 639         * m68k-dis.c: Include cpu-m68k.h
 640
 641 2019-09-23  Alan Modra  <amodra@gmail.com>
 642
 643         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 644         "elf/mips.h" earlier.
 645
 646 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 647
 648         PR gas/25012
 649         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 650         with SReg operand.
 651         * i386-tbl.h: Re-generate.
 652
 653 2019-09-18  Alan Modra  <amodra@gmail.com>
 654
 655         * arc-ext.c: Update throughout for bfd section macro changes.
 656
 657 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 658
 659         * Makefile.in: Re-generate.
 660         * configure: Re-generate.
 661
 662 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 663
 664         * riscv-opc.c (riscv_opcodes): Change subset field
 665         to insn_class field for all instructions.
 666         (riscv_insn_types): Likewise.
 667
 668 2019-09-16  Phil Blundell  <pb@pbcl.net>
 669
 670         * configure: Regenerated.
 671
 672 2019-09-10  Miod Vallat  <miod@online.fr>
 673
 674         PR 24982
 675         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 676
 677 2019-09-09  Phil Blundell  <pb@pbcl.net>
 678
 679         binutils 2.33 branch created.
 680
 681 2019-09-03  Nick Clifton  <nickc@redhat.com>
 682
 683         PR 24961
 684         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 685         greater than zero before indexing via (bufcnt -1).
 686
 687 2019-09-03  Nick Clifton  <nickc@redhat.com>
 688
 689         PR 24958
 690         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 691         (MAX_SPEC_REG_NAME_LEN): Define.
 692         (struct mmix_dis_info): Use defined constants for array lengths.
 693         (get_reg_name): New function.
 694         (get_sprec_reg_name): New function.
 695         (print_insn_mmix): Use new functions.
 696
 697 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 698
 699         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 700         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 701         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 702
 703 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 704
 705         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 706         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 707         (aarch64_sys_reg_supported_p): Update checks for the above.
 708
 709 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 710
 711         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 712         cases MVE_SQRSHRL and MVE_UQRSHLL.
 713         (print_insn_mve): Add case for specifier 'k' to check
 714         specific bit of the instruction.
 715
 716 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 717
 718         PR 24854
 719         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 720         encountering an unknown machine type.
 721         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 722         cases return -1 rather than calling abort.
 723
 724 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 725
 726         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 727         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 728         IgnoreSize.
 729         * i386-tbl.h: Re-generate.
 730
 731 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 732
 733         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 734         instructions.
 735
 736 2019-07-30  Mel Chen <mel.chen@sifive.com>
 737
 738         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 739         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 740
 741         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 742         fscsr.
 743
 744 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 745
 746         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 747         and MPY class instructions.
 748         (parse_option): Add nps400 option.
 749         (print_arc_disassembler_options): Add nps400 info.
 750
 751 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 752
 753         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 754         (bspop): Likewise.
 755         (modapp): Likewise.
 756         * arc-opc.c (RAD_CHK): Add.
 757         * arc-tbl.h: Regenerate.
 758
 759 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 760
 761         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 762         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 763
 764 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 765
 766         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 767         instructions as UNPREDICTABLE.
 768
 769 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 770
 771         * bpf-desc.c: Regenerated.
 772
 773 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 774
 775         * i386-gen.c (static_assert): Define.
 776         (main): Use it.
 777         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 778         (Opcode_Modifier_Num): ... this.
 779         (Mem): Delete.
 780
 781 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-gen.c (operand_types): Move RegMem ...
 784         (opcode_modifiers): ... here.
 785         * i386-opc.h (RegMem): Move to opcode modifer enum.
 786         (union i386_operand_type): Move regmem field ...
 787         (struct i386_opcode_modifier): ... here.
 788         * i386-opc.tbl (RegMem): Define.
 789         (mov, movq): Move RegMem on segment, control, debug, and test
 790         register flavors.
 791         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 792         to non-SSE2AVX flavor.
 793         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 794         Move RegMem on register only flavors. Drop IgnoreSize from
 795         legacy encoding flavors.
 796         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 797         flavors.
 798         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 799         register only flavors.
 800         (vmovd): Move RegMem and drop IgnoreSize on register only
 801         flavor. Change opcode and operand order to store form.
 802         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 803
 804 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 807         entries.
 808         * i386-opc.h (SReg2, SReg3): Replace by ...
 809         (SReg): ... this.
 810         (union i386_operand_type): Replace sreg fields.
 811         * i386-opc.tbl (mov, ): Use SReg.
 812         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 813         register flavors.
 814         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 815         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 816
 817 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 818
 819         * bpf-desc.c: Regenerate.
 820         * bpf-opc.c: Likewise.
 821         * bpf-opc.h: Likewise.
 822
 823 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 824
 825         * bpf-desc.c: Regenerate.
 826         * bpf-opc.c: Likewise.
 827
 828 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 829
 830         * arm-dis.c (print_insn_coprocessor): Rename index to
 831         index_operand.
 832
 833 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 834
 835         * riscv-opc.c (riscv_insn_types): Add r4 type.
 836
 837         * riscv-opc.c (riscv_insn_types): Add b and j type.
 838
 839         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 840         format for sb type and correct s type.
 841
 842 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 843
 844         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 845         SVE FMOV alias of FCPY.
 846
 847 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 848
 849         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 850         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 851
 852 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 855         registers in an instruction prefixed by MOVPRFX.
 856
 857 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 858
 859         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 860         sve_size_13 icode to account for variant behaviour of
 861         pmull{t,b}.
 862         * aarch64-dis-2.c: Regenerate.
 863         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 864         sve_size_13 icode to account for variant behaviour of
 865         pmull{t,b}.
 866         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 867         (OP_SVE_VVV_Q_D): Add new qualifier.
 868         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 869         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 870         AES and those not.
 871
 872 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 873
 874         * opcodes/i386-gen.c (operand_type_init): Remove
 875         OPERAND_TYPE_VEC_IMM4 entry.
 876         (operand_types): Remove Vec_Imm4.
 877         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 878         (union i386_operand_type): Remove vec_imm4.
 879         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 880         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 881
 882 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 885         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 886         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 887         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 888         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 889         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 890         * i386-tbl.h: Re-generate.
 891
 892 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 893
 894         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 895         register operands.
 896         * i386-tbl.h: Re-generate.
 897
 898 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-opc.tbl (C): New.
 901         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 902         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 903         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 904         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 905         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 906         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 907         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 908         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 909         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 910         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 911         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 912         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 913         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 914         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 915         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 916         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 917         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 918         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 919         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 920         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 921         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 922         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 923         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 924         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 925         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 926         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 927         flavors.
 928         * i386-tbl.h: Re-generate.
 929
 930 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 933         register operands.
 934         * i386-tbl.h: Re-generate.
 935
 936 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 939         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 940         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 941         * i386-tbl.h: Re-generate.
 942
 943 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 946         Disp8MemShift from register only templates.
 947         * i386-tbl.h: Re-generate.
 948
 949 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 952         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 953         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 954         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 955         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 956         EVEX_W_0F11_P_3_M_1): Delete.
 957         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 958         EVEX_W_0F11_P_3): New.
 959         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 960         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 961         MOD_EVEX_0F11_PREFIX_3 table entries.
 962         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 963         PREFIX_EVEX_0F11 table entries.
 964         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 965         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 966         EVEX_W_0F11_P_3_M_{0,1} table entries.
 967
 968 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 971         Delete.
 972
 973 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 974
 975         PR binutils/24719
 976         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 977         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 978         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 979         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 980         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 981         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 982         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 983         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 984         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 985         PREFIX_EVEX_0F38C6_REG_6 entries.
 986         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 987         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 988         EVEX_W_0F38C7_R_6_P_2 entries.
 989         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 990         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 991         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 992         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 993         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 994         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 995         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 996
 997 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1000         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1001         VEX_LEN_0F2D_P_3): Delete.
1002         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1003         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1004         (prefix_table): ... here.
1005
1006 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-dis.c (Iq): Delete.
1009         (Id): New.
1010         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1011         TBM insns.
1012         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1013         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1014         (OP_E_memory): Also honor needindex when deciding whether an
1015         address size prefix needs printing.
1016         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1017
1018 2019-06-26  Jim Wilson  <jimw@sifive.com>
1019
1020         PR binutils/24739
1021         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1022         Set info->display_endian to info->endian_code.
1023
1024 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1027         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1028         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1029         OPERAND_TYPE_ACC64 entries.
1030         * i386-init.h: Re-generate.
1031
1032 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1035         Delete.
1036         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1037         of dqa_mode.
1038         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1039         entries here.
1040         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1041         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1042
1043 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1046         variables.
1047
1048 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1051         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1052         movnti.
1053         * i386-opc.tbl (movnti): Add IgnoreSize.
1054         * i386-tbl.h: Re-generate.
1055
1056 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1059         * i386-tbl.h: Re-generate.
1060
1061 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1062
1063         * i386-dis-evex.h: Break into ...
1064         * i386-dis-evex-len.h: New file.
1065         * i386-dis-evex-mod.h: Likewise.
1066         * i386-dis-evex-prefix.h: Likewise.
1067         * i386-dis-evex-reg.h: Likewise.
1068         * i386-dis-evex-w.h: Likewise.
1069         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1070         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1071         i386-dis-evex-mod.h.
1072
1073 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1074
1075         PR binutils/24700
1076         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1077         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1078         EVEX_W_0F385B_P_2.
1079         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1080         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1081         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1082         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1083         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1084         EVEX_LEN_0F385B_P_2_W_1.
1085         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1086         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1087         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1088         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1089         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1090         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1091         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1092         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1093         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1094         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1095
1096 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1097
1098         PR binutils/24691
1099         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1100         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1101         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1102         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1103         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1104         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1105         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1106         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1107         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1108         EVEX_LEN_0F3A43_P_2_W_1.
1109         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1110         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1111         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1112         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1113         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1114         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1115         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1116         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1117         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1118         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1119         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1120         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1121
1122 2019-06-14  Nick Clifton  <nickc@redhat.com>
1123
1124         * po/fr.po; Updated French translation.
1125
1126 2019-06-13  Stafford Horne  <shorne@gmail.com>
1127
1128         * or1k-asm.c: Regenerated.
1129         * or1k-desc.c: Regenerated.
1130         * or1k-desc.h: Regenerated.
1131         * or1k-dis.c: Regenerated.
1132         * or1k-ibld.c: Regenerated.
1133         * or1k-opc.c: Regenerated.
1134         * or1k-opc.h: Regenerated.
1135         * or1k-opinst.c: Regenerated.
1136
1137 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1138
1139         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1140
1141 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1142
1143         PR binutils/24633
1144         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1145         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1146         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1147         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1148         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1149         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1150         EVEX_LEN_0F3A1B_P_2_W_1.
1151         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1152         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1153         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1154         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1155         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1156         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1157         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1158         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1159
1160 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1161
1162         PR binutils/24626
1163         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1164         EVEX.vvvv when disassembling VEX and EVEX instructions.
1165         (OP_VEX): Set vex.register_specifier to 0 after readding
1166         vex.register_specifier.
1167         (OP_Vex_2src_1): Likewise.
1168         (OP_Vex_2src_2): Likewise.
1169         (OP_LWP_E): Likewise.
1170         (OP_EX_Vex): Don't check vex.register_specifier.
1171         (OP_XMM_Vex): Likewise.
1172
1173 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1174             Lili Cui  <lili.cui@intel.com>
1175
1176         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1177         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1178         instructions.
1179         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1180         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1181         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1182         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1183         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1184         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1185         * i386-init.h: Regenerated.
1186         * i386-tbl.h: Likewise.
1187
1188 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1189             Lili Cui  <lili.cui@intel.com>
1190
1191         * doc/c-i386.texi: Document enqcmd.
1192         * testsuite/gas/i386/enqcmd-intel.d: New file.
1193         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1194         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1195         * testsuite/gas/i386/enqcmd.d: Likewise.
1196         * testsuite/gas/i386/enqcmd.s: Likewise.
1197         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1198         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1199         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1200         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1201         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1202         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1203         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1204         and x86-64-enqcmd.
1205
1206 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1207
1208         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1209
1210 2019-06-03  Alan Modra  <amodra@gmail.com>
1211
1212         * ppc-dis.c (prefix_opcd_indices): Correct size.
1213
1214 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1215
1216         PR gas/24625
1217         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1218         Disp8ShiftVL.
1219         * i386-tbl.h: Regenerated.
1220
1221 2019-05-24  Alan Modra  <amodra@gmail.com>
1222
1223         * po/POTFILES.in: Regenerate.
1224
1225 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1226             Alan Modra  <amodra@gmail.com>
1227
1228         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1229         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1230         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1231         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1232         XTOP>): Define and add entries.
1233         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1234         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1235         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1236         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1237
1238 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1239             Alan Modra  <amodra@gmail.com>
1240
1241         * ppc-dis.c (ppc_opts): Add "future" entry.
1242         (PREFIX_OPCD_SEGS): Define.
1243         (prefix_opcd_indices): New array.
1244         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1245         (lookup_prefix): New function.
1246         (print_insn_powerpc): Handle 64-bit prefix instructions.
1247         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1248         (PMRR, POWERXX): Define.
1249         (prefix_opcodes): New instruction table.
1250         (prefix_num_opcodes): New constant.
1251
1252 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1253
1254         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1255         * configure: Regenerated.
1256         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1257         and cpu/bpf.opc.
1258         (HFILES): Add bpf-desc.h and bpf-opc.h.
1259         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1260         bpf-ibld.c and bpf-opc.c.
1261         (BPF_DEPS): Define.
1262         * Makefile.in: Regenerated.
1263         * disassemble.c (ARCH_bpf): Define.
1264         (disassembler): Add case for bfd_arch_bpf.
1265         (disassemble_init_for_target): Likewise.
1266         (enum epbf_isa_attr): Define.
1267         * disassemble.h: extern print_insn_bpf.
1268         * bpf-asm.c: Generated.
1269         * bpf-opc.h: Likewise.
1270         * bpf-opc.c: Likewise.
1271         * bpf-ibld.c: Likewise.
1272         * bpf-dis.c: Likewise.
1273         * bpf-desc.h: Likewise.
1274         * bpf-desc.c: Likewise.
1275
1276 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1277
1278         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1279         and VMSR with the new operands.
1280
1281 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1282
1283         * arm-dis.c (enum mve_instructions): New enum
1284         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1285         and cneg.
1286         (mve_opcodes): New instructions as above.
1287         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1288         csneg and csel.
1289         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1290
1291 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1292
1293         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1294         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1295         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1296         uqshl, urshrl and urshr.
1297         (is_mve_okay_in_it): Add new instructions to TRUE list.
1298         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1299         (print_insn_mve): Updated to accept new %j,
1300         %<bitfield>m and %<bitfield>n patterns.
1301
1302 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1303
1304         * mips-opc.c (mips_builtin_opcodes): Change source register
1305         constraint for DAUI.
1306
1307 2019-05-20  Nick Clifton  <nickc@redhat.com>
1308
1309         * po/fr.po: Updated French translation.
1310
1311 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1312             Michael Collison <michael.collison@arm.com>
1313
1314         * arm-dis.c (thumb32_opcodes): Add new instructions.
1315         (enum mve_instructions): Likewise.
1316         (enum mve_undefined): Add new reasons.
1317         (is_mve_encoding_conflict): Handle new instructions.
1318         (is_mve_undefined): Likewise.
1319         (is_mve_unpredictable): Likewise.
1320         (print_mve_undefined): Likewise.
1321         (print_mve_size): Likewise.
1322
1323 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1324             Michael Collison <michael.collison@arm.com>
1325
1326         * arm-dis.c (thumb32_opcodes): Add new instructions.
1327         (enum mve_instructions): Likewise.
1328         (is_mve_encoding_conflict): Handle new instructions.
1329         (is_mve_undefined): Likewise.
1330         (is_mve_unpredictable): Likewise.
1331         (print_mve_size): Likewise.
1332
1333 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1334             Michael Collison <michael.collison@arm.com>
1335
1336         * arm-dis.c (thumb32_opcodes): Add new instructions.
1337         (enum mve_instructions): Likewise.
1338         (is_mve_encoding_conflict): Likewise.
1339         (is_mve_unpredictable): Likewise.
1340         (print_mve_size): Likewise.
1341
1342 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1343             Michael Collison <michael.collison@arm.com>
1344
1345         * arm-dis.c (thumb32_opcodes): Add new instructions.
1346         (enum mve_instructions): Likewise.
1347         (is_mve_encoding_conflict): Handle new instructions.
1348         (is_mve_undefined): Likewise.
1349         (is_mve_unpredictable): Likewise.
1350         (print_mve_size): Likewise.
1351
1352 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1353             Michael Collison <michael.collison@arm.com>
1354
1355         * arm-dis.c (thumb32_opcodes): Add new instructions.
1356         (enum mve_instructions): Likewise.
1357         (is_mve_encoding_conflict): Handle new instructions.
1358         (is_mve_undefined): Likewise.
1359         (is_mve_unpredictable): Likewise.
1360         (print_mve_size): Likewise.
1361         (print_insn_mve): Likewise.
1362
1363 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1364             Michael Collison <michael.collison@arm.com>
1365
1366         * arm-dis.c (thumb32_opcodes): Add new instructions.
1367         (print_insn_thumb32): Handle new instructions.
1368
1369 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1370             Michael Collison <michael.collison@arm.com>
1371
1372         * arm-dis.c (enum mve_instructions): Add new instructions.
1373         (enum mve_undefined): Add new reasons.
1374         (is_mve_encoding_conflict): Handle new instructions.
1375         (is_mve_undefined): Likewise.
1376         (is_mve_unpredictable): Likewise.
1377         (print_mve_undefined): Likewise.
1378         (print_mve_size): Likewise.
1379         (print_mve_shift_n): Likewise.
1380         (print_insn_mve): Likewise.
1381
1382 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1383             Michael Collison <michael.collison@arm.com>
1384
1385         * arm-dis.c (enum mve_instructions): Add new instructions.
1386         (is_mve_encoding_conflict): Handle new instructions.
1387         (is_mve_unpredictable): Likewise.
1388         (print_mve_rotate): Likewise.
1389         (print_mve_size): Likewise.
1390         (print_insn_mve): Likewise.
1391
1392 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1393             Michael Collison <michael.collison@arm.com>
1394
1395         * arm-dis.c (enum mve_instructions): Add new instructions.
1396         (is_mve_encoding_conflict): Handle new instructions.
1397         (is_mve_unpredictable): Likewise.
1398         (print_mve_size): Likewise.
1399         (print_insn_mve): Likewise.
1400
1401 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1402             Michael Collison <michael.collison@arm.com>
1403
1404         * arm-dis.c (enum mve_instructions): Add new instructions.
1405         (enum mve_undefined): Add new reasons.
1406         (is_mve_encoding_conflict): Handle new instructions.
1407         (is_mve_undefined): Likewise.
1408         (is_mve_unpredictable): Likewise.
1409         (print_mve_undefined): Likewise.
1410         (print_mve_size): Likewise.
1411         (print_insn_mve): Likewise.
1412
1413 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1414             Michael Collison <michael.collison@arm.com>
1415
1416         * arm-dis.c (enum mve_instructions): Add new instructions.
1417         (is_mve_encoding_conflict): Handle new instructions.
1418         (is_mve_undefined): Likewise.
1419         (is_mve_unpredictable): Likewise.
1420         (print_mve_size): Likewise.
1421         (print_insn_mve): Likewise.
1422
1423 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1424             Michael Collison <michael.collison@arm.com>
1425
1426         * arm-dis.c (enum mve_instructions): Add new instructions.
1427         (enum mve_unpredictable): Add new reasons.
1428         (enum mve_undefined): Likewise.
1429         (is_mve_okay_in_it): Handle new isntructions.
1430         (is_mve_encoding_conflict): Likewise.
1431         (is_mve_undefined): Likewise.
1432         (is_mve_unpredictable): Likewise.
1433         (print_mve_vmov_index): Likewise.
1434         (print_simd_imm8): Likewise.
1435         (print_mve_undefined): Likewise.
1436         (print_mve_unpredictable): Likewise.
1437         (print_mve_size): Likewise.
1438         (print_insn_mve): Likewise.
1439
1440 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1441             Michael Collison <michael.collison@arm.com>
1442
1443         * arm-dis.c (enum mve_instructions): Add new instructions.
1444         (enum mve_unpredictable): Add new reasons.
1445         (enum mve_undefined): Likewise.
1446         (is_mve_encoding_conflict): Handle new instructions.
1447         (is_mve_undefined): Likewise.
1448         (is_mve_unpredictable): Likewise.
1449         (print_mve_undefined): Likewise.
1450         (print_mve_unpredictable): Likewise.
1451         (print_mve_rounding_mode): Likewise.
1452         (print_mve_vcvt_size): Likewise.
1453         (print_mve_size): Likewise.
1454         (print_insn_mve): Likewise.
1455
1456 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1457             Michael Collison <michael.collison@arm.com>
1458
1459         * arm-dis.c (enum mve_instructions): Add new instructions.
1460         (enum mve_unpredictable): Add new reasons.
1461         (enum mve_undefined): Likewise.
1462         (is_mve_undefined): Handle new instructions.
1463         (is_mve_unpredictable): Likewise.
1464         (print_mve_undefined): Likewise.
1465         (print_mve_unpredictable): Likewise.
1466         (print_mve_size): Likewise.
1467         (print_insn_mve): Likewise.
1468
1469 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1470             Michael Collison <michael.collison@arm.com>
1471
1472         * arm-dis.c (enum mve_instructions): Add new instructions.
1473         (enum mve_undefined): Add new reasons.
1474         (insns): Add new instructions.
1475         (is_mve_encoding_conflict):
1476         (print_mve_vld_str_addr): New print function.
1477         (is_mve_undefined): Handle new instructions.
1478         (is_mve_unpredictable): Likewise.
1479         (print_mve_undefined): Likewise.
1480         (print_mve_size): Likewise.
1481         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1482         (print_insn_mve):  Handle new operands.
1483
1484 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1485             Michael Collison <michael.collison@arm.com>
1486
1487         * arm-dis.c (enum mve_instructions): Add new instructions.
1488         (enum mve_unpredictable): Add new reasons.
1489         (is_mve_encoding_conflict): Handle new instructions.
1490         (is_mve_unpredictable): Likewise.
1491         (mve_opcodes): Add new instructions.
1492         (print_mve_unpredictable): Handle new reasons.
1493         (print_mve_register_blocks): New print function.
1494         (print_mve_size): Handle new instructions.
1495         (print_insn_mve): Likewise.
1496
1497 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1498             Michael Collison <michael.collison@arm.com>
1499
1500         * arm-dis.c (enum mve_instructions): Add new instructions.
1501         (enum mve_unpredictable): Add new reasons.
1502         (enum mve_undefined): Likewise.
1503         (is_mve_encoding_conflict): Handle new instructions.
1504         (is_mve_undefined): Likewise.
1505         (is_mve_unpredictable): Likewise.
1506         (coprocessor_opcodes): Move NEON VDUP from here...
1507         (neon_opcodes): ... to here.
1508         (mve_opcodes): Add new instructions.
1509         (print_mve_undefined):  Handle new reasons.
1510         (print_mve_unpredictable): Likewise.
1511         (print_mve_size): Handle new instructions.
1512         (print_insn_neon): Handle vdup.
1513         (print_insn_mve): Handle new operands.
1514
1515 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1516             Michael Collison <michael.collison@arm.com>
1517
1518         * arm-dis.c (enum mve_instructions): Add new instructions.
1519         (enum mve_unpredictable): Add new values.
1520         (mve_opcodes): Add new instructions.
1521         (vec_condnames): New array with vector conditions.
1522         (mve_predicatenames): New array with predicate suffixes.
1523         (mve_vec_sizename): New array with vector sizes.
1524         (enum vpt_pred_state): New enum with vector predication states.
1525         (struct vpt_block): New struct type for vpt blocks.
1526         (vpt_block_state): Global struct to keep track of state.
1527         (mve_extract_pred_mask): New helper function.
1528         (num_instructions_vpt_block): Likewise.
1529         (mark_outside_vpt_block): Likewise.
1530         (mark_inside_vpt_block): Likewise.
1531         (invert_next_predicate_state): Likewise.
1532         (update_next_predicate_state): Likewise.
1533         (update_vpt_block_state): Likewise.
1534         (is_vpt_instruction): Likewise.
1535         (is_mve_encoding_conflict): Add entries for new instructions.
1536         (is_mve_unpredictable): Likewise.
1537         (print_mve_unpredictable): Handle new cases.
1538         (print_instruction_predicate): Likewise.
1539         (print_mve_size): New function.
1540         (print_vec_condition): New function.
1541         (print_insn_mve): Handle vpt blocks and new print operands.
1542
1543 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1544
1545         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1546         8, 14 and 15 for Armv8.1-M Mainline.
1547
1548 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1549             Michael Collison <michael.collison@arm.com>
1550
1551         * arm-dis.c (enum mve_instructions): New enum.
1552         (enum mve_unpredictable): Likewise.
1553         (enum mve_undefined): Likewise.
1554         (struct mopcode32): New struct.
1555         (is_mve_okay_in_it): New function.
1556         (is_mve_architecture): Likewise.
1557         (arm_decode_field): Likewise.
1558         (arm_decode_field_multiple): Likewise.
1559         (is_mve_encoding_conflict): Likewise.
1560         (is_mve_undefined): Likewise.
1561         (is_mve_unpredictable): Likewise.
1562         (print_mve_undefined): Likewise.
1563         (print_mve_unpredictable): Likewise.
1564         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1565         (print_insn_mve): New function.
1566         (print_insn_thumb32): Handle MVE architecture.
1567         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1568
1569 2019-05-10  Nick Clifton  <nickc@redhat.com>
1570
1571         PR 24538
1572         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1573         end of the table prematurely.
1574
1575 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1576
1577         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1578         macros for R6.
1579
1580 2019-05-11  Alan Modra  <amodra@gmail.com>
1581
1582         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1583         when -Mraw is in effect.
1584
1585 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1586
1587         * aarch64-dis-2.c: Regenerate.
1588         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1589         (OP_SVE_BBB): New variant set.
1590         (OP_SVE_DDDD): New variant set.
1591         (OP_SVE_HHH): New variant set.
1592         (OP_SVE_HHHU): New variant set.
1593         (OP_SVE_SSS): New variant set.
1594         (OP_SVE_SSSU): New variant set.
1595         (OP_SVE_SHH): New variant set.
1596         (OP_SVE_SBBU): New variant set.
1597         (OP_SVE_DSS): New variant set.
1598         (OP_SVE_DHHU): New variant set.
1599         (OP_SVE_VMV_HSD_BHS): New variant set.
1600         (OP_SVE_VVU_HSD_BHS): New variant set.
1601         (OP_SVE_VVVU_SD_BH): New variant set.
1602         (OP_SVE_VVVU_BHSD): New variant set.
1603         (OP_SVE_VVV_QHD_DBS): New variant set.
1604         (OP_SVE_VVV_HSD_BHS): New variant set.
1605         (OP_SVE_VVV_HSD_BHS2): New variant set.
1606         (OP_SVE_VVV_BHS_HSD): New variant set.
1607         (OP_SVE_VV_BHS_HSD): New variant set.
1608         (OP_SVE_VVV_SD): New variant set.
1609         (OP_SVE_VVU_BHS_HSD): New variant set.
1610         (OP_SVE_VZVV_SD): New variant set.
1611         (OP_SVE_VZVV_BH): New variant set.
1612         (OP_SVE_VZV_SD): New variant set.
1613         (aarch64_opcode_table): Add sve2 instructions.
1614
1615 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1616
1617         * aarch64-asm-2.c: Regenerated.
1618         * aarch64-dis-2.c: Regenerated.
1619         * aarch64-opc-2.c: Regenerated.
1620         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1621         for SVE_SHLIMM_UNPRED_22.
1622         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1623         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1624         operand.
1625
1626 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1627
1628         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1629         sve_size_tsz_bhs iclass encode.
1630         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1631         sve_size_tsz_bhs iclass decode.
1632
1633 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1634
1635         * aarch64-asm-2.c: Regenerated.
1636         * aarch64-dis-2.c: Regenerated.
1637         * aarch64-opc-2.c: Regenerated.
1638         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1639         for SVE_Zm4_11_INDEX.
1640         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1641         (fields): Handle SVE_i2h field.
1642         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1643         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1644
1645 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1646
1647         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1648         sve_shift_tsz_bhsd iclass encode.
1649         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1650         sve_shift_tsz_bhsd iclass decode.
1651
1652 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1653
1654         * aarch64-asm-2.c: Regenerated.
1655         * aarch64-dis-2.c: Regenerated.
1656         * aarch64-opc-2.c: Regenerated.
1657         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1658         (aarch64_encode_variant_using_iclass): Handle
1659         sve_shift_tsz_hsd iclass encode.
1660         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1661         sve_shift_tsz_hsd iclass decode.
1662         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1663         for SVE_SHRIMM_UNPRED_22.
1664         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1665         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1666         operand.
1667
1668 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1669
1670         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1671         sve_size_013 iclass encode.
1672         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1673         sve_size_013 iclass decode.
1674
1675 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1676
1677         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1678         sve_size_bh iclass encode.
1679         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1680         sve_size_bh iclass decode.
1681
1682 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1683
1684         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1685         sve_size_sd2 iclass encode.
1686         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1687         sve_size_sd2 iclass decode.
1688         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1689         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1690
1691 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1692
1693         * aarch64-asm-2.c: Regenerated.
1694         * aarch64-dis-2.c: Regenerated.
1695         * aarch64-opc-2.c: Regenerated.
1696         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1697         for SVE_ADDR_ZX.
1698         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1699         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1700
1701 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1702
1703         * aarch64-asm-2.c: Regenerated.
1704         * aarch64-dis-2.c: Regenerated.
1705         * aarch64-opc-2.c: Regenerated.
1706         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1707         for SVE_Zm3_11_INDEX.
1708         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1709         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1710         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1711         fields.
1712         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1713
1714 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1715
1716         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1717         sve_size_hsd2 iclass encode.
1718         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1719         sve_size_hsd2 iclass decode.
1720         * aarch64-opc.c (fields): Handle SVE_size field.
1721         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1722
1723 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1724
1725         * aarch64-asm-2.c: Regenerated.
1726         * aarch64-dis-2.c: Regenerated.
1727         * aarch64-opc-2.c: Regenerated.
1728         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1729         for SVE_IMM_ROT3.
1730         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1731         (fields): Handle SVE_rot3 field.
1732         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1733         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1734
1735 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1736
1737         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1738         instructions.
1739
1740 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1741
1742         * aarch64-tbl.h
1743         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1744         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1745         aarch64_feature_sve2bitperm): New feature sets.
1746         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1747         for feature set addresses.
1748         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1749         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1750
1751 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1752             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1753
1754         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1755         argument and set ASE_EVA_R6 appropriately.
1756         (set_default_mips_dis_options): Pass ISA to above.
1757         (parse_mips_dis_option): Likewise.
1758         * mips-opc.c (EVAR6): New macro.
1759         (mips_builtin_opcodes): Add llwpe, scwpe.
1760
1761 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1762
1763         * aarch64-asm-2.c: Regenerated.
1764         * aarch64-dis-2.c: Regenerated.
1765         * aarch64-opc-2.c: Regenerated.
1766         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1767         AARCH64_OPND_TME_UIMM16.
1768         (aarch64_print_operand): Likewise.
1769         * aarch64-tbl.h (QL_IMM_NIL): New.
1770         (TME): New.
1771         (_TME_INSN): New.
1772         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1773
1774 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1775
1776         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1777
1778 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1779             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1780
1781         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1782
1783 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1784
1785         * s12z-opc.h: Add extern "C" bracketing to help
1786         users who wish to use this interface in c++ code.
1787
1788 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1789
1790         * s12z-opc.c (bm_decode): Handle bit map operations with the
1791         "reserved0" mode.
1792
1793 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1794
1795         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1796         specifier.  Add entries for VLDR and VSTR of system registers.
1797         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1798         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1799         of %J and %K format specifier.
1800
1801 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1802
1803         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1804         Add new entries for VSCCLRM instruction.
1805         (print_insn_coprocessor): Handle new %C format control code.
1806
1807 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1808
1809         * arm-dis.c (enum isa): New enum.
1810         (struct sopcode32): New structure.
1811         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1812         set isa field of all current entries to ANY.
1813         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1814         Only match an entry if its isa field allows the current mode.
1815
1816 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1817
1818         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1819         CLRM.
1820         (print_insn_thumb32): Add logic to print %n CLRM register list.
1821
1822 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1823
1824         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1825         and %Q patterns.
1826
1827 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1828
1829         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1830         (print_insn_thumb32): Edit the switch case for %Z.
1831
1832 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1833
1834         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1835
1836 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1837
1838         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1839
1840 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1841
1842         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1843
1844 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1845
1846         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1847         Arm register with r13 and r15 unpredictable.
1848         (thumb32_opcodes): New instructions for bfx and bflx.
1849
1850 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1851
1852         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1853
1854 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1855
1856         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1857
1858 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1859
1860         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1861
1862 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1863
1864         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1865
1866 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1867
1868         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1869         "optr". ("operator" is a reserved word in c++).
1870
1871 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1872
1873         * aarch64-opc.c (aarch64_print_operand): Add case for
1874         AARCH64_OPND_Rt_SP.
1875         (verify_constraints): Likewise.
1876         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1877         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1878         to accept Rt|SP as first operand.
1879         (AARCH64_OPERANDS): Add new Rt_SP.
1880         * aarch64-asm-2.c: Regenerated.
1881         * aarch64-dis-2.c: Regenerated.
1882         * aarch64-opc-2.c: Regenerated.
1883
1884 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1885
1886         * aarch64-asm-2.c: Regenerated.
1887         * aarch64-dis-2.c: Likewise.
1888         * aarch64-opc-2.c: Likewise.
1889         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1890
1891 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1892
1893         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1894
1895 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1896
1897         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1898         * i386-init.h: Regenerated.
1899
1900 2019-04-07  Alan Modra  <amodra@gmail.com>
1901
1902         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1903         op_separator to control printing of spaces, comma and parens
1904         rather than need_comma, need_paren and spaces vars.
1905
1906 2019-04-07  Alan Modra  <amodra@gmail.com>
1907
1908         PR 24421
1909         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1910         (print_insn_neon, print_insn_arm): Likewise.
1911
1912 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1913
1914         * i386-dis-evex.h (evex_table): Updated to support BF16
1915         instructions.
1916         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1917         and EVEX_W_0F3872_P_3.
1918         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1919         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1920         * i386-opc.h (enum): Add CpuAVX512_BF16.
1921         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1922         * i386-opc.tbl: Add AVX512 BF16 instructions.
1923         * i386-init.h: Regenerated.
1924         * i386-tbl.h: Likewise.
1925
1926 2019-04-05  Alan Modra  <amodra@gmail.com>
1927
1928         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1929         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1930         to favour printing of "-" branch hint when using the "y" bit.
1931         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1932
1933 2019-04-05  Alan Modra  <amodra@gmail.com>
1934
1935         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1936         opcode until first operand is output.
1937
1938 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1939
1940         PR gas/24349
1941         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1942         (valid_bo_post_v2): Add support for 'at' branch hints.
1943         (insert_bo): Only error on branch on ctr.
1944         (get_bo_hint_mask): New function.
1945         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1946         for inserting 'at' branch hints.
1947         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1948         for extracting 'at' branch hints.
1949         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1950         (BOE): Delete operand.
1951         (BOM, BOP): New operands.
1952         (RM): Update value.
1953         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1954         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1955         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1956         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1957         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1958         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1959         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1960         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1961         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1962         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1963         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1964         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1965         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1966         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1967         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1968         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1969         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1970         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1971         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1972         bttarl+>: New extended mnemonics.
1973
1974 2019-03-28  Alan Modra  <amodra@gmail.com>
1975
1976         PR 24390
1977         * ppc-opc.c (BTF): Define.
1978         (powerpc_opcodes): Use for mtfsb*.
1979         * ppc-dis.c (print_insn_powerpc): Print fields with both
1980         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1981
1982 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1983
1984         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1985         (mapping_symbol_for_insn): Implement new algorithm.
1986         (print_insn): Remove duplicate code.
1987
1988 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1989
1990         * aarch64-dis.c (print_insn_aarch64):
1991         Implement override.
1992
1993 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1994
1995         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1996         order.
1997
1998 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1999
2000         * aarch64-dis.c (last_stop_offset): New.
2001         (print_insn_aarch64): Use stop_offset.
2002
2003 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2004
2005         PR gas/24359
2006         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2007         CPU_ANY_AVX2_FLAGS.
2008         * i386-init.h: Regenerated.
2009
2010 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2011
2012         PR gas/24348
2013         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2014         vmovdqu16, vmovdqu32 and vmovdqu64.
2015         * i386-tbl.h: Regenerated.
2016
2017 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2018
2019         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2020         from vstrszb, vstrszh, and vstrszf.
2021
2022 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2023
2024         * s390-opc.txt: Add instruction descriptions.
2025
2026 2019-02-08  Jim Wilson  <jimw@sifive.com>
2027
2028         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2029         <bne>: Likewise.
2030
2031 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2032
2033         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2034
2035 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2036
2037         PR binutils/23212
2038         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2039         * aarch64-opc.c (verify_elem_sd): New.
2040         (fields): Add FLD_sz entr.
2041         * aarch64-tbl.h (_SIMD_INSN): New.
2042         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2043         fmulx scalar and vector by element isns.
2044
2045 2019-02-07  Nick Clifton  <nickc@redhat.com>
2046
2047         * po/sv.po: Updated Swedish translation.
2048
2049 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2050
2051         * s390-mkopc.c (main): Accept arch13 as cpu string.
2052         * s390-opc.c: Add new instruction formats and instruction opcode
2053         masks.
2054         * s390-opc.txt: Add new arch13 instructions.
2055
2056 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2057
2058         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2059         (aarch64_opcode): Change encoding for stg, stzg
2060         st2g and st2zg.
2061         * aarch64-asm-2.c: Regenerated.
2062         * aarch64-dis-2.c: Regenerated.
2063         * aarch64-opc-2.c: Regenerated.
2064
2065 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2066
2067         * aarch64-asm-2.c: Regenerated.
2068         * aarch64-dis-2.c: Likewise.
2069         * aarch64-opc-2.c: Likewise.
2070         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2071
2072 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2073             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2074
2075         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2076         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2077         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2078         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2079         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2080         case for ldstgv_indexed.
2081         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2082         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2083         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2084         * aarch64-asm-2.c: Regenerated.
2085         * aarch64-dis-2.c: Regenerated.
2086         * aarch64-opc-2.c: Regenerated.
2087
2088 2019-01-23  Nick Clifton  <nickc@redhat.com>
2089
2090         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2091
2092 2019-01-21  Nick Clifton  <nickc@redhat.com>
2093
2094         * po/de.po: Updated German translation.
2095         * po/uk.po: Updated Ukranian translation.
2096
2097 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2098         * mips-dis.c (mips_arch_choices): Fix typo in
2099         gs464, gs464e and gs264e descriptors.
2100
2101 2019-01-19  Nick Clifton  <nickc@redhat.com>
2102
2103         * configure: Regenerate.
2104         * po/opcodes.pot: Regenerate.
2105
2106 2018-06-24  Nick Clifton  <nickc@redhat.com>
2107
2108         2.32 branch created.
2109
2110 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2111
2112         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2113         if it is null.
2114         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2115         zero.
2116
2117 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2118
2119         * configure: Regenerate.
2120
2121 2019-01-07  Alan Modra  <amodra@gmail.com>
2122
2123         * configure: Regenerate.
2124         * po/POTFILES.in: Regenerate.
2125
2126 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2127
2128         * s12z-opc.c: New file.
2129         * s12z-opc.h: New file.
2130         * s12z-dis.c: Removed all code not directly related to display
2131         of instructions.  Used the interface provided by the new files
2132         instead.
2133         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2134         * Makefile.in: Regenerate.
2135         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2136         * configure: Regenerate.
2137
2138 2019-01-01  Alan Modra  <amodra@gmail.com>
2139
2140         Update year range in copyright notice of all files.
2141
2142 For older changes see ChangeLog-2018
2143 \f
2144 Copyright (C) 2019 Free Software Foundation, Inc.
2145
2146 Copying and distribution of this file, with or without modification,
2147 are permitted in any medium without royalty provided the copyright
2148 notice and this notice are preserved.
2149
2150 Local Variables:
2151 mode: change-log
2152 left-margin: 8
2153 fill-column: 74
2154 version-control: never
2155 End: