1 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
3 * i386-dis.c (enum): Add PREFIX_0F09.
4 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
5 (cpu_flags): Add CpuWBNOINVD.
6 * i386-opc.h (enum): Add CpuWBNOINVD.
7 (i386_cpu_flags): Add cpuwbnoinvd.
8 * i386-opc.tbl: Add WBNOINVD instruction.
9 * i386-init.h: Regenerate.
10 * i386-tbl.h: Likewise.
12 2018-01-17 Jim Wilson <jimw@sifive.com>
14 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
16 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
18 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
19 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
20 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
21 (cpu_flags): Add CpuIBT, CpuSHSTK.
22 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
23 (i386_cpu_flags): Add cpuibt, cpushstk.
24 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
25 * i386-init.h: Regenerate.
26 * i386-tbl.h: Likewise.
28 2018-01-16 Nick Clifton <nickc@redhat.com>
30 * po/pt_BR.po: Updated Brazilian Portugese translation.
31 * po/de.po: Updated German translation.
33 2018-01-15 Jim Wilson <jimw@sifive.com>
35 * riscv-opc.c (match_c_nop): New.
36 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
38 2018-01-15 Nick Clifton <nickc@redhat.com>
40 * po/uk.po: Updated Ukranian translation.
42 2018-01-13 Nick Clifton <nickc@redhat.com>
44 * po/opcodes.pot: Regenerated.
46 2018-01-13 Nick Clifton <nickc@redhat.com>
48 * configure: Regenerate.
50 2018-01-13 Nick Clifton <nickc@redhat.com>
54 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
56 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
57 * i386-tbl.h: Regenerate.
59 2018-01-10 Jan Beulich <jbeulich@suse.com>
61 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
62 * i386-tbl.h: Re-generate.
64 2018-01-10 Jan Beulich <jbeulich@suse.com>
66 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
67 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
68 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
69 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
70 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
71 Disp8MemShift of AVX512VL forms.
72 * i386-tbl.h: Re-generate.
74 2018-01-09 Jim Wilson <jimw@sifive.com>
76 * riscv-dis.c (maybe_print_address): If base_reg is zero,
77 then the hi_addr value is zero.
79 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
81 * arm-dis.c (arm_opcodes): Add csdb.
82 (thumb32_opcodes): Add csdb.
84 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
86 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
87 * aarch64-asm-2.c: Regenerate.
88 * aarch64-dis-2.c: Regenerate.
89 * aarch64-opc-2.c: Regenerate.
91 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
94 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
95 Remove AVX512 vmovd with 64-bit operands.
96 * i386-tbl.h: Regenerated.
98 2018-01-05 Jim Wilson <jimw@sifive.com>
100 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
103 2018-01-03 Alan Modra <amodra@gmail.com>
105 Update year range in copyright notice of all files.
107 2018-01-02 Jan Beulich <jbeulich@suse.com>
109 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
110 and OPERAND_TYPE_REGZMM entries.
112 For older changes see ChangeLog-2017
114 Copyright (C) 2018 Free Software Foundation, Inc.
116 Copying and distribution of this file, with or without modification,
117 are permitted in any medium without royalty provided the copyright
118 notice and this notice are preserved.
124 version-control: never