opcodes/ChangeLog

   1 2018-01-09  Jim Wilson  <jimw@sifive.com>
   2
   3         * riscv-dis.c (maybe_print_address): If base_reg is zero,
   4         then the hi_addr value is zero.
   5
   6 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
   7
   8         * arm-dis.c (arm_opcodes): Add csdb.
   9         (thumb32_opcodes): Add csdb.
  10
  11 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
  12
  13         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
  14         * aarch64-asm-2.c: Regenerate.
  15         * aarch64-dis-2.c: Regenerate.
  16         * aarch64-opc-2.c: Regenerate.
  17
  18 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         PR gas/22681
  21         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
  22         Remove AVX512 vmovd with 64-bit operands.
  23         * i386-tbl.h: Regenerated.
  24
  25 2018-01-05  Jim Wilson  <jimw@sifive.com>
  26
  27         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
  28         jalr.
  29
  30 2018-01-03  Alan Modra  <amodra@gmail.com>
  31
  32         Update year range in copyright notice of all files.
  33
  34 2018-01-02  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
  37         and OPERAND_TYPE_REGZMM entries.
  38
  39 For older changes see ChangeLog-2017
  40 \f
  41 Copyright (C) 2018 Free Software Foundation, Inc.
  42
  43 Copying and distribution of this file, with or without modification,
  44 are permitted in any medium without royalty provided the copyright
  45 notice and this notice are preserved.
  46
  47 Local Variables:
  48 mode: change-log
  49 left-margin: 8
  50 fill-column: 74
  51 version-control: never
  52 End: