1 2015-09-28 Tom Rix <tom@bumblecow.com>
3 * ppc-opc.c (PPC500): Mark some opcodes as invalid
5 2015-09-23 Nick Clifton <nickc@redhat.com>
7 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
9 * tic30-dis.c (print_branch): Likewise.
10 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
11 value before left shifting.
12 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
13 * hppa-dis.c (print_insn_hppa): Likewise.
14 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
16 * msp430-dis.c (msp430_singleoperand): Likewise.
17 (msp430_doubleoperand): Likewise.
18 (print_insn_msp430): Likewise.
19 * nds32-asm.c (parse_operand): Likewise.
20 * sh-opc.h (MASK): Likewise.
21 * v850-dis.c (get_operand_value): Likewise.
23 2015-09-22 Nick Clifton <nickc@redhat.com>
25 * rx-decode.opc (bwl): Use RX_Bad_Size.
27 (ubwl): Likewise. Rename to ubw.
28 (uBWL): Rename to uBW.
29 Replace all references to uBWL with uBW.
30 * rx-decode.c: Regenerate.
31 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
32 (opsize_names): Likewise.
33 (print_insn_rx): Detect and report RX_Bad_Size.
35 2015-09-22 Anton Blanchard <anton@samba.org>
37 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
39 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
41 * sparc-dis.c (print_insn_sparc): Handle the privileged register
44 2015-08-24 Jan Stancek <jstancek@redhat.com>
46 * i386-dis.c (print_insn): Fix decoding of three byte operands.
48 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
51 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
52 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
53 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
54 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
55 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
56 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
57 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
58 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
59 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
60 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
61 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
62 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
63 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
64 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
65 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
66 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
67 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
68 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
69 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
70 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
71 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
72 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
73 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
74 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
75 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
76 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
77 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
78 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
79 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
80 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
81 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
82 (vex_w_table): Replace terminals with MOD_TABLE entries for
83 most of mask instructions.
85 2015-08-17 Alan Modra <amodra@gmail.com>
87 * cgen.sh: Trim trailing space from cgen output.
88 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
89 (print_dis_table): Likewise.
90 * opc2c.c (dump_lines): Likewise.
91 (orig_filename): Warning fix.
92 * ia64-asmtab.c: Regenerate.
94 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
96 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
97 and higher with ARM instruction set will now mark the 26-bit
98 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
99 (arm_opcodes): Fix for unpredictable nop being recognized as a
102 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
104 * micromips-opc.c (micromips_opcodes): Re-order table so that move
105 based on 'or' is first.
106 * mips-opc.c (mips_builtin_opcodes): Ditto.
108 2015-08-11 Nick Clifton <nickc@redhat.com>
111 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
114 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
116 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
118 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
120 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
121 * i386-init.h: Regenerated.
123 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
126 * i386-dis.c (MOD_0FC3): New.
127 (PREFIX_0FC3): Renamed to ...
128 (PREFIX_MOD_0_0FC3): This.
129 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
130 (prefix_table): Replace Ma with Ev on movntiS.
131 (mod_table): Add MOD_0FC3.
133 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
135 * configure: Regenerated.
137 2015-07-23 Alan Modra <amodra@gmail.com>
140 * i386-dis.c (get64): Avoid signed integer overflow.
142 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
145 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
146 "EXEvexHalfBcstXmmq" for the second operand.
147 (EVEX_W_0F79_P_2): Likewise.
148 (EVEX_W_0F7A_P_2): Likewise.
149 (EVEX_W_0F7B_P_2): Likewise.
151 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
153 * arm-dis.c (print_insn_coprocessor): Added support for quarter
154 float bitfield format.
155 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
156 quarter float bitfield format.
158 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
160 * configure: Regenerated.
162 2015-07-03 Alan Modra <amodra@gmail.com>
164 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
165 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
166 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
168 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
169 Cesar Philippidis <cesar@codesourcery.com>
171 * nios2-dis.c (nios2_extract_opcode): New.
172 (nios2_disassembler_state): New.
173 (nios2_find_opcode_hash): Use mach parameter to select correct
175 (nios2_print_insn_arg): Extend to support new R2 argument letters
177 (print_insn_nios2): Check for 16-bit instruction at end of memory.
178 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
179 (NIOS2_NUM_OPCODES): Rename to...
180 (NIOS2_NUM_R1_OPCODES): This.
181 (nios2_r2_opcodes): New.
182 (NIOS2_NUM_R2_OPCODES): New.
183 (nios2_num_r2_opcodes): New.
184 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
185 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
186 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
187 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
188 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
190 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
192 * i386-dis.c (OP_Mwaitx): New.
193 (rm_table): Add monitorx/mwaitx.
194 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
195 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
196 (operand_type_init): Add CpuMWAITX.
197 * i386-opc.h (CpuMWAITX): New.
198 (i386_cpu_flags): Add cpumwaitx.
199 * i386-opc.tbl: Add monitorx and mwaitx.
200 * i386-init.h: Regenerated.
201 * i386-tbl.h: Likewise.
203 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
205 * ppc-opc.c (insert_ls): Test for invalid LS operands.
206 (insert_esync): New function.
207 (LS, WC): Use insert_ls.
208 (ESYNC): Use insert_esync.
210 2015-06-22 Nick Clifton <nickc@redhat.com>
212 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
213 requested region lies beyond it.
214 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
215 looking for 32-bit insns.
216 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
218 * sh-dis.c (print_insn_sh): Likewise.
219 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
220 blocks of instructions.
221 * vax-dis.c (print_insn_vax): Check that the requested address
222 does not clash with the stop_vma.
224 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
226 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
227 * ppc-opc.c (FXM4): Add non-zero optional value.
230 (insert_fxm): Handle new default operand value.
231 (extract_fxm): Likewise.
232 (insert_tbr): Likewise.
233 (extract_tbr): Likewise.
235 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
237 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
239 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
241 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
243 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
245 * ppc-opc.c: Add comment accidentally removed by old commit.
248 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
250 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
252 2015-06-04 Nick Clifton <nickc@redhat.com>
255 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
257 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
259 * arm-dis.c (arm_opcodes): Add "setpan".
260 (thumb_opcodes): Add "setpan".
262 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
264 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
267 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
269 * aarch64-tbl.h (aarch64_feature_rdma): New.
271 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
272 * aarch64-asm-2.c: Regenerate.
273 * aarch64-dis-2.c: Regenerate.
274 * aarch64-opc-2.c: Regenerate.
276 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
278 * aarch64-tbl.h (aarch64_feature_lor): New.
280 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
282 * aarch64-asm-2.c: Regenerate.
283 * aarch64-dis-2.c: Regenerate.
284 * aarch64-opc-2.c: Regenerate.
286 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
288 * aarch64-opc.c (F_ARCHEXT): New.
289 (aarch64_sys_regs): Add "pan".
290 (aarch64_sys_reg_supported_p): New.
291 (aarch64_pstatefields): Add "pan".
292 (aarch64_pstatefield_supported_p): New.
294 2015-06-01 Jan Beulich <jbeulich@suse.com>
296 * i386-tbl.h: Regenerate.
298 2015-06-01 Jan Beulich <jbeulich@suse.com>
300 * i386-dis.c (print_insn): Swap rounding mode specifier and
301 general purpose register in Intel mode.
303 2015-06-01 Jan Beulich <jbeulich@suse.com>
305 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
306 * i386-tbl.h: Regenerate.
308 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
310 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
311 * i386-init.h: Regenerated.
313 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
316 * i386-dis.c: Add comments for '@'.
317 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
318 (enum x86_64_isa): New.
320 (print_i386_disassembler_options): Add amd64 and intel64.
321 (print_insn): Handle amd64 and intel64.
323 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
324 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
325 * i386-opc.h (AMD64): New.
326 (CpuIntel64): Likewise.
327 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
328 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
329 Mark direct call/jmp without Disp16|Disp32 as Intel64.
330 * i386-init.h: Regenerated.
331 * i386-tbl.h: Likewise.
333 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
335 * ppc-opc.c (IH) New define.
336 (powerpc_opcodes) <wait>: Do not enable for POWER7.
337 <tlbie>: Add RS operand for POWER7.
338 <slbia>: Add IH operand for POWER6.
340 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
342 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
345 * i386-tbl.h: Regenerated.
347 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
349 * configure.ac: Support bfd_iamcu_arch.
350 * disassemble.c (disassembler): Support bfd_iamcu_arch.
351 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
352 CPU_IAMCU_COMPAT_FLAGS.
353 (cpu_flags): Add CpuIAMCU.
354 * i386-opc.h (CpuIAMCU): New.
355 (i386_cpu_flags): Add cpuiamcu.
356 * configure: Regenerated.
357 * i386-init.h: Likewise.
358 * i386-tbl.h: Likewise.
360 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
363 * i386-dis.c (X86_64_E8): New.
364 (X86_64_E9): Likewise.
365 Update comments on 'T', 'U', 'V'. Add comments for '^'.
366 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
367 (x86_64_table): Add X86_64_E8 and X86_64_E9.
368 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
370 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
373 2015-04-30 DJ Delorie <dj@redhat.com>
375 * disassemble.c (disassembler): Choose suitable disassembler based
377 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
378 it to decode mul/div insns.
379 * rl78-decode.c: Regenerate.
380 * rl78-dis.c (print_insn_rl78): Rename to...
381 (print_insn_rl78_common): ...this, take ISA parameter.
382 (print_insn_rl78): New.
383 (print_insn_rl78_g10): New.
384 (print_insn_rl78_g13): New.
385 (print_insn_rl78_g14): New.
386 (rl78_get_disassembler): New.
388 2015-04-29 Nick Clifton <nickc@redhat.com>
390 * po/fr.po: Updated French translation.
392 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
394 * ppc-opc.c (DCBT_EO): New define.
395 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
399 <waitrsv>: Do not enable for POWER7 and later.
400 <waitimpl>: Likewise.
401 <dcbt>: Default to the two operand form of the instruction for all
402 "old" cpus. For "new" cpus, use the operand ordering that matches
403 whether the cpu is server or embedded.
406 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
408 * s390-opc.c: New instruction type VV0UU2.
409 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
412 2015-04-23 Jan Beulich <jbeulich@suse.com>
414 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
415 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
416 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
417 (vfpclasspd, vfpclassps): Add %XZ.
419 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
421 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
422 (PREFIX_UD_REPZ): Likewise.
423 (PREFIX_UD_REPNZ): Likewise.
424 (PREFIX_UD_DATA): Likewise.
425 (PREFIX_UD_ADDR): Likewise.
426 (PREFIX_UD_LOCK): Likewise.
428 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
430 * i386-dis.c (prefix_requirement): Removed.
431 (print_insn): Don't set prefix_requirement. Check
432 dp->prefix_requirement instead of prefix_requirement.
434 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
437 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
438 (PREFIX_MOD_0_0FC7_REG_6): This.
439 (PREFIX_MOD_3_0FC7_REG_6): New.
440 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
441 (prefix_table): Replace PREFIX_0FC7_REG_6 with
442 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
443 PREFIX_MOD_3_0FC7_REG_7.
444 (mod_table): Replace PREFIX_0FC7_REG_6 with
445 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
446 PREFIX_MOD_3_0FC7_REG_7.
448 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
450 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
451 (PREFIX_MANDATORY_REPNZ): Likewise.
452 (PREFIX_MANDATORY_DATA): Likewise.
453 (PREFIX_MANDATORY_ADDR): Likewise.
454 (PREFIX_MANDATORY_LOCK): Likewise.
455 (PREFIX_MANDATORY): Likewise.
456 (PREFIX_UD_SHIFT): Set to 8
457 (PREFIX_UD_REPZ): Updated.
458 (PREFIX_UD_REPNZ): Likewise.
459 (PREFIX_UD_DATA): Likewise.
460 (PREFIX_UD_ADDR): Likewise.
461 (PREFIX_UD_LOCK): Likewise.
462 (PREFIX_IGNORED_SHIFT): New.
463 (PREFIX_IGNORED_REPZ): Likewise.
464 (PREFIX_IGNORED_REPNZ): Likewise.
465 (PREFIX_IGNORED_DATA): Likewise.
466 (PREFIX_IGNORED_ADDR): Likewise.
467 (PREFIX_IGNORED_LOCK): Likewise.
468 (PREFIX_OPCODE): Likewise.
469 (PREFIX_IGNORED): Likewise.
470 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
471 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
472 (three_byte_table): Likewise.
473 (mod_table): Likewise.
474 (mandatory_prefix): Renamed to ...
475 (prefix_requirement): This.
476 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
477 Update PREFIX_90 entry.
478 (get_valid_dis386): Check prefix_requirement to see if a prefix
480 (print_insn): Replace mandatory_prefix with prefix_requirement.
482 2015-04-15 Renlin Li <renlin.li@arm.com>
484 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
485 use it for ssat and ssat16.
486 (print_insn_thumb32): Add handle case for 'D' control code.
488 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
489 H.J. Lu <hongjiu.lu@intel.com>
491 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
492 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
493 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
494 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
495 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
496 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
497 Fill prefix_requirement field.
498 (struct dis386): Add prefix_requirement field.
499 (dis386): Fill prefix_requirement field.
500 (dis386_twobyte): Ditto.
501 (twobyte_has_mandatory_prefix_: Remove.
502 (reg_table): Fill prefix_requirement field.
503 (prefix_table): Ditto.
504 (x86_64_table): Ditto.
505 (three_byte_table): Ditto.
508 (vex_len_table): Ditto.
509 (vex_w_table): Ditto.
512 (print_insn): Use prefix_requirement.
513 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
514 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
517 2015-03-30 Mike Frysinger <vapier@gentoo.org>
519 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
521 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
523 * Makefile.in: Regenerated.
525 2015-03-25 Anton Blanchard <anton@samba.org>
527 * ppc-dis.c (disassemble_init_powerpc): Only initialise
528 powerpc_opcd_indices and vle_opcd_indices once.
530 2015-03-25 Anton Blanchard <anton@samba.org>
532 * ppc-opc.c (powerpc_opcodes): Add slbfee.
534 2015-03-24 Terry Guo <terry.guo@arm.com>
536 * arm-dis.c (opcode32): Updated to use new arm feature struct.
537 (opcode16): Likewise.
538 (coprocessor_opcodes): Replace bit with feature struct.
539 (neon_opcodes): Likewise.
540 (arm_opcodes): Likewise.
541 (thumb_opcodes): Likewise.
542 (thumb32_opcodes): Likewise.
543 (print_insn_coprocessor): Likewise.
544 (print_insn_arm): Likewise.
545 (select_arm_features): Follow new feature struct.
547 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
549 * i386-dis.c (rm_table): Add clzero.
550 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
551 Add CPU_CLZERO_FLAGS.
552 (cpu_flags): Add CpuCLZERO.
553 * i386-opc.h: Add CpuCLZERO.
554 * i386-opc.tbl: Add clzero.
555 * i386-init.h: Re-generated.
556 * i386-tbl.h: Re-generated.
558 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
560 * mips-opc.c (decode_mips_operand): Fix constraint issues
561 with u and y operands.
563 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
565 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
567 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
569 * s390-opc.c: Add new IBM z13 instructions.
570 * s390-opc.txt: Likewise.
572 2015-03-10 Renlin Li <renlin.li@arm.com>
574 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
575 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
577 * aarch64-asm-2.c: Regenerate.
578 * aarch64-dis-2.c: Likewise.
579 * aarch64-opc-2.c: Likewise.
581 2015-03-03 Jiong Wang <jiong.wang@arm.com>
583 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
585 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
587 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
589 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
590 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
592 2015-02-23 Vinay <Vinay.G@kpit.com>
594 * rl78-decode.opc (MOV): Added space between two operands for
595 'mov' instruction in index addressing mode.
596 * rl78-decode.c: Regenerate.
598 2015-02-19 Pedro Alves <palves@redhat.com>
600 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
602 2015-02-10 Pedro Alves <palves@redhat.com>
603 Tom Tromey <tromey@redhat.com>
605 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
606 microblaze_and, microblaze_xor.
607 * microblaze-opc.h (opcodes): Adjust.
609 2015-01-28 James Bowman <james.bowman@ftdichip.com>
611 * Makefile.am: Add FT32 files.
612 * configure.ac: Handle FT32.
613 * disassemble.c (disassembler): Call print_insn_ft32.
614 * ft32-dis.c: New file.
615 * ft32-opc.c: New file.
616 * Makefile.in: Regenerate.
617 * configure: Regenerate.
618 * po/POTFILES.in: Regenerate.
620 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
622 * nds32-asm.c (keyword_sr): Add new system registers.
624 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
626 * s390-dis.c (s390_extract_operand): Support vector register
628 (s390_print_insn_with_opcode): Support new operands types and add
629 new handling of optional operands.
630 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
631 and include opcode/s390.h instead.
632 (struct op_struct): New field `flags'.
633 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
634 (dumpTable): Dump flags.
635 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
637 * s390-opc.c: Add new operands types, instruction formats, and
639 (s390_opformats): Add new formats for .insn.
640 * s390-opc.txt: Add new instructions.
642 2015-01-01 Alan Modra <amodra@gmail.com>
644 Update year range in copyright notice of all files.
646 For older changes see ChangeLog-2014
648 Copyright (C) 2015 Free Software Foundation, Inc.
650 Copying and distribution of this file, with or without modification,
651 are permitted in any medium without royalty provided the copyright
652 notice and this notice are preserved.
658 version-control: never