opcodes/ChangeLog

   1 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * bpf-desc.c: Regenerate.
   4         * bpf-opc.c: Likewise.
   5         * bpf-opc.h: Likewise.
   6
   7 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
   8
   9         * bpf-desc.c: Regenerate.
  10         * bpf-opc.c: Likewise.
  11
  12 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  13
  14         * arm-dis.c (print_insn_coprocessor): Rename index to
  15         index_operand.
  16
  17 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  18
  19         * riscv-opc.c (riscv_insn_types): Add r4 type.
  20
  21         * riscv-opc.c (riscv_insn_types): Add b and j type.
  22
  23         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  24         format for sb type and correct s type.
  25
  26 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  27
  28         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
  29         SVE FMOV alias of FCPY.
  30
  31 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  32
  33         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
  34         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
  35
  36 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  37
  38         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
  39         registers in an instruction prefixed by MOVPRFX.
  40
  41 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
  42
  43         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
  44         sve_size_13 icode to account for variant behaviour of
  45         pmull{t,b}.
  46         * aarch64-dis-2.c: Regenerate.
  47         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
  48         sve_size_13 icode to account for variant behaviour of
  49         pmull{t,b}.
  50         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
  51         (OP_SVE_VVV_Q_D): Add new qualifier.
  52         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
  53         (struct aarch64_opcode): Split pmull{t,b} into those requiring
  54         AES and those not.
  55
  56 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  57
  58         * opcodes/i386-gen.c (operand_type_init): Remove
  59         OPERAND_TYPE_VEC_IMM4 entry.
  60         (operand_types): Remove Vec_Imm4.
  61         * opcodes/i386-opc.h (Vec_Imm4): Delete.
  62         (union i386_operand_type): Remove vec_imm4.
  63         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
  64         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  65
  66 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
  69         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
  70         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
  71         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
  72         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
  73         monitorx, mwaitx): Drop ImmExt from operand-less forms.
  74         * i386-tbl.h: Re-generate.
  75
  76 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
  79         register operands.
  80         * i386-tbl.h: Re-generate.
  81
  82 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.tbl (C): New.
  85         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
  86         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
  87         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
  88         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
  89         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
  90         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
  91         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
  92         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
  93         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
  94         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
  95         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
  96         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
  97         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
  98         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
  99         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 100         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 101         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 102         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 103         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 104         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 105         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 106         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 107         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 108         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 109         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 110         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 111         flavors.
 112         * i386-tbl.h: Re-generate.
 113
 114 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 117         register operands.
 118         * i386-tbl.h: Re-generate.
 119
 120 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 123         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 124         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 125         * i386-tbl.h: Re-generate.
 126
 127 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 130         Disp8MemShift from register only templates.
 131         * i386-tbl.h: Re-generate.
 132
 133 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 136         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 137         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 138         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 139         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 140         EVEX_W_0F11_P_3_M_1): Delete.
 141         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 142         EVEX_W_0F11_P_3): New.
 143         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 144         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 145         MOD_EVEX_0F11_PREFIX_3 table entries.
 146         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 147         PREFIX_EVEX_0F11 table entries.
 148         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 149         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 150         EVEX_W_0F11_P_3_M_{0,1} table entries.
 151
 152 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 155         Delete.
 156
 157 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 158
 159         PR binutils/24719
 160         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 161         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 162         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 163         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 164         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 165         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 166         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 167         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 168         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 169         PREFIX_EVEX_0F38C6_REG_6 entries.
 170         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 171         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 172         EVEX_W_0F38C7_R_6_P_2 entries.
 173         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 174         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 175         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 176         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 177         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 178         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 179         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 180
 181 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 184         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 185         VEX_LEN_0F2D_P_3): Delete.
 186         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 187         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 188         (prefix_table): ... here.
 189
 190 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-dis.c (Iq): Delete.
 193         (Id): New.
 194         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 195         TBM insns.
 196         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 197         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 198         (OP_E_memory): Also honor needindex when deciding whether an
 199         address size prefix needs printing.
 200         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 201
 202 2019-06-26  Jim Wilson  <jimw@sifive.com>
 203
 204         PR binutils/24739
 205         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 206         Set info->display_endian to info->endian_code.
 207
 208 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 211         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 212         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 213         OPERAND_TYPE_ACC64 entries.
 214         * i386-init.h: Re-generate.
 215
 216 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 219         Delete.
 220         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 221         of dqa_mode.
 222         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 223         entries here.
 224         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 225         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 226
 227 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 230         variables.
 231
 232 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 235         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 236         movnti.
 237         * i386-opc.tbl (movnti): Add IgnoreSize.
 238         * i386-tbl.h: Re-generate.
 239
 240 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 243         * i386-tbl.h: Re-generate.
 244
 245 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 246
 247         * i386-dis-evex.h: Break into ...
 248         * i386-dis-evex-len.h: New file.
 249         * i386-dis-evex-mod.h: Likewise.
 250         * i386-dis-evex-prefix.h: Likewise.
 251         * i386-dis-evex-reg.h: Likewise.
 252         * i386-dis-evex-w.h: Likewise.
 253         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 254         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 255         i386-dis-evex-mod.h.
 256
 257 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         PR binutils/24700
 260         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 261         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 262         EVEX_W_0F385B_P_2.
 263         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 264         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 265         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 266         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 267         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 268         EVEX_LEN_0F385B_P_2_W_1.
 269         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 270         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 271         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 272         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 273         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 274         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 275         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 276         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 277         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 278         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 279
 280 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 281
 282         PR binutils/24691
 283         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 284         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 285         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 286         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 287         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 288         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 289         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 290         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 291         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 292         EVEX_LEN_0F3A43_P_2_W_1.
 293         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 294         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 295         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 296         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 297         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 298         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 299         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 300         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 301         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 302         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 303         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 304         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 305
 306 2019-06-14  Nick Clifton  <nickc@redhat.com>
 307
 308         * po/fr.po; Updated French translation.
 309
 310 2019-06-13  Stafford Horne  <shorne@gmail.com>
 311
 312         * or1k-asm.c: Regenerated.
 313         * or1k-desc.c: Regenerated.
 314         * or1k-desc.h: Regenerated.
 315         * or1k-dis.c: Regenerated.
 316         * or1k-ibld.c: Regenerated.
 317         * or1k-opc.c: Regenerated.
 318         * or1k-opc.h: Regenerated.
 319         * or1k-opinst.c: Regenerated.
 320
 321 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 322
 323         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 324
 325 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 326
 327         PR binutils/24633
 328         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 329         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 330         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 331         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 332         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 333         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 334         EVEX_LEN_0F3A1B_P_2_W_1.
 335         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 336         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 337         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 338         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 339         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 340         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 341         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 342         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 343
 344 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 345
 346         PR binutils/24626
 347         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 348         EVEX.vvvv when disassembling VEX and EVEX instructions.
 349         (OP_VEX): Set vex.register_specifier to 0 after readding
 350         vex.register_specifier.
 351         (OP_Vex_2src_1): Likewise.
 352         (OP_Vex_2src_2): Likewise.
 353         (OP_LWP_E): Likewise.
 354         (OP_EX_Vex): Don't check vex.register_specifier.
 355         (OP_XMM_Vex): Likewise.
 356
 357 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 358             Lili Cui  <lili.cui@intel.com>
 359
 360         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 361         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 362         instructions.
 363         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 364         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 365         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 366         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 367         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 368         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 369         * i386-init.h: Regenerated.
 370         * i386-tbl.h: Likewise.
 371
 372 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 373             Lili Cui  <lili.cui@intel.com>
 374
 375         * doc/c-i386.texi: Document enqcmd.
 376         * testsuite/gas/i386/enqcmd-intel.d: New file.
 377         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 378         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 379         * testsuite/gas/i386/enqcmd.d: Likewise.
 380         * testsuite/gas/i386/enqcmd.s: Likewise.
 381         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 382         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 383         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 384         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 385         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 386         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 387         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 388         and x86-64-enqcmd.
 389
 390 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 391
 392         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 393
 394 2019-06-03  Alan Modra  <amodra@gmail.com>
 395
 396         * ppc-dis.c (prefix_opcd_indices): Correct size.
 397
 398 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         PR gas/24625
 401         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 402         Disp8ShiftVL.
 403         * i386-tbl.h: Regenerated.
 404
 405 2019-05-24  Alan Modra  <amodra@gmail.com>
 406
 407         * po/POTFILES.in: Regenerate.
 408
 409 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 410             Alan Modra  <amodra@gmail.com>
 411
 412         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 413         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 414         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 415         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 416         XTOP>): Define and add entries.
 417         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 418         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 419         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 420         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 421
 422 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 423             Alan Modra  <amodra@gmail.com>
 424
 425         * ppc-dis.c (ppc_opts): Add "future" entry.
 426         (PREFIX_OPCD_SEGS): Define.
 427         (prefix_opcd_indices): New array.
 428         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 429         (lookup_prefix): New function.
 430         (print_insn_powerpc): Handle 64-bit prefix instructions.
 431         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 432         (PMRR, POWERXX): Define.
 433         (prefix_opcodes): New instruction table.
 434         (prefix_num_opcodes): New constant.
 435
 436 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 437
 438         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 439         * configure: Regenerated.
 440         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 441         and cpu/bpf.opc.
 442         (HFILES): Add bpf-desc.h and bpf-opc.h.
 443         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 444         bpf-ibld.c and bpf-opc.c.
 445         (BPF_DEPS): Define.
 446         * Makefile.in: Regenerated.
 447         * disassemble.c (ARCH_bpf): Define.
 448         (disassembler): Add case for bfd_arch_bpf.
 449         (disassemble_init_for_target): Likewise.
 450         (enum epbf_isa_attr): Define.
 451         * disassemble.h: extern print_insn_bpf.
 452         * bpf-asm.c: Generated.
 453         * bpf-opc.h: Likewise.
 454         * bpf-opc.c: Likewise.
 455         * bpf-ibld.c: Likewise.
 456         * bpf-dis.c: Likewise.
 457         * bpf-desc.h: Likewise.
 458         * bpf-desc.c: Likewise.
 459
 460 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 461
 462         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 463         and VMSR with the new operands.
 464
 465 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 466
 467         * arm-dis.c (enum mve_instructions): New enum
 468         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 469         and cneg.
 470         (mve_opcodes): New instructions as above.
 471         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 472         csneg and csel.
 473         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 474
 475 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 476
 477         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 478         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 479         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 480         uqshl, urshrl and urshr.
 481         (is_mve_okay_in_it): Add new instructions to TRUE list.
 482         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 483         (print_insn_mve): Updated to accept new %j,
 484         %<bitfield>m and %<bitfield>n patterns.
 485
 486 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 487
 488         * mips-opc.c (mips_builtin_opcodes): Change source register
 489         constraint for DAUI.
 490
 491 2019-05-20  Nick Clifton  <nickc@redhat.com>
 492
 493         * po/fr.po: Updated French translation.
 494
 495 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 496             Michael Collison <michael.collison@arm.com>
 497
 498         * arm-dis.c (thumb32_opcodes): Add new instructions.
 499         (enum mve_instructions): Likewise.
 500         (enum mve_undefined): Add new reasons.
 501         (is_mve_encoding_conflict): Handle new instructions.
 502         (is_mve_undefined): Likewise.
 503         (is_mve_unpredictable): Likewise.
 504         (print_mve_undefined): Likewise.
 505         (print_mve_size): Likewise.
 506
 507 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 508             Michael Collison <michael.collison@arm.com>
 509
 510         * arm-dis.c (thumb32_opcodes): Add new instructions.
 511         (enum mve_instructions): Likewise.
 512         (is_mve_encoding_conflict): Handle new instructions.
 513         (is_mve_undefined): Likewise.
 514         (is_mve_unpredictable): Likewise.
 515         (print_mve_size): Likewise.
 516
 517 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 518             Michael Collison <michael.collison@arm.com>
 519
 520         * arm-dis.c (thumb32_opcodes): Add new instructions.
 521         (enum mve_instructions): Likewise.
 522         (is_mve_encoding_conflict): Likewise.
 523         (is_mve_unpredictable): Likewise.
 524         (print_mve_size): Likewise.
 525
 526 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 527             Michael Collison <michael.collison@arm.com>
 528
 529         * arm-dis.c (thumb32_opcodes): Add new instructions.
 530         (enum mve_instructions): Likewise.
 531         (is_mve_encoding_conflict): Handle new instructions.
 532         (is_mve_undefined): Likewise.
 533         (is_mve_unpredictable): Likewise.
 534         (print_mve_size): Likewise.
 535
 536 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 537             Michael Collison <michael.collison@arm.com>
 538
 539         * arm-dis.c (thumb32_opcodes): Add new instructions.
 540         (enum mve_instructions): Likewise.
 541         (is_mve_encoding_conflict): Handle new instructions.
 542         (is_mve_undefined): Likewise.
 543         (is_mve_unpredictable): Likewise.
 544         (print_mve_size): Likewise.
 545         (print_insn_mve): Likewise.
 546
 547 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 548             Michael Collison <michael.collison@arm.com>
 549
 550         * arm-dis.c (thumb32_opcodes): Add new instructions.
 551         (print_insn_thumb32): Handle new instructions.
 552
 553 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 554             Michael Collison <michael.collison@arm.com>
 555
 556         * arm-dis.c (enum mve_instructions): Add new instructions.
 557         (enum mve_undefined): Add new reasons.
 558         (is_mve_encoding_conflict): Handle new instructions.
 559         (is_mve_undefined): Likewise.
 560         (is_mve_unpredictable): Likewise.
 561         (print_mve_undefined): Likewise.
 562         (print_mve_size): Likewise.
 563         (print_mve_shift_n): Likewise.
 564         (print_insn_mve): Likewise.
 565
 566 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 567             Michael Collison <michael.collison@arm.com>
 568
 569         * arm-dis.c (enum mve_instructions): Add new instructions.
 570         (is_mve_encoding_conflict): Handle new instructions.
 571         (is_mve_unpredictable): Likewise.
 572         (print_mve_rotate): Likewise.
 573         (print_mve_size): Likewise.
 574         (print_insn_mve): Likewise.
 575
 576 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 577             Michael Collison <michael.collison@arm.com>
 578
 579         * arm-dis.c (enum mve_instructions): Add new instructions.
 580         (is_mve_encoding_conflict): Handle new instructions.
 581         (is_mve_unpredictable): Likewise.
 582         (print_mve_size): Likewise.
 583         (print_insn_mve): Likewise.
 584
 585 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 586             Michael Collison <michael.collison@arm.com>
 587
 588         * arm-dis.c (enum mve_instructions): Add new instructions.
 589         (enum mve_undefined): Add new reasons.
 590         (is_mve_encoding_conflict): Handle new instructions.
 591         (is_mve_undefined): Likewise.
 592         (is_mve_unpredictable): Likewise.
 593         (print_mve_undefined): Likewise.
 594         (print_mve_size): Likewise.
 595         (print_insn_mve): Likewise.
 596
 597 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 598             Michael Collison <michael.collison@arm.com>
 599
 600         * arm-dis.c (enum mve_instructions): Add new instructions.
 601         (is_mve_encoding_conflict): Handle new instructions.
 602         (is_mve_undefined): Likewise.
 603         (is_mve_unpredictable): Likewise.
 604         (print_mve_size): Likewise.
 605         (print_insn_mve): Likewise.
 606
 607 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 608             Michael Collison <michael.collison@arm.com>
 609
 610         * arm-dis.c (enum mve_instructions): Add new instructions.
 611         (enum mve_unpredictable): Add new reasons.
 612         (enum mve_undefined): Likewise.
 613         (is_mve_okay_in_it): Handle new isntructions.
 614         (is_mve_encoding_conflict): Likewise.
 615         (is_mve_undefined): Likewise.
 616         (is_mve_unpredictable): Likewise.
 617         (print_mve_vmov_index): Likewise.
 618         (print_simd_imm8): Likewise.
 619         (print_mve_undefined): Likewise.
 620         (print_mve_unpredictable): Likewise.
 621         (print_mve_size): Likewise.
 622         (print_insn_mve): Likewise.
 623
 624 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 625             Michael Collison <michael.collison@arm.com>
 626
 627         * arm-dis.c (enum mve_instructions): Add new instructions.
 628         (enum mve_unpredictable): Add new reasons.
 629         (enum mve_undefined): Likewise.
 630         (is_mve_encoding_conflict): Handle new instructions.
 631         (is_mve_undefined): Likewise.
 632         (is_mve_unpredictable): Likewise.
 633         (print_mve_undefined): Likewise.
 634         (print_mve_unpredictable): Likewise.
 635         (print_mve_rounding_mode): Likewise.
 636         (print_mve_vcvt_size): Likewise.
 637         (print_mve_size): Likewise.
 638         (print_insn_mve): Likewise.
 639
 640 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 641             Michael Collison <michael.collison@arm.com>
 642
 643         * arm-dis.c (enum mve_instructions): Add new instructions.
 644         (enum mve_unpredictable): Add new reasons.
 645         (enum mve_undefined): Likewise.
 646         (is_mve_undefined): Handle new instructions.
 647         (is_mve_unpredictable): Likewise.
 648         (print_mve_undefined): Likewise.
 649         (print_mve_unpredictable): Likewise.
 650         (print_mve_size): Likewise.
 651         (print_insn_mve): Likewise.
 652
 653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 654             Michael Collison <michael.collison@arm.com>
 655
 656         * arm-dis.c (enum mve_instructions): Add new instructions.
 657         (enum mve_undefined): Add new reasons.
 658         (insns): Add new instructions.
 659         (is_mve_encoding_conflict):
 660         (print_mve_vld_str_addr): New print function.
 661         (is_mve_undefined): Handle new instructions.
 662         (is_mve_unpredictable): Likewise.
 663         (print_mve_undefined): Likewise.
 664         (print_mve_size): Likewise.
 665         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 666         (print_insn_mve):  Handle new operands.
 667
 668 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 669             Michael Collison <michael.collison@arm.com>
 670
 671         * arm-dis.c (enum mve_instructions): Add new instructions.
 672         (enum mve_unpredictable): Add new reasons.
 673         (is_mve_encoding_conflict): Handle new instructions.
 674         (is_mve_unpredictable): Likewise.
 675         (mve_opcodes): Add new instructions.
 676         (print_mve_unpredictable): Handle new reasons.
 677         (print_mve_register_blocks): New print function.
 678         (print_mve_size): Handle new instructions.
 679         (print_insn_mve): Likewise.
 680
 681 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 682             Michael Collison <michael.collison@arm.com>
 683
 684         * arm-dis.c (enum mve_instructions): Add new instructions.
 685         (enum mve_unpredictable): Add new reasons.
 686         (enum mve_undefined): Likewise.
 687         (is_mve_encoding_conflict): Handle new instructions.
 688         (is_mve_undefined): Likewise.
 689         (is_mve_unpredictable): Likewise.
 690         (coprocessor_opcodes): Move NEON VDUP from here...
 691         (neon_opcodes): ... to here.
 692         (mve_opcodes): Add new instructions.
 693         (print_mve_undefined):  Handle new reasons.
 694         (print_mve_unpredictable): Likewise.
 695         (print_mve_size): Handle new instructions.
 696         (print_insn_neon): Handle vdup.
 697         (print_insn_mve): Handle new operands.
 698
 699 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 700             Michael Collison <michael.collison@arm.com>
 701
 702         * arm-dis.c (enum mve_instructions): Add new instructions.
 703         (enum mve_unpredictable): Add new values.
 704         (mve_opcodes): Add new instructions.
 705         (vec_condnames): New array with vector conditions.
 706         (mve_predicatenames): New array with predicate suffixes.
 707         (mve_vec_sizename): New array with vector sizes.
 708         (enum vpt_pred_state): New enum with vector predication states.
 709         (struct vpt_block): New struct type for vpt blocks.
 710         (vpt_block_state): Global struct to keep track of state.
 711         (mve_extract_pred_mask): New helper function.
 712         (num_instructions_vpt_block): Likewise.
 713         (mark_outside_vpt_block): Likewise.
 714         (mark_inside_vpt_block): Likewise.
 715         (invert_next_predicate_state): Likewise.
 716         (update_next_predicate_state): Likewise.
 717         (update_vpt_block_state): Likewise.
 718         (is_vpt_instruction): Likewise.
 719         (is_mve_encoding_conflict): Add entries for new instructions.
 720         (is_mve_unpredictable): Likewise.
 721         (print_mve_unpredictable): Handle new cases.
 722         (print_instruction_predicate): Likewise.
 723         (print_mve_size): New function.
 724         (print_vec_condition): New function.
 725         (print_insn_mve): Handle vpt blocks and new print operands.
 726
 727 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 728
 729         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 730         8, 14 and 15 for Armv8.1-M Mainline.
 731
 732 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 733             Michael Collison <michael.collison@arm.com>
 734
 735         * arm-dis.c (enum mve_instructions): New enum.
 736         (enum mve_unpredictable): Likewise.
 737         (enum mve_undefined): Likewise.
 738         (struct mopcode32): New struct.
 739         (is_mve_okay_in_it): New function.
 740         (is_mve_architecture): Likewise.
 741         (arm_decode_field): Likewise.
 742         (arm_decode_field_multiple): Likewise.
 743         (is_mve_encoding_conflict): Likewise.
 744         (is_mve_undefined): Likewise.
 745         (is_mve_unpredictable): Likewise.
 746         (print_mve_undefined): Likewise.
 747         (print_mve_unpredictable): Likewise.
 748         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 749         (print_insn_mve): New function.
 750         (print_insn_thumb32): Handle MVE architecture.
 751         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 752
 753 2019-05-10  Nick Clifton  <nickc@redhat.com>
 754
 755         PR 24538
 756         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 757         end of the table prematurely.
 758
 759 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 760
 761         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 762         macros for R6.
 763
 764 2019-05-11  Alan Modra  <amodra@gmail.com>
 765
 766         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 767         when -Mraw is in effect.
 768
 769 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 770
 771         * aarch64-dis-2.c: Regenerate.
 772         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 773         (OP_SVE_BBB): New variant set.
 774         (OP_SVE_DDDD): New variant set.
 775         (OP_SVE_HHH): New variant set.
 776         (OP_SVE_HHHU): New variant set.
 777         (OP_SVE_SSS): New variant set.
 778         (OP_SVE_SSSU): New variant set.
 779         (OP_SVE_SHH): New variant set.
 780         (OP_SVE_SBBU): New variant set.
 781         (OP_SVE_DSS): New variant set.
 782         (OP_SVE_DHHU): New variant set.
 783         (OP_SVE_VMV_HSD_BHS): New variant set.
 784         (OP_SVE_VVU_HSD_BHS): New variant set.
 785         (OP_SVE_VVVU_SD_BH): New variant set.
 786         (OP_SVE_VVVU_BHSD): New variant set.
 787         (OP_SVE_VVV_QHD_DBS): New variant set.
 788         (OP_SVE_VVV_HSD_BHS): New variant set.
 789         (OP_SVE_VVV_HSD_BHS2): New variant set.
 790         (OP_SVE_VVV_BHS_HSD): New variant set.
 791         (OP_SVE_VV_BHS_HSD): New variant set.
 792         (OP_SVE_VVV_SD): New variant set.
 793         (OP_SVE_VVU_BHS_HSD): New variant set.
 794         (OP_SVE_VZVV_SD): New variant set.
 795         (OP_SVE_VZVV_BH): New variant set.
 796         (OP_SVE_VZV_SD): New variant set.
 797         (aarch64_opcode_table): Add sve2 instructions.
 798
 799 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 800
 801         * aarch64-asm-2.c: Regenerated.
 802         * aarch64-dis-2.c: Regenerated.
 803         * aarch64-opc-2.c: Regenerated.
 804         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 805         for SVE_SHLIMM_UNPRED_22.
 806         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 807         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 808         operand.
 809
 810 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 811
 812         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 813         sve_size_tsz_bhs iclass encode.
 814         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 815         sve_size_tsz_bhs iclass decode.
 816
 817 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 818
 819         * aarch64-asm-2.c: Regenerated.
 820         * aarch64-dis-2.c: Regenerated.
 821         * aarch64-opc-2.c: Regenerated.
 822         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 823         for SVE_Zm4_11_INDEX.
 824         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 825         (fields): Handle SVE_i2h field.
 826         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 827         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 828
 829 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 830
 831         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 832         sve_shift_tsz_bhsd iclass encode.
 833         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 834         sve_shift_tsz_bhsd iclass decode.
 835
 836 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 837
 838         * aarch64-asm-2.c: Regenerated.
 839         * aarch64-dis-2.c: Regenerated.
 840         * aarch64-opc-2.c: Regenerated.
 841         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 842         (aarch64_encode_variant_using_iclass): Handle
 843         sve_shift_tsz_hsd iclass encode.
 844         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 845         sve_shift_tsz_hsd iclass decode.
 846         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 847         for SVE_SHRIMM_UNPRED_22.
 848         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 849         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 850         operand.
 851
 852 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 853
 854         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 855         sve_size_013 iclass encode.
 856         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 857         sve_size_013 iclass decode.
 858
 859 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 860
 861         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 862         sve_size_bh iclass encode.
 863         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 864         sve_size_bh iclass decode.
 865
 866 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 867
 868         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 869         sve_size_sd2 iclass encode.
 870         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 871         sve_size_sd2 iclass decode.
 872         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 873         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 874
 875 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 876
 877         * aarch64-asm-2.c: Regenerated.
 878         * aarch64-dis-2.c: Regenerated.
 879         * aarch64-opc-2.c: Regenerated.
 880         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 881         for SVE_ADDR_ZX.
 882         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 883         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 884
 885 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 886
 887         * aarch64-asm-2.c: Regenerated.
 888         * aarch64-dis-2.c: Regenerated.
 889         * aarch64-opc-2.c: Regenerated.
 890         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 891         for SVE_Zm3_11_INDEX.
 892         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 893         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 894         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 895         fields.
 896         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 897
 898 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 899
 900         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 901         sve_size_hsd2 iclass encode.
 902         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 903         sve_size_hsd2 iclass decode.
 904         * aarch64-opc.c (fields): Handle SVE_size field.
 905         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 906
 907 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 908
 909         * aarch64-asm-2.c: Regenerated.
 910         * aarch64-dis-2.c: Regenerated.
 911         * aarch64-opc-2.c: Regenerated.
 912         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 913         for SVE_IMM_ROT3.
 914         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 915         (fields): Handle SVE_rot3 field.
 916         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 917         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 918
 919 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 920
 921         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 922         instructions.
 923
 924 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 925
 926         * aarch64-tbl.h
 927         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 928         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 929         aarch64_feature_sve2bitperm): New feature sets.
 930         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 931         for feature set addresses.
 932         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 933         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 934
 935 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 936             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 937
 938         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 939         argument and set ASE_EVA_R6 appropriately.
 940         (set_default_mips_dis_options): Pass ISA to above.
 941         (parse_mips_dis_option): Likewise.
 942         * mips-opc.c (EVAR6): New macro.
 943         (mips_builtin_opcodes): Add llwpe, scwpe.
 944
 945 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 946
 947         * aarch64-asm-2.c: Regenerated.
 948         * aarch64-dis-2.c: Regenerated.
 949         * aarch64-opc-2.c: Regenerated.
 950         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 951         AARCH64_OPND_TME_UIMM16.
 952         (aarch64_print_operand): Likewise.
 953         * aarch64-tbl.h (QL_IMM_NIL): New.
 954         (TME): New.
 955         (_TME_INSN): New.
 956         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 957
 958 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 959
 960         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 961
 962 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 963             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 964
 965         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 966
 967 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 968
 969         * s12z-opc.h: Add extern "C" bracketing to help
 970         users who wish to use this interface in c++ code.
 971
 972 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 973
 974         * s12z-opc.c (bm_decode): Handle bit map operations with the
 975         "reserved0" mode.
 976
 977 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 978
 979         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 980         specifier.  Add entries for VLDR and VSTR of system registers.
 981         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 982         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 983         of %J and %K format specifier.
 984
 985 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 986
 987         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 988         Add new entries for VSCCLRM instruction.
 989         (print_insn_coprocessor): Handle new %C format control code.
 990
 991 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 992
 993         * arm-dis.c (enum isa): New enum.
 994         (struct sopcode32): New structure.
 995         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 996         set isa field of all current entries to ANY.
 997         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 998         Only match an entry if its isa field allows the current mode.
 999
1000 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1001
1002         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1003         CLRM.
1004         (print_insn_thumb32): Add logic to print %n CLRM register list.
1005
1006 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1007
1008         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1009         and %Q patterns.
1010
1011 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1012
1013         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1014         (print_insn_thumb32): Edit the switch case for %Z.
1015
1016 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1017
1018         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1019
1020 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1021
1022         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1023
1024 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1025
1026         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1027
1028 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1029
1030         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1031         Arm register with r13 and r15 unpredictable.
1032         (thumb32_opcodes): New instructions for bfx and bflx.
1033
1034 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1035
1036         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1037
1038 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1039
1040         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1041
1042 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1043
1044         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1045
1046 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1047
1048         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1049
1050 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1051
1052         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1053         "optr". ("operator" is a reserved word in c++).
1054
1055 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1056
1057         * aarch64-opc.c (aarch64_print_operand): Add case for
1058         AARCH64_OPND_Rt_SP.
1059         (verify_constraints): Likewise.
1060         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1061         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1062         to accept Rt|SP as first operand.
1063         (AARCH64_OPERANDS): Add new Rt_SP.
1064         * aarch64-asm-2.c: Regenerated.
1065         * aarch64-dis-2.c: Regenerated.
1066         * aarch64-opc-2.c: Regenerated.
1067
1068 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1069
1070         * aarch64-asm-2.c: Regenerated.
1071         * aarch64-dis-2.c: Likewise.
1072         * aarch64-opc-2.c: Likewise.
1073         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1074
1075 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1076
1077         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1078
1079 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1080
1081         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1082         * i386-init.h: Regenerated.
1083
1084 2019-04-07  Alan Modra  <amodra@gmail.com>
1085
1086         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1087         op_separator to control printing of spaces, comma and parens
1088         rather than need_comma, need_paren and spaces vars.
1089
1090 2019-04-07  Alan Modra  <amodra@gmail.com>
1091
1092         PR 24421
1093         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1094         (print_insn_neon, print_insn_arm): Likewise.
1095
1096 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1097
1098         * i386-dis-evex.h (evex_table): Updated to support BF16
1099         instructions.
1100         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1101         and EVEX_W_0F3872_P_3.
1102         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1103         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1104         * i386-opc.h (enum): Add CpuAVX512_BF16.
1105         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1106         * i386-opc.tbl: Add AVX512 BF16 instructions.
1107         * i386-init.h: Regenerated.
1108         * i386-tbl.h: Likewise.
1109
1110 2019-04-05  Alan Modra  <amodra@gmail.com>
1111
1112         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1113         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1114         to favour printing of "-" branch hint when using the "y" bit.
1115         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1116
1117 2019-04-05  Alan Modra  <amodra@gmail.com>
1118
1119         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1120         opcode until first operand is output.
1121
1122 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1123
1124         PR gas/24349
1125         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1126         (valid_bo_post_v2): Add support for 'at' branch hints.
1127         (insert_bo): Only error on branch on ctr.
1128         (get_bo_hint_mask): New function.
1129         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1130         for inserting 'at' branch hints.
1131         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1132         for extracting 'at' branch hints.
1133         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1134         (BOE): Delete operand.
1135         (BOM, BOP): New operands.
1136         (RM): Update value.
1137         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1138         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1139         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1140         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1141         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1142         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1143         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1144         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1145         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1146         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1147         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1148         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1149         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1150         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1151         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1152         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1153         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1154         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1155         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1156         bttarl+>: New extended mnemonics.
1157
1158 2019-03-28  Alan Modra  <amodra@gmail.com>
1159
1160         PR 24390
1161         * ppc-opc.c (BTF): Define.
1162         (powerpc_opcodes): Use for mtfsb*.
1163         * ppc-dis.c (print_insn_powerpc): Print fields with both
1164         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1165
1166 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1167
1168         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1169         (mapping_symbol_for_insn): Implement new algorithm.
1170         (print_insn): Remove duplicate code.
1171
1172 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1173
1174         * aarch64-dis.c (print_insn_aarch64):
1175         Implement override.
1176
1177 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1178
1179         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1180         order.
1181
1182 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1183
1184         * aarch64-dis.c (last_stop_offset): New.
1185         (print_insn_aarch64): Use stop_offset.
1186
1187 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1188
1189         PR gas/24359
1190         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1191         CPU_ANY_AVX2_FLAGS.
1192         * i386-init.h: Regenerated.
1193
1194 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1195
1196         PR gas/24348
1197         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1198         vmovdqu16, vmovdqu32 and vmovdqu64.
1199         * i386-tbl.h: Regenerated.
1200
1201 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1202
1203         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1204         from vstrszb, vstrszh, and vstrszf.
1205
1206 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1207
1208         * s390-opc.txt: Add instruction descriptions.
1209
1210 2019-02-08  Jim Wilson  <jimw@sifive.com>
1211
1212         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1213         <bne>: Likewise.
1214
1215 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1216
1217         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1218
1219 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1220
1221         PR binutils/23212
1222         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1223         * aarch64-opc.c (verify_elem_sd): New.
1224         (fields): Add FLD_sz entr.
1225         * aarch64-tbl.h (_SIMD_INSN): New.
1226         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1227         fmulx scalar and vector by element isns.
1228
1229 2019-02-07  Nick Clifton  <nickc@redhat.com>
1230
1231         * po/sv.po: Updated Swedish translation.
1232
1233 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1234
1235         * s390-mkopc.c (main): Accept arch13 as cpu string.
1236         * s390-opc.c: Add new instruction formats and instruction opcode
1237         masks.
1238         * s390-opc.txt: Add new arch13 instructions.
1239
1240 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1241
1242         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1243         (aarch64_opcode): Change encoding for stg, stzg
1244         st2g and st2zg.
1245         * aarch64-asm-2.c: Regenerated.
1246         * aarch64-dis-2.c: Regenerated.
1247         * aarch64-opc-2.c: Regenerated.
1248
1249 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1250
1251         * aarch64-asm-2.c: Regenerated.
1252         * aarch64-dis-2.c: Likewise.
1253         * aarch64-opc-2.c: Likewise.
1254         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1255
1256 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1257             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1258
1259         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1260         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1261         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1262         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1263         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1264         case for ldstgv_indexed.
1265         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1266         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1267         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1268         * aarch64-asm-2.c: Regenerated.
1269         * aarch64-dis-2.c: Regenerated.
1270         * aarch64-opc-2.c: Regenerated.
1271
1272 2019-01-23  Nick Clifton  <nickc@redhat.com>
1273
1274         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1275
1276 2019-01-21  Nick Clifton  <nickc@redhat.com>
1277
1278         * po/de.po: Updated German translation.
1279         * po/uk.po: Updated Ukranian translation.
1280
1281 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1282         * mips-dis.c (mips_arch_choices): Fix typo in
1283         gs464, gs464e and gs264e descriptors.
1284
1285 2019-01-19  Nick Clifton  <nickc@redhat.com>
1286
1287         * configure: Regenerate.
1288         * po/opcodes.pot: Regenerate.
1289
1290 2018-06-24  Nick Clifton  <nickc@redhat.com>
1291
1292         2.32 branch created.
1293
1294 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1295
1296         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1297         if it is null.
1298         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1299         zero.
1300
1301 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1302
1303         * configure: Regenerate.
1304
1305 2019-01-07  Alan Modra  <amodra@gmail.com>
1306
1307         * configure: Regenerate.
1308         * po/POTFILES.in: Regenerate.
1309
1310 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1311
1312         * s12z-opc.c: New file.
1313         * s12z-opc.h: New file.
1314         * s12z-dis.c: Removed all code not directly related to display
1315         of instructions.  Used the interface provided by the new files
1316         instead.
1317         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1318         * Makefile.in: Regenerate.
1319         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1320         * configure: Regenerate.
1321
1322 2019-01-01  Alan Modra  <amodra@gmail.com>
1323
1324         Update year range in copyright notice of all files.
1325
1326 For older changes see ChangeLog-2018
1327 \f
1328 Copyright (C) 2019 Free Software Foundation, Inc.
1329
1330 Copying and distribution of this file, with or without modification,
1331 are permitted in any medium without royalty provided the copyright
1332 notice and this notice are preserved.
1333
1334 Local Variables:
1335 mode: change-log
1336 left-margin: 8
1337 fill-column: 74
1338 version-control: never
1339 End: