1 2019-12-27 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (Jdqw): Define.
4 (dqw_mode): Adjust associated comment.
5 (rm_table): Use Jdqw for XBEGIN.
6 (OP_J): Handle dqw_mode.
8 2019-12-27 Jan Beulich <jbeulich@suse.com>
10 * i386-gen.c (process_i386_operand_type): Don't set Disp32 for
12 * i386-opc.tbl (mov): Fold two templates.
13 (jcxz, jecxz, jrcxz, loop, loope, loopne, loopnz, loopz): Drop
14 Disp16, Disp32, and Disp32S.
15 (xbegin): Add Disp32S.
16 * i386-tbl.h: Re-generate.
18 2019-12-26 Alan Modra <amodra@gmail.com>
20 * crx-dis.c (get_number_of_operands): Don't access operands[]
23 2019-12-26 Alan Modra <amodra@gmail.com>
25 * v850-dis.c (disassemble): Avoid signed overflow. Don't use
26 long vars when unsigned int will do.
28 2019-12-24 Alan Modra <amodra@gmail.com>
30 * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
32 2019-12-23 Jan Beulich <jbeulich@suse.com>
34 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
36 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
38 2019-12-23 Alan Modra <amodra@gmail.com>
40 * score-dis.c (print_insn_score32): Avoid signed overflow.
41 (print_insn_score48): Likewise. Don't cast to int when printing
44 2019-12-23 Alan Modra <amodra@gmail.com>
46 * iq2000-ibld.c: Regenerate.
48 2019-12-23 Alan Modra <amodra@gmail.com>
50 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
51 oper. Use unsigned vars.
52 (print_insn): Make num var uint64_t. Constify oper and remove now
53 unnecessary casts on extract_value calls.
54 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
56 2019-12-23 Alan Modra <amodra@gmail.com>
58 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
59 Catch value overflow. Sign extend only on terminating byte.
61 2019-12-20 Alan Modra <amodra@gmail.com>
64 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
65 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
66 printed. Print .word in more cases.
68 2019-12-20 Alan Modra <amodra@gmail.com>
70 * or1k-ibld.c: Regenerate.
72 2019-12-20 Alan Modra <amodra@gmail.com>
74 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
77 2019-12-20 Alan Modra <amodra@gmail.com>
79 * m68hc11-dis.c (read_memory): Delete forward decls.
80 (print_indexed_operand, print_insn): Likewise.
81 (print_indexed_operand): Formatting. Don't rely on short being
82 exactly 16 bits, make sign extension explicit.
83 (print_insn): Likewise. Avoid signed overflow.
85 2019-12-19 Alan Modra <amodra@gmail.com>
87 * vax-dis.c (print_insn_mode): Stop index mode recursion.
89 2019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
92 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
94 * microblaze-opc.h (opcodes): Adjust to suit.
96 2019-12-18 Alan Modra <amodra@gmail.com>
98 * alpha-opc.c (OP): Avoid signed overflow.
99 * arm-dis.c (print_insn): Likewise.
100 * mcore-dis.c (print_insn_mcore): Likewise.
101 * pj-dis.c (get_int): Likewise.
102 * ppc-opc.c (EBD15, EBD15BI): Likewise.
103 * score7-dis.c (s7_print_insn): Likewise.
104 * tic30-dis.c (print_insn_tic30): Likewise.
105 * v850-opc.c (insert_SELID): Likewise.
106 * vax-dis.c (print_insn_vax): Likewise.
107 * arc-ext.c (create_map): Likewise.
108 (struct ExtAuxRegister): Make "address" field unsigned int.
109 (arcExtMap_auxRegName): Pass unsigned address.
110 (dump_ARC_extmap): Adjust.
111 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
113 2019-12-17 Alan Modra <amodra@gmail.com>
115 * visium-dis.c (print_insn_visium): Avoid signed overflow.
117 2019-12-17 Alan Modra <amodra@gmail.com>
119 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
120 (value_fit_unsigned_field_p): Likewise.
121 (aarch64_wide_constant_p): Likewise.
122 (operand_general_constraint_met_p): Likewise.
123 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
125 2019-12-17 Alan Modra <amodra@gmail.com>
127 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
128 (print_insn_nds32): Use uint64_t for "given" and "given1".
130 2019-12-17 Alan Modra <amodra@gmail.com>
132 * tic80-dis.c: Delete file.
133 * tic80-opc.c: Delete file.
134 * disassemble.c: Remove tic80 support.
135 * disassemble.h: Likewise.
136 * Makefile.am: Likewise.
137 * configure.ac: Likewise.
138 * Makefile.in: Regenerate.
139 * configure: Regenerate.
140 * po/POTFILES.in: Regenerate.
142 2019-12-17 Alan Modra <amodra@gmail.com>
144 * bpf-ibld.c: Regenerate.
146 2019-12-16 Alan Modra <amodra@gmail.com>
148 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
150 (aarch64_ext_imm): Avoid signed overflow.
152 2019-12-16 Alan Modra <amodra@gmail.com>
154 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
156 2019-12-16 Alan Modra <amodra@gmail.com>
158 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
160 2019-12-16 Alan Modra <amodra@gmail.com>
162 * xstormy16-ibld.c: Regenerate.
164 2019-12-16 Alan Modra <amodra@gmail.com>
166 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
167 value adjustment so that it doesn't affect reg field too.
169 2019-12-16 Alan Modra <amodra@gmail.com>
171 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
172 (get_number_of_operands, getargtype, getbits, getregname),
173 (getcopregname, getprocregname, gettrapstring, getcinvstring),
174 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
175 (powerof2, match_opcode, make_instruction, print_arguments),
176 (print_arg): Delete forward declarations, moving static to..
177 (getregname, getcopregname, getregliststring): ..these definitions.
178 (build_mask): Return unsigned int mask.
179 (match_opcode): Use unsigned int vars.
181 2019-12-16 Alan Modra <amodra@gmail.com>
183 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
185 2019-12-16 Alan Modra <amodra@gmail.com>
187 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
188 (struct objdump_disasm_info): Delete.
189 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
190 N32_IMMS to unsigned before shifting left.
192 2019-12-16 Alan Modra <amodra@gmail.com>
194 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
195 (print_insn_moxie): Remove unnecessary cast.
197 2019-12-12 Alan Modra <amodra@gmail.com>
199 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
202 2019-12-11 Alan Modra <amodra@gmail.com>
204 * arc-dis.c (BITS): Don't truncate high bits with shifts.
205 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
206 * tic54x-dis.c (print_instruction): Likewise.
207 * tilegx-opc.c (parse_insn_tilegx): Likewise.
208 * tilepro-opc.c (parse_insn_tilepro): Likewise.
209 * visium-dis.c (disassem_class0): Likewise.
210 * pdp11-dis.c (sign_extend): Likewise.
212 * epiphany-ibld.c: Regenerate.
213 * lm32-ibld.c: Regenerate.
214 * m32c-ibld.c: Regenerate.
216 2019-12-11 Alan Modra <amodra@gmail.com>
218 * ns32k-dis.c (sign_extend): Correct last patch.
220 2019-12-11 Alan Modra <amodra@gmail.com>
222 * vax-dis.c (NEXTLONG): Avoid signed overflow.
224 2019-12-11 Alan Modra <amodra@gmail.com>
226 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
227 sign extend using shifts.
229 2019-12-11 Alan Modra <amodra@gmail.com>
231 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
233 2019-12-11 Alan Modra <amodra@gmail.com>
235 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
236 on NULL registertable entry.
237 (tic4x_hash_opcode): Use unsigned arithmetic.
239 2019-12-11 Alan Modra <amodra@gmail.com>
241 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
243 2019-12-11 Alan Modra <amodra@gmail.com>
245 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
246 (bit_extract_simple, sign_extend): Likewise.
248 2019-12-11 Alan Modra <amodra@gmail.com>
250 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
252 2019-12-11 Alan Modra <amodra@gmail.com>
254 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
256 2019-12-11 Alan Modra <amodra@gmail.com>
258 * m68k-dis.c (COERCE32): Cast value first.
259 (NEXTLONG, NEXTULONG): Avoid signed overflow.
261 2019-12-11 Alan Modra <amodra@gmail.com>
263 * h8300-dis.c (extract_immediate): Avoid signed overflow.
264 (bfd_h8_disassemble): Likewise.
266 2019-12-11 Alan Modra <amodra@gmail.com>
268 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
269 past end of operands array.
271 2019-12-11 Alan Modra <amodra@gmail.com>
273 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
274 overflow when collecting bytes of a number.
276 2019-12-11 Alan Modra <amodra@gmail.com>
278 * cris-dis.c (print_with_operands): Avoid signed integer
279 overflow when collecting bytes of a 32-bit integer.
281 2019-12-11 Alan Modra <amodra@gmail.com>
283 * cr16-dis.c (EXTRACT, SBM): Rewrite.
284 (cr16_match_opcode): Delete duplicate bcond test.
286 2019-12-11 Alan Modra <amodra@gmail.com>
288 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
290 (MASKBITS, SIGNEXTEND): Rewrite.
291 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
292 unsigned arithmetic, instead assign result of SIGNEXTEND back
294 (fmtconst_val): Use 1u in shift expression.
296 2019-12-11 Alan Modra <amodra@gmail.com>
298 * arc-dis.c (find_format_from_table): Use ull constant when
299 shifting by up to 32.
301 2019-12-11 Alan Modra <amodra@gmail.com>
304 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
305 false when field is zero for sve_size_tsz_bhs.
307 2019-12-11 Alan Modra <amodra@gmail.com>
309 * epiphany-ibld.c: Regenerate.
311 2019-12-10 Alan Modra <amodra@gmail.com>
314 * disassemble.c (disassemble_free_target): New function.
316 2019-12-10 Alan Modra <amodra@gmail.com>
318 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
319 * disassemble.c (disassemble_init_for_target): Likewise.
320 * bpf-dis.c: Regenerate.
321 * epiphany-dis.c: Regenerate.
322 * fr30-dis.c: Regenerate.
323 * frv-dis.c: Regenerate.
324 * ip2k-dis.c: Regenerate.
325 * iq2000-dis.c: Regenerate.
326 * lm32-dis.c: Regenerate.
327 * m32c-dis.c: Regenerate.
328 * m32r-dis.c: Regenerate.
329 * mep-dis.c: Regenerate.
330 * mt-dis.c: Regenerate.
331 * or1k-dis.c: Regenerate.
332 * xc16x-dis.c: Regenerate.
333 * xstormy16-dis.c: Regenerate.
335 2019-12-10 Alan Modra <amodra@gmail.com>
337 * ppc-dis.c (private): Delete variable.
338 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
339 (powerpc_init_dialect): Don't use global private.
341 2019-12-10 Alan Modra <amodra@gmail.com>
343 * s12z-opc.c: Formatting.
345 2019-12-08 Alan Modra <amodra@gmail.com>
347 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
350 2019-12-05 Jan Beulich <jbeulich@suse.com>
352 * aarch64-tbl.h (aarch64_feature_crypto,
353 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
354 CRYPTO_V8_2_INSN): Delete.
356 2019-12-05 Alan Modra <amodra@gmail.com>
359 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
360 (struct string_buf): New.
361 (strbuf): New function.
362 (get_field): Use strbuf rather than strdup of local temp.
363 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
364 (get_field_rfsl, get_field_imm15): Likewise.
365 (get_field_rd, get_field_r1, get_field_r2): Update macros.
366 (get_field_special): Likewise. Don't strcpy spr. Formatting.
367 (print_insn_microblaze): Formatting. Init and pass string_buf to
370 2019-12-04 Jan Beulich <jbeulich@suse.com>
372 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
373 * i386-tbl.h: Re-generate.
375 2019-12-04 Jan Beulich <jbeulich@suse.com>
377 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
379 2019-12-04 Jan Beulich <jbeulich@suse.com>
381 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
383 (xbegin): Drop DefaultSize.
384 * i386-tbl.h: Re-generate.
386 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
388 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
389 Change the coproc CRC conditions to use the extension
390 feature set, second word, base on ARM_EXT2_CRC.
392 2019-11-14 Jan Beulich <jbeulich@suse.com>
394 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
395 * i386-tbl.h: Re-generate.
397 2019-11-14 Jan Beulich <jbeulich@suse.com>
399 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
400 JumpInterSegment, and JumpAbsolute entries.
401 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
402 JUMP_ABSOLUTE): Define.
403 (struct i386_opcode_modifier): Extend jump field to 3 bits.
404 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
406 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
407 JumpInterSegment): Define.
408 * i386-tbl.h: Re-generate.
410 2019-11-14 Jan Beulich <jbeulich@suse.com>
412 * i386-gen.c (operand_type_init): Remove
413 OPERAND_TYPE_JUMPABSOLUTE entry.
414 (opcode_modifiers): Add JumpAbsolute entry.
415 (operand_types): Remove JumpAbsolute entry.
416 * i386-opc.h (JumpAbsolute): Move between enums.
417 (struct i386_opcode_modifier): Add jumpabsolute field.
418 (union i386_operand_type): Remove jumpabsolute field.
419 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
420 * i386-init.h, i386-tbl.h: Re-generate.
422 2019-11-14 Jan Beulich <jbeulich@suse.com>
424 * i386-gen.c (opcode_modifiers): Add AnySize entry.
425 (operand_types): Remove AnySize entry.
426 * i386-opc.h (AnySize): Move between enums.
427 (struct i386_opcode_modifier): Add anysize field.
428 (OTUnused): Un-comment.
429 (union i386_operand_type): Remove anysize field.
430 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
431 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
432 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
434 * i386-tbl.h: Re-generate.
436 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
438 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
439 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
440 use the floating point register (FPR).
442 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
444 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
446 (is_mve_encoding_conflict): Update cmode conflict checks for
449 2019-11-12 Jan Beulich <jbeulich@suse.com>
451 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
453 (operand_types): Remove EsSeg entry.
454 (main): Replace stale use of OTMax.
455 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
456 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
458 (OTUnused): Comment out.
459 (union i386_operand_type): Remove esseg field.
460 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
461 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
462 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
463 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
464 * i386-init.h, i386-tbl.h: Re-generate.
466 2019-11-12 Jan Beulich <jbeulich@suse.com>
468 * i386-gen.c (operand_instances): Add RegB entry.
469 * i386-opc.h (enum operand_instance): Add RegB.
470 * i386-opc.tbl (RegC, RegD, RegB): Define.
471 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
472 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
473 monitorx, mwaitx): Drop ImmExt and convert encodings
475 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
476 (edx, rdx): Add Instance=RegD.
477 (ebx, rbx): Add Instance=RegB.
478 * i386-tbl.h: Re-generate.
480 2019-11-12 Jan Beulich <jbeulich@suse.com>
482 * i386-gen.c (operand_type_init): Adjust
483 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
484 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
485 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
486 (operand_instances): New.
487 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
488 (output_operand_type): New parameter "instance". Process it.
489 (process_i386_operand_type): New local variable "instance".
490 (main): Adjust static assertions.
491 * i386-opc.h (INSTANCE_WIDTH): Define.
492 (enum operand_instance): New.
493 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
494 (union i386_operand_type): Replace acc, inoutportreg, and
495 shiftcount by instance.
496 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
497 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
499 * i386-init.h, i386-tbl.h: Re-generate.
501 2019-11-11 Jan Beulich <jbeulich@suse.com>
503 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
504 smaxp/sminp entries' "tied_operand" field to 2.
506 2019-11-11 Jan Beulich <jbeulich@suse.com>
508 * aarch64-opc.c (operand_general_constraint_met_p): Replace
509 "index" local variable by that of the already existing "num".
511 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
514 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
515 * i386-tbl.h: Regenerated.
517 2019-11-08 Jan Beulich <jbeulich@suse.com>
519 * i386-gen.c (operand_type_init): Add Class= to
520 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
521 OPERAND_TYPE_REGBND entry.
522 (operand_classes): Add RegMask and RegBND entries.
523 (operand_types): Drop RegMask and RegBND entry.
524 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
525 (RegMask, RegBND): Delete.
526 (union i386_operand_type): Remove regmask and regbnd fields.
527 * i386-opc.tbl (RegMask, RegBND): Define.
528 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
530 * i386-init.h, i386-tbl.h: Re-generate.
532 2019-11-08 Jan Beulich <jbeulich@suse.com>
534 * i386-gen.c (operand_type_init): Add Class= to
535 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
536 OPERAND_TYPE_REGZMM entries.
537 (operand_classes): Add RegMMX and RegSIMD entries.
538 (operand_types): Drop RegMMX and RegSIMD entries.
539 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
540 (RegMMX, RegSIMD): Delete.
541 (union i386_operand_type): Remove regmmx and regsimd fields.
542 * i386-opc.tbl (RegMMX): Define.
543 (RegXMM, RegYMM, RegZMM): Add Class=.
544 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
546 * i386-init.h, i386-tbl.h: Re-generate.
548 2019-11-08 Jan Beulich <jbeulich@suse.com>
550 * i386-gen.c (operand_type_init): Add Class= to
551 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
553 (operand_classes): Add RegCR, RegDR, and RegTR entries.
554 (operand_types): Drop Control, Debug, and Test entries.
555 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
556 (Control, Debug, Test): Delete.
557 (union i386_operand_type): Remove control, debug, and test
559 * i386-opc.tbl (Control, Debug, Test): Define.
560 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
561 Class=RegDR, and Test by Class=RegTR.
562 * i386-init.h, i386-tbl.h: Re-generate.
564 2019-11-08 Jan Beulich <jbeulich@suse.com>
566 * i386-gen.c (operand_type_init): Add Class= to
567 OPERAND_TYPE_SREG entry.
568 (operand_classes): Add SReg entry.
569 (operand_types): Drop SReg entry.
570 * i386-opc.h (enum operand_class): Add SReg.
572 (union i386_operand_type): Remove sreg field.
573 * i386-opc.tbl (SReg): Define.
574 * i386-reg.tbl: Replace SReg by Class=SReg.
575 * i386-init.h, i386-tbl.h: Re-generate.
577 2019-11-08 Jan Beulich <jbeulich@suse.com>
579 * i386-gen.c (operand_type_init): Add Class=. New
580 OPERAND_TYPE_ANYIMM entry.
581 (operand_classes): New.
582 (operand_types): Drop Reg entry.
583 (output_operand_type): New parameter "class". Process it.
584 (process_i386_operand_type): New local variable "class".
585 (main): Adjust static assertions.
586 * i386-opc.h (CLASS_WIDTH): Define.
587 (enum operand_class): New.
588 (Reg): Replace by Class. Adjust comment.
589 (union i386_operand_type): Replace reg by class.
590 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
592 * i386-reg.tbl: Replace Reg by Class=Reg.
593 * i386-init.h: Re-generate.
595 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
597 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
598 (aarch64_opcode_table): Add data gathering hint mnemonic.
599 * opcodes/aarch64-dis-2.c: Account for new instruction.
601 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
603 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
606 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
608 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
609 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
610 aarch64_feature_f64mm): New feature sets.
611 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
612 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
614 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
616 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
617 (OP_SVE_QQQ): New qualifier.
618 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
619 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
620 the movprfx constraint.
621 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
622 (aarch64_opcode_table): Define new instructions smmla,
623 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
625 * aarch64-opc.c (operand_general_constraint_met_p): Handle
626 AARCH64_OPND_SVE_ADDR_RI_S4x32.
627 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
628 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
629 Account for new instructions.
630 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
632 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
634 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
635 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
637 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
639 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
640 (neon_opcodes): Add bfloat SIMD instructions.
641 (print_insn_coprocessor): Add new control character %b to print
642 condition code without checking cp_num.
643 (print_insn_neon): Account for BFloat16 instructions that have no
644 special top-byte handling.
646 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
647 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
649 * arm-dis.c (print_insn_coprocessor,
650 print_insn_generic_coprocessor): Create wrapper functions around
651 the implementation of the print_insn_coprocessor control codes.
652 (print_insn_coprocessor_1): Original print_insn_coprocessor
653 function that now takes which array to look at as an argument.
654 (print_insn_arm): Use both print_insn_coprocessor and
655 print_insn_generic_coprocessor.
656 (print_insn_thumb32): As above.
658 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
659 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
661 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
662 in reglane special case.
663 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
664 aarch64_find_next_opcode): Account for new instructions.
665 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
666 in reglane special case.
667 * aarch64-opc.c (struct operand_qualifier_data): Add data for
668 new AARCH64_OPND_QLF_S_2H qualifier.
669 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
670 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
671 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
673 (BFLOAT_SVE, BFLOAT): New feature set macros.
674 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
676 (aarch64_opcode_table): Define new instructions bfdot,
677 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
680 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
681 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
683 * aarch64-tbl.h (ARMV8_6): New macro.
685 2019-11-07 Jan Beulich <jbeulich@suse.com>
687 * i386-dis.c (prefix_table): Add mcommit.
688 (rm_table): Add rdpru.
689 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
690 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
691 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
692 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
693 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
694 * i386-opc.tbl (mcommit, rdpru): New.
695 * i386-init.h, i386-tbl.h: Re-generate.
697 2019-11-07 Jan Beulich <jbeulich@suse.com>
699 * i386-dis.c (OP_Mwait): Drop local variable "names", use
701 (OP_Monitor): Drop local variable "op1_names", re-purpose
702 "names" for it instead, and replace former "names" uses by
705 2019-11-07 Jan Beulich <jbeulich@suse.com>
708 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
710 * opcodes/i386-tbl.h: Re-generate.
712 2019-11-05 Jan Beulich <jbeulich@suse.com>
714 * i386-dis.c (OP_Mwaitx): Delete.
715 (prefix_table): Use OP_Mwait for mwaitx entry.
716 (OP_Mwait): Also handle mwaitx.
718 2019-11-05 Jan Beulich <jbeulich@suse.com>
720 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
721 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
722 (prefix_table): Add respective entries.
723 (rm_table): Link to those entries.
725 2019-11-05 Jan Beulich <jbeulich@suse.com>
727 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
728 (REG_0F1C_P_0_MOD_0): ... this.
729 (REG_0F1E_MOD_3): Rename to ...
730 (REG_0F1E_P_1_MOD_3): ... this.
731 (RM_0F01_REG_5): Rename to ...
732 (RM_0F01_REG_5_MOD_3): ... this.
733 (RM_0F01_REG_7): Rename to ...
734 (RM_0F01_REG_7_MOD_3): ... this.
735 (RM_0F1E_MOD_3_REG_7): Rename to ...
736 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
737 (RM_0FAE_REG_6): Rename to ...
738 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
739 (RM_0FAE_REG_7): Rename to ...
740 (RM_0FAE_REG_7_MOD_3): ... this.
741 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
742 (PREFIX_0F01_REG_5_MOD_0): ... this.
743 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
744 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
745 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
746 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
747 (PREFIX_0FAE_REG_0): Rename to ...
748 (PREFIX_0FAE_REG_0_MOD_3): ... this.
749 (PREFIX_0FAE_REG_1): Rename to ...
750 (PREFIX_0FAE_REG_1_MOD_3): ... this.
751 (PREFIX_0FAE_REG_2): Rename to ...
752 (PREFIX_0FAE_REG_2_MOD_3): ... this.
753 (PREFIX_0FAE_REG_3): Rename to ...
754 (PREFIX_0FAE_REG_3_MOD_3): ... this.
755 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
756 (PREFIX_0FAE_REG_4_MOD_0): ... this.
757 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
758 (PREFIX_0FAE_REG_4_MOD_3): ... this.
759 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
760 (PREFIX_0FAE_REG_5_MOD_0): ... this.
761 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
762 (PREFIX_0FAE_REG_5_MOD_3): ... this.
763 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
764 (PREFIX_0FAE_REG_6_MOD_0): ... this.
765 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
766 (PREFIX_0FAE_REG_6_MOD_3): ... this.
767 (PREFIX_0FAE_REG_7): Rename to ...
768 (PREFIX_0FAE_REG_7_MOD_0): ... this.
769 (PREFIX_MOD_0_0FC3): Rename to ...
770 (PREFIX_0FC3_MOD_0): ... this.
771 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
772 (PREFIX_0FC7_REG_6_MOD_0): ... this.
773 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
774 (PREFIX_0FC7_REG_6_MOD_3): ... this.
775 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
776 (PREFIX_0FC7_REG_7_MOD_3): ... this.
777 (reg_table, prefix_table, mod_table, rm_table): Adjust
780 2019-11-04 Nick Clifton <nickc@redhat.com>
782 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
783 of a v850 system register. Move the v850_sreg_names array into
785 (get_v850_reg_name): Likewise for ordinary register names.
786 (get_v850_vreg_name): Likewise for vector register names.
787 (get_v850_cc_name): Likewise for condition codes.
788 * get_v850_float_cc_name): Likewise for floating point condition
790 (get_v850_cacheop_name): Likewise for cache-ops.
791 (get_v850_prefop_name): Likewise for pref-ops.
792 (disassemble): Use the new accessor functions.
794 2019-10-30 Delia Burduv <delia.burduv@arm.com>
796 * aarch64-opc.c (print_immediate_offset_address): Don't print the
797 immediate for the writeback form of ldraa/ldrab if it is 0.
798 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
799 * aarch64-opc-2.c: Regenerated.
801 2019-10-30 Jan Beulich <jbeulich@suse.com>
803 * i386-gen.c (operand_type_shorthands): Delete.
804 (operand_type_init): Expand previous shorthands.
805 (set_bitfield_from_shorthand): Rename back to ...
806 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
807 of operand_type_init[].
808 (set_bitfield): Adjust call to the above function.
809 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
810 RegXMM, RegYMM, RegZMM): Define.
811 * i386-reg.tbl: Expand prior shorthands.
813 2019-10-30 Jan Beulich <jbeulich@suse.com>
815 * i386-gen.c (output_i386_opcode): Change order of fields
817 * i386-opc.h (struct insn_template): Move operands field.
818 Convert extension_opcode field to unsigned short.
819 * i386-tbl.h: Re-generate.
821 2019-10-30 Jan Beulich <jbeulich@suse.com>
823 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
825 * i386-opc.h (W): Extend comment.
826 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
827 general purpose variants not allowing for byte operands.
828 * i386-tbl.h: Re-generate.
830 2019-10-29 Nick Clifton <nickc@redhat.com>
832 * tic30-dis.c (print_branch): Correct size of operand array.
834 2019-10-29 Nick Clifton <nickc@redhat.com>
836 * d30v-dis.c (print_insn): Check that operand index is valid
837 before attempting to access the operands array.
839 2019-10-29 Nick Clifton <nickc@redhat.com>
841 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
842 locating the bit to be tested.
844 2019-10-29 Nick Clifton <nickc@redhat.com>
846 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
848 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
849 (print_insn_s12z): Check for illegal size values.
851 2019-10-28 Nick Clifton <nickc@redhat.com>
853 * csky-dis.c (csky_chars_to_number): Check for a negative
854 count. Use an unsigned integer to construct the return value.
856 2019-10-28 Nick Clifton <nickc@redhat.com>
858 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
859 operand buffer. Set value to 15 not 13.
860 (get_register_operand): Use OPERAND_BUFFER_LEN.
861 (get_indirect_operand): Likewise.
862 (print_two_operand): Likewise.
863 (print_three_operand): Likewise.
864 (print_oar_insn): Likewise.
866 2019-10-28 Nick Clifton <nickc@redhat.com>
868 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
869 (bit_extract_simple): Likewise.
870 (bit_copy): Likewise.
871 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
872 index_offset array are not accessed.
874 2019-10-28 Nick Clifton <nickc@redhat.com>
876 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
879 2019-10-25 Nick Clifton <nickc@redhat.com>
881 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
882 access to opcodes.op array element.
884 2019-10-23 Nick Clifton <nickc@redhat.com>
886 * rx-dis.c (get_register_name): Fix spelling typo in error
888 (get_condition_name, get_flag_name, get_double_register_name)
889 (get_double_register_high_name, get_double_register_low_name)
890 (get_double_control_register_name, get_double_condition_name)
891 (get_opsize_name, get_size_name): Likewise.
893 2019-10-22 Nick Clifton <nickc@redhat.com>
895 * rx-dis.c (get_size_name): New function. Provides safe
896 access to name array.
897 (get_opsize_name): Likewise.
898 (print_insn_rx): Use the accessor functions.
900 2019-10-16 Nick Clifton <nickc@redhat.com>
902 * rx-dis.c (get_register_name): New function. Provides safe
903 access to name array.
904 (get_condition_name, get_flag_name, get_double_register_name)
905 (get_double_register_high_name, get_double_register_low_name)
906 (get_double_control_register_name, get_double_condition_name):
908 (print_insn_rx): Use the accessor functions.
910 2019-10-09 Nick Clifton <nickc@redhat.com>
913 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
916 2019-10-07 Jan Beulich <jbeulich@suse.com>
918 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
919 (cmpsd): Likewise. Move EsSeg to other operand.
920 * opcodes/i386-tbl.h: Re-generate.
922 2019-09-23 Alan Modra <amodra@gmail.com>
924 * m68k-dis.c: Include cpu-m68k.h
926 2019-09-23 Alan Modra <amodra@gmail.com>
928 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
929 "elf/mips.h" earlier.
931 2018-09-20 Jan Beulich <jbeulich@suse.com>
934 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
936 * i386-tbl.h: Re-generate.
938 2019-09-18 Alan Modra <amodra@gmail.com>
940 * arc-ext.c: Update throughout for bfd section macro changes.
942 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
944 * Makefile.in: Re-generate.
945 * configure: Re-generate.
947 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
949 * riscv-opc.c (riscv_opcodes): Change subset field
950 to insn_class field for all instructions.
951 (riscv_insn_types): Likewise.
953 2019-09-16 Phil Blundell <pb@pbcl.net>
955 * configure: Regenerated.
957 2019-09-10 Miod Vallat <miod@online.fr>
960 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
962 2019-09-09 Phil Blundell <pb@pbcl.net>
964 binutils 2.33 branch created.
966 2019-09-03 Nick Clifton <nickc@redhat.com>
969 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
970 greater than zero before indexing via (bufcnt -1).
972 2019-09-03 Nick Clifton <nickc@redhat.com>
975 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
976 (MAX_SPEC_REG_NAME_LEN): Define.
977 (struct mmix_dis_info): Use defined constants for array lengths.
978 (get_reg_name): New function.
979 (get_sprec_reg_name): New function.
980 (print_insn_mmix): Use new functions.
982 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
984 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
985 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
986 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
988 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
990 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
991 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
992 (aarch64_sys_reg_supported_p): Update checks for the above.
994 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
996 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
997 cases MVE_SQRSHRL and MVE_UQRSHLL.
998 (print_insn_mve): Add case for specifier 'k' to check
999 specific bit of the instruction.
1001 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
1004 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
1005 encountering an unknown machine type.
1006 (print_insn_arc): Handle arc_insn_length returning 0. In error
1007 cases return -1 rather than calling abort.
1009 2019-08-07 Jan Beulich <jbeulich@suse.com>
1011 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
1012 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
1014 * i386-tbl.h: Re-generate.
1016 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
1018 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
1021 2019-07-30 Mel Chen <mel.chen@sifive.com>
1023 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
1024 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
1026 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1029 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1031 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1032 and MPY class instructions.
1033 (parse_option): Add nps400 option.
1034 (print_arc_disassembler_options): Add nps400 info.
1036 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1038 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1041 * arc-opc.c (RAD_CHK): Add.
1042 * arc-tbl.h: Regenerate.
1044 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1046 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1047 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1049 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1051 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1052 instructions as UNPREDICTABLE.
1054 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1056 * bpf-desc.c: Regenerated.
1058 2019-07-17 Jan Beulich <jbeulich@suse.com>
1060 * i386-gen.c (static_assert): Define.
1062 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1063 (Opcode_Modifier_Num): ... this.
1066 2019-07-16 Jan Beulich <jbeulich@suse.com>
1068 * i386-gen.c (operand_types): Move RegMem ...
1069 (opcode_modifiers): ... here.
1070 * i386-opc.h (RegMem): Move to opcode modifer enum.
1071 (union i386_operand_type): Move regmem field ...
1072 (struct i386_opcode_modifier): ... here.
1073 * i386-opc.tbl (RegMem): Define.
1074 (mov, movq): Move RegMem on segment, control, debug, and test
1076 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1077 to non-SSE2AVX flavor.
1078 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1079 Move RegMem on register only flavors. Drop IgnoreSize from
1080 legacy encoding flavors.
1081 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1083 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1084 register only flavors.
1085 (vmovd): Move RegMem and drop IgnoreSize on register only
1086 flavor. Change opcode and operand order to store form.
1087 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1089 2019-07-16 Jan Beulich <jbeulich@suse.com>
1091 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1093 * i386-opc.h (SReg2, SReg3): Replace by ...
1095 (union i386_operand_type): Replace sreg fields.
1096 * i386-opc.tbl (mov, ): Use SReg.
1097 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1099 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1100 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1102 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1104 * bpf-desc.c: Regenerate.
1105 * bpf-opc.c: Likewise.
1106 * bpf-opc.h: Likewise.
1108 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1110 * bpf-desc.c: Regenerate.
1111 * bpf-opc.c: Likewise.
1113 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1115 * arm-dis.c (print_insn_coprocessor): Rename index to
1118 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
1120 * riscv-opc.c (riscv_insn_types): Add r4 type.
1122 * riscv-opc.c (riscv_insn_types): Add b and j type.
1124 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1125 format for sb type and correct s type.
1127 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1129 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1130 SVE FMOV alias of FCPY.
1132 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1134 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1135 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1137 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1139 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1140 registers in an instruction prefixed by MOVPRFX.
1142 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1144 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1145 sve_size_13 icode to account for variant behaviour of
1147 * aarch64-dis-2.c: Regenerate.
1148 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1149 sve_size_13 icode to account for variant behaviour of
1151 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1152 (OP_SVE_VVV_Q_D): Add new qualifier.
1153 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1154 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1157 2019-07-01 Jan Beulich <jbeulich@suse.com>
1159 * opcodes/i386-gen.c (operand_type_init): Remove
1160 OPERAND_TYPE_VEC_IMM4 entry.
1161 (operand_types): Remove Vec_Imm4.
1162 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1163 (union i386_operand_type): Remove vec_imm4.
1164 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1165 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1167 2019-07-01 Jan Beulich <jbeulich@suse.com>
1169 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1170 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1171 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1172 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1173 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1174 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1175 * i386-tbl.h: Re-generate.
1177 2019-07-01 Jan Beulich <jbeulich@suse.com>
1179 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1181 * i386-tbl.h: Re-generate.
1183 2019-07-01 Jan Beulich <jbeulich@suse.com>
1185 * i386-opc.tbl (C): New.
1186 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1187 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1188 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1189 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1190 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1191 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1192 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1193 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1194 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1195 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1196 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1197 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1198 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1199 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1200 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1201 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1202 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1203 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1204 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1205 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1206 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1207 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1208 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1209 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1210 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1211 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1213 * i386-tbl.h: Re-generate.
1215 2019-07-01 Jan Beulich <jbeulich@suse.com>
1217 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1219 * i386-tbl.h: Re-generate.
1221 2019-07-01 Jan Beulich <jbeulich@suse.com>
1223 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1224 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1225 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1226 * i386-tbl.h: Re-generate.
1228 2019-07-01 Jan Beulich <jbeulich@suse.com>
1230 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1231 Disp8MemShift from register only templates.
1232 * i386-tbl.h: Re-generate.
1234 2019-07-01 Jan Beulich <jbeulich@suse.com>
1236 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1237 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1238 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1239 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1240 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1241 EVEX_W_0F11_P_3_M_1): Delete.
1242 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1243 EVEX_W_0F11_P_3): New.
1244 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1245 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1246 MOD_EVEX_0F11_PREFIX_3 table entries.
1247 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1248 PREFIX_EVEX_0F11 table entries.
1249 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1250 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1251 EVEX_W_0F11_P_3_M_{0,1} table entries.
1253 2019-07-01 Jan Beulich <jbeulich@suse.com>
1255 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1258 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1261 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1262 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1263 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1264 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1265 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1266 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1267 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1268 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1269 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1270 PREFIX_EVEX_0F38C6_REG_6 entries.
1271 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1272 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1273 EVEX_W_0F38C7_R_6_P_2 entries.
1274 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1275 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1276 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1277 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1278 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1279 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1280 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1282 2019-06-27 Jan Beulich <jbeulich@suse.com>
1284 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1285 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1286 VEX_LEN_0F2D_P_3): Delete.
1287 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1288 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1289 (prefix_table): ... here.
1291 2019-06-27 Jan Beulich <jbeulich@suse.com>
1293 * i386-dis.c (Iq): Delete.
1295 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1297 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1298 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1299 (OP_E_memory): Also honor needindex when deciding whether an
1300 address size prefix needs printing.
1301 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1303 2019-06-26 Jim Wilson <jimw@sifive.com>
1306 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1307 Set info->display_endian to info->endian_code.
1309 2019-06-25 Jan Beulich <jbeulich@suse.com>
1311 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1312 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1313 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1314 OPERAND_TYPE_ACC64 entries.
1315 * i386-init.h: Re-generate.
1317 2019-06-25 Jan Beulich <jbeulich@suse.com>
1319 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1321 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1323 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1325 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1326 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1328 2019-06-25 Jan Beulich <jbeulich@suse.com>
1330 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1333 2019-06-25 Jan Beulich <jbeulich@suse.com>
1335 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1336 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1338 * i386-opc.tbl (movnti): Add IgnoreSize.
1339 * i386-tbl.h: Re-generate.
1341 2019-06-25 Jan Beulich <jbeulich@suse.com>
1343 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1344 * i386-tbl.h: Re-generate.
1346 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1348 * i386-dis-evex.h: Break into ...
1349 * i386-dis-evex-len.h: New file.
1350 * i386-dis-evex-mod.h: Likewise.
1351 * i386-dis-evex-prefix.h: Likewise.
1352 * i386-dis-evex-reg.h: Likewise.
1353 * i386-dis-evex-w.h: Likewise.
1354 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1355 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1356 i386-dis-evex-mod.h.
1358 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1361 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1362 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1364 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1365 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1366 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1367 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1368 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1369 EVEX_LEN_0F385B_P_2_W_1.
1370 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1371 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1372 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1373 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1374 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1375 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1376 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1377 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1378 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1379 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1381 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1384 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1385 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1386 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1387 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1388 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1389 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1390 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1391 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1392 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1393 EVEX_LEN_0F3A43_P_2_W_1.
1394 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1395 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1396 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1397 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1398 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1399 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1400 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1401 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1402 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1403 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1404 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1405 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1407 2019-06-14 Nick Clifton <nickc@redhat.com>
1409 * po/fr.po; Updated French translation.
1411 2019-06-13 Stafford Horne <shorne@gmail.com>
1413 * or1k-asm.c: Regenerated.
1414 * or1k-desc.c: Regenerated.
1415 * or1k-desc.h: Regenerated.
1416 * or1k-dis.c: Regenerated.
1417 * or1k-ibld.c: Regenerated.
1418 * or1k-opc.c: Regenerated.
1419 * or1k-opc.h: Regenerated.
1420 * or1k-opinst.c: Regenerated.
1422 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1424 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1426 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1429 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1430 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1431 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1432 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1433 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1434 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1435 EVEX_LEN_0F3A1B_P_2_W_1.
1436 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1437 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1438 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1439 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1440 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1441 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1442 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1443 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1445 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1448 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1449 EVEX.vvvv when disassembling VEX and EVEX instructions.
1450 (OP_VEX): Set vex.register_specifier to 0 after readding
1451 vex.register_specifier.
1452 (OP_Vex_2src_1): Likewise.
1453 (OP_Vex_2src_2): Likewise.
1454 (OP_LWP_E): Likewise.
1455 (OP_EX_Vex): Don't check vex.register_specifier.
1456 (OP_XMM_Vex): Likewise.
1458 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1459 Lili Cui <lili.cui@intel.com>
1461 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1462 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1464 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1465 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1466 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1467 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1468 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1469 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1470 * i386-init.h: Regenerated.
1471 * i386-tbl.h: Likewise.
1473 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1474 Lili Cui <lili.cui@intel.com>
1476 * doc/c-i386.texi: Document enqcmd.
1477 * testsuite/gas/i386/enqcmd-intel.d: New file.
1478 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1479 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1480 * testsuite/gas/i386/enqcmd.d: Likewise.
1481 * testsuite/gas/i386/enqcmd.s: Likewise.
1482 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1483 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1484 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1485 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1486 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1487 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1488 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1491 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1493 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1495 2019-06-03 Alan Modra <amodra@gmail.com>
1497 * ppc-dis.c (prefix_opcd_indices): Correct size.
1499 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1502 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1504 * i386-tbl.h: Regenerated.
1506 2019-05-24 Alan Modra <amodra@gmail.com>
1508 * po/POTFILES.in: Regenerate.
1510 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1511 Alan Modra <amodra@gmail.com>
1513 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1514 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1515 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1516 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1517 XTOP>): Define and add entries.
1518 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1519 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1520 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1521 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1523 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1524 Alan Modra <amodra@gmail.com>
1526 * ppc-dis.c (ppc_opts): Add "future" entry.
1527 (PREFIX_OPCD_SEGS): Define.
1528 (prefix_opcd_indices): New array.
1529 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1530 (lookup_prefix): New function.
1531 (print_insn_powerpc): Handle 64-bit prefix instructions.
1532 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1533 (PMRR, POWERXX): Define.
1534 (prefix_opcodes): New instruction table.
1535 (prefix_num_opcodes): New constant.
1537 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1539 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1540 * configure: Regenerated.
1541 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1543 (HFILES): Add bpf-desc.h and bpf-opc.h.
1544 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1545 bpf-ibld.c and bpf-opc.c.
1547 * Makefile.in: Regenerated.
1548 * disassemble.c (ARCH_bpf): Define.
1549 (disassembler): Add case for bfd_arch_bpf.
1550 (disassemble_init_for_target): Likewise.
1551 (enum epbf_isa_attr): Define.
1552 * disassemble.h: extern print_insn_bpf.
1553 * bpf-asm.c: Generated.
1554 * bpf-opc.h: Likewise.
1555 * bpf-opc.c: Likewise.
1556 * bpf-ibld.c: Likewise.
1557 * bpf-dis.c: Likewise.
1558 * bpf-desc.h: Likewise.
1559 * bpf-desc.c: Likewise.
1561 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1563 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1564 and VMSR with the new operands.
1566 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1568 * arm-dis.c (enum mve_instructions): New enum
1569 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1571 (mve_opcodes): New instructions as above.
1572 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1574 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1576 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1578 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1579 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1580 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1581 uqshl, urshrl and urshr.
1582 (is_mve_okay_in_it): Add new instructions to TRUE list.
1583 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1584 (print_insn_mve): Updated to accept new %j,
1585 %<bitfield>m and %<bitfield>n patterns.
1587 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1589 * mips-opc.c (mips_builtin_opcodes): Change source register
1590 constraint for DAUI.
1592 2019-05-20 Nick Clifton <nickc@redhat.com>
1594 * po/fr.po: Updated French translation.
1596 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1597 Michael Collison <michael.collison@arm.com>
1599 * arm-dis.c (thumb32_opcodes): Add new instructions.
1600 (enum mve_instructions): Likewise.
1601 (enum mve_undefined): Add new reasons.
1602 (is_mve_encoding_conflict): Handle new instructions.
1603 (is_mve_undefined): Likewise.
1604 (is_mve_unpredictable): Likewise.
1605 (print_mve_undefined): Likewise.
1606 (print_mve_size): Likewise.
1608 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1609 Michael Collison <michael.collison@arm.com>
1611 * arm-dis.c (thumb32_opcodes): Add new instructions.
1612 (enum mve_instructions): Likewise.
1613 (is_mve_encoding_conflict): Handle new instructions.
1614 (is_mve_undefined): Likewise.
1615 (is_mve_unpredictable): Likewise.
1616 (print_mve_size): Likewise.
1618 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1619 Michael Collison <michael.collison@arm.com>
1621 * arm-dis.c (thumb32_opcodes): Add new instructions.
1622 (enum mve_instructions): Likewise.
1623 (is_mve_encoding_conflict): Likewise.
1624 (is_mve_unpredictable): Likewise.
1625 (print_mve_size): Likewise.
1627 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1628 Michael Collison <michael.collison@arm.com>
1630 * arm-dis.c (thumb32_opcodes): Add new instructions.
1631 (enum mve_instructions): Likewise.
1632 (is_mve_encoding_conflict): Handle new instructions.
1633 (is_mve_undefined): Likewise.
1634 (is_mve_unpredictable): Likewise.
1635 (print_mve_size): Likewise.
1637 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1638 Michael Collison <michael.collison@arm.com>
1640 * arm-dis.c (thumb32_opcodes): Add new instructions.
1641 (enum mve_instructions): Likewise.
1642 (is_mve_encoding_conflict): Handle new instructions.
1643 (is_mve_undefined): Likewise.
1644 (is_mve_unpredictable): Likewise.
1645 (print_mve_size): Likewise.
1646 (print_insn_mve): Likewise.
1648 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1649 Michael Collison <michael.collison@arm.com>
1651 * arm-dis.c (thumb32_opcodes): Add new instructions.
1652 (print_insn_thumb32): Handle new instructions.
1654 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1655 Michael Collison <michael.collison@arm.com>
1657 * arm-dis.c (enum mve_instructions): Add new instructions.
1658 (enum mve_undefined): Add new reasons.
1659 (is_mve_encoding_conflict): Handle new instructions.
1660 (is_mve_undefined): Likewise.
1661 (is_mve_unpredictable): Likewise.
1662 (print_mve_undefined): Likewise.
1663 (print_mve_size): Likewise.
1664 (print_mve_shift_n): Likewise.
1665 (print_insn_mve): Likewise.
1667 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1668 Michael Collison <michael.collison@arm.com>
1670 * arm-dis.c (enum mve_instructions): Add new instructions.
1671 (is_mve_encoding_conflict): Handle new instructions.
1672 (is_mve_unpredictable): Likewise.
1673 (print_mve_rotate): Likewise.
1674 (print_mve_size): Likewise.
1675 (print_insn_mve): Likewise.
1677 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1678 Michael Collison <michael.collison@arm.com>
1680 * arm-dis.c (enum mve_instructions): Add new instructions.
1681 (is_mve_encoding_conflict): Handle new instructions.
1682 (is_mve_unpredictable): Likewise.
1683 (print_mve_size): Likewise.
1684 (print_insn_mve): Likewise.
1686 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1687 Michael Collison <michael.collison@arm.com>
1689 * arm-dis.c (enum mve_instructions): Add new instructions.
1690 (enum mve_undefined): Add new reasons.
1691 (is_mve_encoding_conflict): Handle new instructions.
1692 (is_mve_undefined): Likewise.
1693 (is_mve_unpredictable): Likewise.
1694 (print_mve_undefined): Likewise.
1695 (print_mve_size): Likewise.
1696 (print_insn_mve): Likewise.
1698 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1699 Michael Collison <michael.collison@arm.com>
1701 * arm-dis.c (enum mve_instructions): Add new instructions.
1702 (is_mve_encoding_conflict): Handle new instructions.
1703 (is_mve_undefined): Likewise.
1704 (is_mve_unpredictable): Likewise.
1705 (print_mve_size): Likewise.
1706 (print_insn_mve): Likewise.
1708 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1709 Michael Collison <michael.collison@arm.com>
1711 * arm-dis.c (enum mve_instructions): Add new instructions.
1712 (enum mve_unpredictable): Add new reasons.
1713 (enum mve_undefined): Likewise.
1714 (is_mve_okay_in_it): Handle new isntructions.
1715 (is_mve_encoding_conflict): Likewise.
1716 (is_mve_undefined): Likewise.
1717 (is_mve_unpredictable): Likewise.
1718 (print_mve_vmov_index): Likewise.
1719 (print_simd_imm8): Likewise.
1720 (print_mve_undefined): Likewise.
1721 (print_mve_unpredictable): Likewise.
1722 (print_mve_size): Likewise.
1723 (print_insn_mve): Likewise.
1725 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1726 Michael Collison <michael.collison@arm.com>
1728 * arm-dis.c (enum mve_instructions): Add new instructions.
1729 (enum mve_unpredictable): Add new reasons.
1730 (enum mve_undefined): Likewise.
1731 (is_mve_encoding_conflict): Handle new instructions.
1732 (is_mve_undefined): Likewise.
1733 (is_mve_unpredictable): Likewise.
1734 (print_mve_undefined): Likewise.
1735 (print_mve_unpredictable): Likewise.
1736 (print_mve_rounding_mode): Likewise.
1737 (print_mve_vcvt_size): Likewise.
1738 (print_mve_size): Likewise.
1739 (print_insn_mve): Likewise.
1741 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1742 Michael Collison <michael.collison@arm.com>
1744 * arm-dis.c (enum mve_instructions): Add new instructions.
1745 (enum mve_unpredictable): Add new reasons.
1746 (enum mve_undefined): Likewise.
1747 (is_mve_undefined): Handle new instructions.
1748 (is_mve_unpredictable): Likewise.
1749 (print_mve_undefined): Likewise.
1750 (print_mve_unpredictable): Likewise.
1751 (print_mve_size): Likewise.
1752 (print_insn_mve): Likewise.
1754 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1755 Michael Collison <michael.collison@arm.com>
1757 * arm-dis.c (enum mve_instructions): Add new instructions.
1758 (enum mve_undefined): Add new reasons.
1759 (insns): Add new instructions.
1760 (is_mve_encoding_conflict):
1761 (print_mve_vld_str_addr): New print function.
1762 (is_mve_undefined): Handle new instructions.
1763 (is_mve_unpredictable): Likewise.
1764 (print_mve_undefined): Likewise.
1765 (print_mve_size): Likewise.
1766 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1767 (print_insn_mve): Handle new operands.
1769 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1770 Michael Collison <michael.collison@arm.com>
1772 * arm-dis.c (enum mve_instructions): Add new instructions.
1773 (enum mve_unpredictable): Add new reasons.
1774 (is_mve_encoding_conflict): Handle new instructions.
1775 (is_mve_unpredictable): Likewise.
1776 (mve_opcodes): Add new instructions.
1777 (print_mve_unpredictable): Handle new reasons.
1778 (print_mve_register_blocks): New print function.
1779 (print_mve_size): Handle new instructions.
1780 (print_insn_mve): Likewise.
1782 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1783 Michael Collison <michael.collison@arm.com>
1785 * arm-dis.c (enum mve_instructions): Add new instructions.
1786 (enum mve_unpredictable): Add new reasons.
1787 (enum mve_undefined): Likewise.
1788 (is_mve_encoding_conflict): Handle new instructions.
1789 (is_mve_undefined): Likewise.
1790 (is_mve_unpredictable): Likewise.
1791 (coprocessor_opcodes): Move NEON VDUP from here...
1792 (neon_opcodes): ... to here.
1793 (mve_opcodes): Add new instructions.
1794 (print_mve_undefined): Handle new reasons.
1795 (print_mve_unpredictable): Likewise.
1796 (print_mve_size): Handle new instructions.
1797 (print_insn_neon): Handle vdup.
1798 (print_insn_mve): Handle new operands.
1800 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1801 Michael Collison <michael.collison@arm.com>
1803 * arm-dis.c (enum mve_instructions): Add new instructions.
1804 (enum mve_unpredictable): Add new values.
1805 (mve_opcodes): Add new instructions.
1806 (vec_condnames): New array with vector conditions.
1807 (mve_predicatenames): New array with predicate suffixes.
1808 (mve_vec_sizename): New array with vector sizes.
1809 (enum vpt_pred_state): New enum with vector predication states.
1810 (struct vpt_block): New struct type for vpt blocks.
1811 (vpt_block_state): Global struct to keep track of state.
1812 (mve_extract_pred_mask): New helper function.
1813 (num_instructions_vpt_block): Likewise.
1814 (mark_outside_vpt_block): Likewise.
1815 (mark_inside_vpt_block): Likewise.
1816 (invert_next_predicate_state): Likewise.
1817 (update_next_predicate_state): Likewise.
1818 (update_vpt_block_state): Likewise.
1819 (is_vpt_instruction): Likewise.
1820 (is_mve_encoding_conflict): Add entries for new instructions.
1821 (is_mve_unpredictable): Likewise.
1822 (print_mve_unpredictable): Handle new cases.
1823 (print_instruction_predicate): Likewise.
1824 (print_mve_size): New function.
1825 (print_vec_condition): New function.
1826 (print_insn_mve): Handle vpt blocks and new print operands.
1828 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1830 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1831 8, 14 and 15 for Armv8.1-M Mainline.
1833 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1834 Michael Collison <michael.collison@arm.com>
1836 * arm-dis.c (enum mve_instructions): New enum.
1837 (enum mve_unpredictable): Likewise.
1838 (enum mve_undefined): Likewise.
1839 (struct mopcode32): New struct.
1840 (is_mve_okay_in_it): New function.
1841 (is_mve_architecture): Likewise.
1842 (arm_decode_field): Likewise.
1843 (arm_decode_field_multiple): Likewise.
1844 (is_mve_encoding_conflict): Likewise.
1845 (is_mve_undefined): Likewise.
1846 (is_mve_unpredictable): Likewise.
1847 (print_mve_undefined): Likewise.
1848 (print_mve_unpredictable): Likewise.
1849 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1850 (print_insn_mve): New function.
1851 (print_insn_thumb32): Handle MVE architecture.
1852 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1854 2019-05-10 Nick Clifton <nickc@redhat.com>
1857 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1858 end of the table prematurely.
1860 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1862 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1865 2019-05-11 Alan Modra <amodra@gmail.com>
1867 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1868 when -Mraw is in effect.
1870 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1872 * aarch64-dis-2.c: Regenerate.
1873 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1874 (OP_SVE_BBB): New variant set.
1875 (OP_SVE_DDDD): New variant set.
1876 (OP_SVE_HHH): New variant set.
1877 (OP_SVE_HHHU): New variant set.
1878 (OP_SVE_SSS): New variant set.
1879 (OP_SVE_SSSU): New variant set.
1880 (OP_SVE_SHH): New variant set.
1881 (OP_SVE_SBBU): New variant set.
1882 (OP_SVE_DSS): New variant set.
1883 (OP_SVE_DHHU): New variant set.
1884 (OP_SVE_VMV_HSD_BHS): New variant set.
1885 (OP_SVE_VVU_HSD_BHS): New variant set.
1886 (OP_SVE_VVVU_SD_BH): New variant set.
1887 (OP_SVE_VVVU_BHSD): New variant set.
1888 (OP_SVE_VVV_QHD_DBS): New variant set.
1889 (OP_SVE_VVV_HSD_BHS): New variant set.
1890 (OP_SVE_VVV_HSD_BHS2): New variant set.
1891 (OP_SVE_VVV_BHS_HSD): New variant set.
1892 (OP_SVE_VV_BHS_HSD): New variant set.
1893 (OP_SVE_VVV_SD): New variant set.
1894 (OP_SVE_VVU_BHS_HSD): New variant set.
1895 (OP_SVE_VZVV_SD): New variant set.
1896 (OP_SVE_VZVV_BH): New variant set.
1897 (OP_SVE_VZV_SD): New variant set.
1898 (aarch64_opcode_table): Add sve2 instructions.
1900 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1902 * aarch64-asm-2.c: Regenerated.
1903 * aarch64-dis-2.c: Regenerated.
1904 * aarch64-opc-2.c: Regenerated.
1905 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1906 for SVE_SHLIMM_UNPRED_22.
1907 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1908 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1911 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1913 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1914 sve_size_tsz_bhs iclass encode.
1915 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1916 sve_size_tsz_bhs iclass decode.
1918 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1920 * aarch64-asm-2.c: Regenerated.
1921 * aarch64-dis-2.c: Regenerated.
1922 * aarch64-opc-2.c: Regenerated.
1923 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1924 for SVE_Zm4_11_INDEX.
1925 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1926 (fields): Handle SVE_i2h field.
1927 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1928 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1930 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1932 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1933 sve_shift_tsz_bhsd iclass encode.
1934 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1935 sve_shift_tsz_bhsd iclass decode.
1937 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1939 * aarch64-asm-2.c: Regenerated.
1940 * aarch64-dis-2.c: Regenerated.
1941 * aarch64-opc-2.c: Regenerated.
1942 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1943 (aarch64_encode_variant_using_iclass): Handle
1944 sve_shift_tsz_hsd iclass encode.
1945 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1946 sve_shift_tsz_hsd iclass decode.
1947 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1948 for SVE_SHRIMM_UNPRED_22.
1949 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1950 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1953 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1955 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1956 sve_size_013 iclass encode.
1957 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1958 sve_size_013 iclass decode.
1960 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1962 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1963 sve_size_bh iclass encode.
1964 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1965 sve_size_bh iclass decode.
1967 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1969 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1970 sve_size_sd2 iclass encode.
1971 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1972 sve_size_sd2 iclass decode.
1973 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1974 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1976 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1978 * aarch64-asm-2.c: Regenerated.
1979 * aarch64-dis-2.c: Regenerated.
1980 * aarch64-opc-2.c: Regenerated.
1981 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1983 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1984 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1986 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1988 * aarch64-asm-2.c: Regenerated.
1989 * aarch64-dis-2.c: Regenerated.
1990 * aarch64-opc-2.c: Regenerated.
1991 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1992 for SVE_Zm3_11_INDEX.
1993 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1994 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1995 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1997 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1999 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2001 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
2002 sve_size_hsd2 iclass encode.
2003 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
2004 sve_size_hsd2 iclass decode.
2005 * aarch64-opc.c (fields): Handle SVE_size field.
2006 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2008 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2010 * aarch64-asm-2.c: Regenerated.
2011 * aarch64-dis-2.c: Regenerated.
2012 * aarch64-opc-2.c: Regenerated.
2013 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
2015 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
2016 (fields): Handle SVE_rot3 field.
2017 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
2018 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2020 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2022 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
2025 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2028 (aarch64_feature_sve2, aarch64_feature_sve2aes,
2029 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2030 aarch64_feature_sve2bitperm): New feature sets.
2031 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2032 for feature set addresses.
2033 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2034 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2036 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2037 Faraz Shahbazker <fshahbazker@wavecomp.com>
2039 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2040 argument and set ASE_EVA_R6 appropriately.
2041 (set_default_mips_dis_options): Pass ISA to above.
2042 (parse_mips_dis_option): Likewise.
2043 * mips-opc.c (EVAR6): New macro.
2044 (mips_builtin_opcodes): Add llwpe, scwpe.
2046 2019-05-01 Sudakshina Das <sudi.das@arm.com>
2048 * aarch64-asm-2.c: Regenerated.
2049 * aarch64-dis-2.c: Regenerated.
2050 * aarch64-opc-2.c: Regenerated.
2051 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2052 AARCH64_OPND_TME_UIMM16.
2053 (aarch64_print_operand): Likewise.
2054 * aarch64-tbl.h (QL_IMM_NIL): New.
2057 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2059 2019-04-29 John Darrington <john@darrington.wattle.id.au>
2061 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2063 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2064 Faraz Shahbazker <fshahbazker@wavecomp.com>
2066 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2068 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2070 * s12z-opc.h: Add extern "C" bracketing to help
2071 users who wish to use this interface in c++ code.
2073 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2075 * s12z-opc.c (bm_decode): Handle bit map operations with the
2078 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2080 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2081 specifier. Add entries for VLDR and VSTR of system registers.
2082 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2083 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2084 of %J and %K format specifier.
2086 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2088 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2089 Add new entries for VSCCLRM instruction.
2090 (print_insn_coprocessor): Handle new %C format control code.
2092 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2094 * arm-dis.c (enum isa): New enum.
2095 (struct sopcode32): New structure.
2096 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2097 set isa field of all current entries to ANY.
2098 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2099 Only match an entry if its isa field allows the current mode.
2101 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2103 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2105 (print_insn_thumb32): Add logic to print %n CLRM register list.
2107 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2109 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2112 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2114 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2115 (print_insn_thumb32): Edit the switch case for %Z.
2117 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2119 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2121 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2123 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2125 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2127 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2129 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2131 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2132 Arm register with r13 and r15 unpredictable.
2133 (thumb32_opcodes): New instructions for bfx and bflx.
2135 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2137 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2139 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2141 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2143 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2145 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2147 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2149 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2151 2019-04-12 John Darrington <john@darrington.wattle.id.au>
2153 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2154 "optr". ("operator" is a reserved word in c++).
2156 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2158 * aarch64-opc.c (aarch64_print_operand): Add case for
2160 (verify_constraints): Likewise.
2161 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2162 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2163 to accept Rt|SP as first operand.
2164 (AARCH64_OPERANDS): Add new Rt_SP.
2165 * aarch64-asm-2.c: Regenerated.
2166 * aarch64-dis-2.c: Regenerated.
2167 * aarch64-opc-2.c: Regenerated.
2169 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2171 * aarch64-asm-2.c: Regenerated.
2172 * aarch64-dis-2.c: Likewise.
2173 * aarch64-opc-2.c: Likewise.
2174 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2176 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2178 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2180 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2182 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2183 * i386-init.h: Regenerated.
2185 2019-04-07 Alan Modra <amodra@gmail.com>
2187 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2188 op_separator to control printing of spaces, comma and parens
2189 rather than need_comma, need_paren and spaces vars.
2191 2019-04-07 Alan Modra <amodra@gmail.com>
2194 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2195 (print_insn_neon, print_insn_arm): Likewise.
2197 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2199 * i386-dis-evex.h (evex_table): Updated to support BF16
2201 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2202 and EVEX_W_0F3872_P_3.
2203 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2204 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2205 * i386-opc.h (enum): Add CpuAVX512_BF16.
2206 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2207 * i386-opc.tbl: Add AVX512 BF16 instructions.
2208 * i386-init.h: Regenerated.
2209 * i386-tbl.h: Likewise.
2211 2019-04-05 Alan Modra <amodra@gmail.com>
2213 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2214 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2215 to favour printing of "-" branch hint when using the "y" bit.
2216 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2218 2019-04-05 Alan Modra <amodra@gmail.com>
2220 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2221 opcode until first operand is output.
2223 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2226 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2227 (valid_bo_post_v2): Add support for 'at' branch hints.
2228 (insert_bo): Only error on branch on ctr.
2229 (get_bo_hint_mask): New function.
2230 (insert_boe): Add new 'branch_taken' formal argument. Add support
2231 for inserting 'at' branch hints.
2232 (extract_boe): Add new 'branch_taken' formal argument. Add support
2233 for extracting 'at' branch hints.
2234 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2235 (BOE): Delete operand.
2236 (BOM, BOP): New operands.
2238 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2239 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2240 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2241 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2242 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2243 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2244 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2245 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2246 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2247 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2248 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2249 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2250 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2251 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2252 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2253 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2254 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2255 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2256 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2257 bttarl+>: New extended mnemonics.
2259 2019-03-28 Alan Modra <amodra@gmail.com>
2262 * ppc-opc.c (BTF): Define.
2263 (powerpc_opcodes): Use for mtfsb*.
2264 * ppc-dis.c (print_insn_powerpc): Print fields with both
2265 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2267 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2269 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2270 (mapping_symbol_for_insn): Implement new algorithm.
2271 (print_insn): Remove duplicate code.
2273 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2275 * aarch64-dis.c (print_insn_aarch64):
2278 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2280 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2283 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2285 * aarch64-dis.c (last_stop_offset): New.
2286 (print_insn_aarch64): Use stop_offset.
2288 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2291 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2293 * i386-init.h: Regenerated.
2295 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2298 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2299 vmovdqu16, vmovdqu32 and vmovdqu64.
2300 * i386-tbl.h: Regenerated.
2302 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2304 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2305 from vstrszb, vstrszh, and vstrszf.
2307 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2309 * s390-opc.txt: Add instruction descriptions.
2311 2019-02-08 Jim Wilson <jimw@sifive.com>
2313 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2316 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2318 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2320 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2323 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2324 * aarch64-opc.c (verify_elem_sd): New.
2325 (fields): Add FLD_sz entr.
2326 * aarch64-tbl.h (_SIMD_INSN): New.
2327 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2328 fmulx scalar and vector by element isns.
2330 2019-02-07 Nick Clifton <nickc@redhat.com>
2332 * po/sv.po: Updated Swedish translation.
2334 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2336 * s390-mkopc.c (main): Accept arch13 as cpu string.
2337 * s390-opc.c: Add new instruction formats and instruction opcode
2339 * s390-opc.txt: Add new arch13 instructions.
2341 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2343 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2344 (aarch64_opcode): Change encoding for stg, stzg
2346 * aarch64-asm-2.c: Regenerated.
2347 * aarch64-dis-2.c: Regenerated.
2348 * aarch64-opc-2.c: Regenerated.
2350 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2352 * aarch64-asm-2.c: Regenerated.
2353 * aarch64-dis-2.c: Likewise.
2354 * aarch64-opc-2.c: Likewise.
2355 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2357 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2358 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2360 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2361 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2362 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2363 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2364 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2365 case for ldstgv_indexed.
2366 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2367 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2368 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2369 * aarch64-asm-2.c: Regenerated.
2370 * aarch64-dis-2.c: Regenerated.
2371 * aarch64-opc-2.c: Regenerated.
2373 2019-01-23 Nick Clifton <nickc@redhat.com>
2375 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2377 2019-01-21 Nick Clifton <nickc@redhat.com>
2379 * po/de.po: Updated German translation.
2380 * po/uk.po: Updated Ukranian translation.
2382 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2383 * mips-dis.c (mips_arch_choices): Fix typo in
2384 gs464, gs464e and gs264e descriptors.
2386 2019-01-19 Nick Clifton <nickc@redhat.com>
2388 * configure: Regenerate.
2389 * po/opcodes.pot: Regenerate.
2391 2018-06-24 Nick Clifton <nickc@redhat.com>
2393 2.32 branch created.
2395 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2397 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2399 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2402 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2404 * configure: Regenerate.
2406 2019-01-07 Alan Modra <amodra@gmail.com>
2408 * configure: Regenerate.
2409 * po/POTFILES.in: Regenerate.
2411 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2413 * s12z-opc.c: New file.
2414 * s12z-opc.h: New file.
2415 * s12z-dis.c: Removed all code not directly related to display
2416 of instructions. Used the interface provided by the new files
2418 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2419 * Makefile.in: Regenerate.
2420 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2421 * configure: Regenerate.
2423 2019-01-01 Alan Modra <amodra@gmail.com>
2425 Update year range in copyright notice of all files.
2427 For older changes see ChangeLog-2018
2429 Copyright (C) 2019 Free Software Foundation, Inc.
2431 Copying and distribution of this file, with or without modification,
2432 are permitted in any medium without royalty provided the copyright
2433 notice and this notice are preserved.
2439 version-control: never