1 2019-12-05 Alan Modra <amodra@gmail.com>
4 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
5 (struct string_buf): New.
6 (strbuf): New function.
7 (get_field): Use strbuf rather than strdup of local temp.
8 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
9 (get_field_rfsl, get_field_imm15): Likewise.
10 (get_field_rd, get_field_r1, get_field_r2): Update macros.
11 (get_field_special): Likewise. Don't strcpy spr. Formatting.
12 (print_insn_microblaze): Formatting. Init and pass string_buf to
15 2019-12-04 Jan Beulich <jbeulich@suse.com>
17 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
18 * i386-tbl.h: Re-generate.
20 2019-12-04 Jan Beulich <jbeulich@suse.com>
22 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
24 2019-12-04 Jan Beulich <jbeulich@suse.com>
26 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
28 (xbegin): Drop DefaultSize.
29 * i386-tbl.h: Re-generate.
31 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
33 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
34 Change the coproc CRC conditions to use the extension
35 feature set, second word, base on ARM_EXT2_CRC.
37 2019-11-14 Jan Beulich <jbeulich@suse.com>
39 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
40 * i386-tbl.h: Re-generate.
42 2019-11-14 Jan Beulich <jbeulich@suse.com>
44 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
45 JumpInterSegment, and JumpAbsolute entries.
46 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
47 JUMP_ABSOLUTE): Define.
48 (struct i386_opcode_modifier): Extend jump field to 3 bits.
49 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
51 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
52 JumpInterSegment): Define.
53 * i386-tbl.h: Re-generate.
55 2019-11-14 Jan Beulich <jbeulich@suse.com>
57 * i386-gen.c (operand_type_init): Remove
58 OPERAND_TYPE_JUMPABSOLUTE entry.
59 (opcode_modifiers): Add JumpAbsolute entry.
60 (operand_types): Remove JumpAbsolute entry.
61 * i386-opc.h (JumpAbsolute): Move between enums.
62 (struct i386_opcode_modifier): Add jumpabsolute field.
63 (union i386_operand_type): Remove jumpabsolute field.
64 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
65 * i386-init.h, i386-tbl.h: Re-generate.
67 2019-11-14 Jan Beulich <jbeulich@suse.com>
69 * i386-gen.c (opcode_modifiers): Add AnySize entry.
70 (operand_types): Remove AnySize entry.
71 * i386-opc.h (AnySize): Move between enums.
72 (struct i386_opcode_modifier): Add anysize field.
73 (OTUnused): Un-comment.
74 (union i386_operand_type): Remove anysize field.
75 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
76 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
77 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
79 * i386-tbl.h: Re-generate.
81 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
83 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
84 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
85 use the floating point register (FPR).
87 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
89 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
91 (is_mve_encoding_conflict): Update cmode conflict checks for
94 2019-11-12 Jan Beulich <jbeulich@suse.com>
96 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
98 (operand_types): Remove EsSeg entry.
99 (main): Replace stale use of OTMax.
100 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
101 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
103 (OTUnused): Comment out.
104 (union i386_operand_type): Remove esseg field.
105 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
106 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
107 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
108 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
109 * i386-init.h, i386-tbl.h: Re-generate.
111 2019-11-12 Jan Beulich <jbeulich@suse.com>
113 * i386-gen.c (operand_instances): Add RegB entry.
114 * i386-opc.h (enum operand_instance): Add RegB.
115 * i386-opc.tbl (RegC, RegD, RegB): Define.
116 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
117 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
118 monitorx, mwaitx): Drop ImmExt and convert encodings
120 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
121 (edx, rdx): Add Instance=RegD.
122 (ebx, rbx): Add Instance=RegB.
123 * i386-tbl.h: Re-generate.
125 2019-11-12 Jan Beulich <jbeulich@suse.com>
127 * i386-gen.c (operand_type_init): Adjust
128 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
129 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
130 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
131 (operand_instances): New.
132 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
133 (output_operand_type): New parameter "instance". Process it.
134 (process_i386_operand_type): New local variable "instance".
135 (main): Adjust static assertions.
136 * i386-opc.h (INSTANCE_WIDTH): Define.
137 (enum operand_instance): New.
138 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
139 (union i386_operand_type): Replace acc, inoutportreg, and
140 shiftcount by instance.
141 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
142 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
144 * i386-init.h, i386-tbl.h: Re-generate.
146 2019-11-11 Jan Beulich <jbeulich@suse.com>
148 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
149 smaxp/sminp entries' "tied_operand" field to 2.
151 2019-11-11 Jan Beulich <jbeulich@suse.com>
153 * aarch64-opc.c (operand_general_constraint_met_p): Replace
154 "index" local variable by that of the already existing "num".
156 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
159 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
160 * i386-tbl.h: Regenerated.
162 2019-11-08 Jan Beulich <jbeulich@suse.com>
164 * i386-gen.c (operand_type_init): Add Class= to
165 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
166 OPERAND_TYPE_REGBND entry.
167 (operand_classes): Add RegMask and RegBND entries.
168 (operand_types): Drop RegMask and RegBND entry.
169 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
170 (RegMask, RegBND): Delete.
171 (union i386_operand_type): Remove regmask and regbnd fields.
172 * i386-opc.tbl (RegMask, RegBND): Define.
173 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
175 * i386-init.h, i386-tbl.h: Re-generate.
177 2019-11-08 Jan Beulich <jbeulich@suse.com>
179 * i386-gen.c (operand_type_init): Add Class= to
180 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
181 OPERAND_TYPE_REGZMM entries.
182 (operand_classes): Add RegMMX and RegSIMD entries.
183 (operand_types): Drop RegMMX and RegSIMD entries.
184 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
185 (RegMMX, RegSIMD): Delete.
186 (union i386_operand_type): Remove regmmx and regsimd fields.
187 * i386-opc.tbl (RegMMX): Define.
188 (RegXMM, RegYMM, RegZMM): Add Class=.
189 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
191 * i386-init.h, i386-tbl.h: Re-generate.
193 2019-11-08 Jan Beulich <jbeulich@suse.com>
195 * i386-gen.c (operand_type_init): Add Class= to
196 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
198 (operand_classes): Add RegCR, RegDR, and RegTR entries.
199 (operand_types): Drop Control, Debug, and Test entries.
200 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
201 (Control, Debug, Test): Delete.
202 (union i386_operand_type): Remove control, debug, and test
204 * i386-opc.tbl (Control, Debug, Test): Define.
205 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
206 Class=RegDR, and Test by Class=RegTR.
207 * i386-init.h, i386-tbl.h: Re-generate.
209 2019-11-08 Jan Beulich <jbeulich@suse.com>
211 * i386-gen.c (operand_type_init): Add Class= to
212 OPERAND_TYPE_SREG entry.
213 (operand_classes): Add SReg entry.
214 (operand_types): Drop SReg entry.
215 * i386-opc.h (enum operand_class): Add SReg.
217 (union i386_operand_type): Remove sreg field.
218 * i386-opc.tbl (SReg): Define.
219 * i386-reg.tbl: Replace SReg by Class=SReg.
220 * i386-init.h, i386-tbl.h: Re-generate.
222 2019-11-08 Jan Beulich <jbeulich@suse.com>
224 * i386-gen.c (operand_type_init): Add Class=. New
225 OPERAND_TYPE_ANYIMM entry.
226 (operand_classes): New.
227 (operand_types): Drop Reg entry.
228 (output_operand_type): New parameter "class". Process it.
229 (process_i386_operand_type): New local variable "class".
230 (main): Adjust static assertions.
231 * i386-opc.h (CLASS_WIDTH): Define.
232 (enum operand_class): New.
233 (Reg): Replace by Class. Adjust comment.
234 (union i386_operand_type): Replace reg by class.
235 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
237 * i386-reg.tbl: Replace Reg by Class=Reg.
238 * i386-init.h: Re-generate.
240 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
242 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
243 (aarch64_opcode_table): Add data gathering hint mnemonic.
244 * opcodes/aarch64-dis-2.c: Account for new instruction.
246 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
248 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
251 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
253 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
254 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
255 aarch64_feature_f64mm): New feature sets.
256 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
257 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
259 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
261 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
262 (OP_SVE_QQQ): New qualifier.
263 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
264 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
265 the movprfx constraint.
266 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
267 (aarch64_opcode_table): Define new instructions smmla,
268 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
270 * aarch64-opc.c (operand_general_constraint_met_p): Handle
271 AARCH64_OPND_SVE_ADDR_RI_S4x32.
272 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
273 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
274 Account for new instructions.
275 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
277 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
279 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
280 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
282 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
284 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
285 (neon_opcodes): Add bfloat SIMD instructions.
286 (print_insn_coprocessor): Add new control character %b to print
287 condition code without checking cp_num.
288 (print_insn_neon): Account for BFloat16 instructions that have no
289 special top-byte handling.
291 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
292 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
294 * arm-dis.c (print_insn_coprocessor,
295 print_insn_generic_coprocessor): Create wrapper functions around
296 the implementation of the print_insn_coprocessor control codes.
297 (print_insn_coprocessor_1): Original print_insn_coprocessor
298 function that now takes which array to look at as an argument.
299 (print_insn_arm): Use both print_insn_coprocessor and
300 print_insn_generic_coprocessor.
301 (print_insn_thumb32): As above.
303 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
304 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
306 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
307 in reglane special case.
308 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
309 aarch64_find_next_opcode): Account for new instructions.
310 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
311 in reglane special case.
312 * aarch64-opc.c (struct operand_qualifier_data): Add data for
313 new AARCH64_OPND_QLF_S_2H qualifier.
314 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
315 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
316 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
318 (BFLOAT_SVE, BFLOAT): New feature set macros.
319 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
321 (aarch64_opcode_table): Define new instructions bfdot,
322 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
325 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
326 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
328 * aarch64-tbl.h (ARMV8_6): New macro.
330 2019-11-07 Jan Beulich <jbeulich@suse.com>
332 * i386-dis.c (prefix_table): Add mcommit.
333 (rm_table): Add rdpru.
334 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
335 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
336 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
337 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
338 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
339 * i386-opc.tbl (mcommit, rdpru): New.
340 * i386-init.h, i386-tbl.h: Re-generate.
342 2019-11-07 Jan Beulich <jbeulich@suse.com>
344 * i386-dis.c (OP_Mwait): Drop local variable "names", use
346 (OP_Monitor): Drop local variable "op1_names", re-purpose
347 "names" for it instead, and replace former "names" uses by
350 2019-11-07 Jan Beulich <jbeulich@suse.com>
353 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
355 * opcodes/i386-tbl.h: Re-generate.
357 2019-11-05 Jan Beulich <jbeulich@suse.com>
359 * i386-dis.c (OP_Mwaitx): Delete.
360 (prefix_table): Use OP_Mwait for mwaitx entry.
361 (OP_Mwait): Also handle mwaitx.
363 2019-11-05 Jan Beulich <jbeulich@suse.com>
365 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
366 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
367 (prefix_table): Add respective entries.
368 (rm_table): Link to those entries.
370 2019-11-05 Jan Beulich <jbeulich@suse.com>
372 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
373 (REG_0F1C_P_0_MOD_0): ... this.
374 (REG_0F1E_MOD_3): Rename to ...
375 (REG_0F1E_P_1_MOD_3): ... this.
376 (RM_0F01_REG_5): Rename to ...
377 (RM_0F01_REG_5_MOD_3): ... this.
378 (RM_0F01_REG_7): Rename to ...
379 (RM_0F01_REG_7_MOD_3): ... this.
380 (RM_0F1E_MOD_3_REG_7): Rename to ...
381 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
382 (RM_0FAE_REG_6): Rename to ...
383 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
384 (RM_0FAE_REG_7): Rename to ...
385 (RM_0FAE_REG_7_MOD_3): ... this.
386 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
387 (PREFIX_0F01_REG_5_MOD_0): ... this.
388 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
389 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
390 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
391 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
392 (PREFIX_0FAE_REG_0): Rename to ...
393 (PREFIX_0FAE_REG_0_MOD_3): ... this.
394 (PREFIX_0FAE_REG_1): Rename to ...
395 (PREFIX_0FAE_REG_1_MOD_3): ... this.
396 (PREFIX_0FAE_REG_2): Rename to ...
397 (PREFIX_0FAE_REG_2_MOD_3): ... this.
398 (PREFIX_0FAE_REG_3): Rename to ...
399 (PREFIX_0FAE_REG_3_MOD_3): ... this.
400 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
401 (PREFIX_0FAE_REG_4_MOD_0): ... this.
402 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
403 (PREFIX_0FAE_REG_4_MOD_3): ... this.
404 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
405 (PREFIX_0FAE_REG_5_MOD_0): ... this.
406 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
407 (PREFIX_0FAE_REG_5_MOD_3): ... this.
408 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
409 (PREFIX_0FAE_REG_6_MOD_0): ... this.
410 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
411 (PREFIX_0FAE_REG_6_MOD_3): ... this.
412 (PREFIX_0FAE_REG_7): Rename to ...
413 (PREFIX_0FAE_REG_7_MOD_0): ... this.
414 (PREFIX_MOD_0_0FC3): Rename to ...
415 (PREFIX_0FC3_MOD_0): ... this.
416 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
417 (PREFIX_0FC7_REG_6_MOD_0): ... this.
418 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
419 (PREFIX_0FC7_REG_6_MOD_3): ... this.
420 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
421 (PREFIX_0FC7_REG_7_MOD_3): ... this.
422 (reg_table, prefix_table, mod_table, rm_table): Adjust
425 2019-11-04 Nick Clifton <nickc@redhat.com>
427 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
428 of a v850 system register. Move the v850_sreg_names array into
430 (get_v850_reg_name): Likewise for ordinary register names.
431 (get_v850_vreg_name): Likewise for vector register names.
432 (get_v850_cc_name): Likewise for condition codes.
433 * get_v850_float_cc_name): Likewise for floating point condition
435 (get_v850_cacheop_name): Likewise for cache-ops.
436 (get_v850_prefop_name): Likewise for pref-ops.
437 (disassemble): Use the new accessor functions.
439 2019-10-30 Delia Burduv <delia.burduv@arm.com>
441 * aarch64-opc.c (print_immediate_offset_address): Don't print the
442 immediate for the writeback form of ldraa/ldrab if it is 0.
443 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
444 * aarch64-opc-2.c: Regenerated.
446 2019-10-30 Jan Beulich <jbeulich@suse.com>
448 * i386-gen.c (operand_type_shorthands): Delete.
449 (operand_type_init): Expand previous shorthands.
450 (set_bitfield_from_shorthand): Rename back to ...
451 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
452 of operand_type_init[].
453 (set_bitfield): Adjust call to the above function.
454 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
455 RegXMM, RegYMM, RegZMM): Define.
456 * i386-reg.tbl: Expand prior shorthands.
458 2019-10-30 Jan Beulich <jbeulich@suse.com>
460 * i386-gen.c (output_i386_opcode): Change order of fields
462 * i386-opc.h (struct insn_template): Move operands field.
463 Convert extension_opcode field to unsigned short.
464 * i386-tbl.h: Re-generate.
466 2019-10-30 Jan Beulich <jbeulich@suse.com>
468 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
470 * i386-opc.h (W): Extend comment.
471 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
472 general purpose variants not allowing for byte operands.
473 * i386-tbl.h: Re-generate.
475 2019-10-29 Nick Clifton <nickc@redhat.com>
477 * tic30-dis.c (print_branch): Correct size of operand array.
479 2019-10-29 Nick Clifton <nickc@redhat.com>
481 * d30v-dis.c (print_insn): Check that operand index is valid
482 before attempting to access the operands array.
484 2019-10-29 Nick Clifton <nickc@redhat.com>
486 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
487 locating the bit to be tested.
489 2019-10-29 Nick Clifton <nickc@redhat.com>
491 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
493 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
494 (print_insn_s12z): Check for illegal size values.
496 2019-10-28 Nick Clifton <nickc@redhat.com>
498 * csky-dis.c (csky_chars_to_number): Check for a negative
499 count. Use an unsigned integer to construct the return value.
501 2019-10-28 Nick Clifton <nickc@redhat.com>
503 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
504 operand buffer. Set value to 15 not 13.
505 (get_register_operand): Use OPERAND_BUFFER_LEN.
506 (get_indirect_operand): Likewise.
507 (print_two_operand): Likewise.
508 (print_three_operand): Likewise.
509 (print_oar_insn): Likewise.
511 2019-10-28 Nick Clifton <nickc@redhat.com>
513 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
514 (bit_extract_simple): Likewise.
515 (bit_copy): Likewise.
516 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
517 index_offset array are not accessed.
519 2019-10-28 Nick Clifton <nickc@redhat.com>
521 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
524 2019-10-25 Nick Clifton <nickc@redhat.com>
526 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
527 access to opcodes.op array element.
529 2019-10-23 Nick Clifton <nickc@redhat.com>
531 * rx-dis.c (get_register_name): Fix spelling typo in error
533 (get_condition_name, get_flag_name, get_double_register_name)
534 (get_double_register_high_name, get_double_register_low_name)
535 (get_double_control_register_name, get_double_condition_name)
536 (get_opsize_name, get_size_name): Likewise.
538 2019-10-22 Nick Clifton <nickc@redhat.com>
540 * rx-dis.c (get_size_name): New function. Provides safe
541 access to name array.
542 (get_opsize_name): Likewise.
543 (print_insn_rx): Use the accessor functions.
545 2019-10-16 Nick Clifton <nickc@redhat.com>
547 * rx-dis.c (get_register_name): New function. Provides safe
548 access to name array.
549 (get_condition_name, get_flag_name, get_double_register_name)
550 (get_double_register_high_name, get_double_register_low_name)
551 (get_double_control_register_name, get_double_condition_name):
553 (print_insn_rx): Use the accessor functions.
555 2019-10-09 Nick Clifton <nickc@redhat.com>
558 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
561 2019-10-07 Jan Beulich <jbeulich@suse.com>
563 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
564 (cmpsd): Likewise. Move EsSeg to other operand.
565 * opcodes/i386-tbl.h: Re-generate.
567 2019-09-23 Alan Modra <amodra@gmail.com>
569 * m68k-dis.c: Include cpu-m68k.h
571 2019-09-23 Alan Modra <amodra@gmail.com>
573 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
574 "elf/mips.h" earlier.
576 2018-09-20 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
581 * i386-tbl.h: Re-generate.
583 2019-09-18 Alan Modra <amodra@gmail.com>
585 * arc-ext.c: Update throughout for bfd section macro changes.
587 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
589 * Makefile.in: Re-generate.
590 * configure: Re-generate.
592 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
594 * riscv-opc.c (riscv_opcodes): Change subset field
595 to insn_class field for all instructions.
596 (riscv_insn_types): Likewise.
598 2019-09-16 Phil Blundell <pb@pbcl.net>
600 * configure: Regenerated.
602 2019-09-10 Miod Vallat <miod@online.fr>
605 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
607 2019-09-09 Phil Blundell <pb@pbcl.net>
609 binutils 2.33 branch created.
611 2019-09-03 Nick Clifton <nickc@redhat.com>
614 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
615 greater than zero before indexing via (bufcnt -1).
617 2019-09-03 Nick Clifton <nickc@redhat.com>
620 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
621 (MAX_SPEC_REG_NAME_LEN): Define.
622 (struct mmix_dis_info): Use defined constants for array lengths.
623 (get_reg_name): New function.
624 (get_sprec_reg_name): New function.
625 (print_insn_mmix): Use new functions.
627 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
629 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
630 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
631 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
633 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
635 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
636 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
637 (aarch64_sys_reg_supported_p): Update checks for the above.
639 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
641 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
642 cases MVE_SQRSHRL and MVE_UQRSHLL.
643 (print_insn_mve): Add case for specifier 'k' to check
644 specific bit of the instruction.
646 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
649 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
650 encountering an unknown machine type.
651 (print_insn_arc): Handle arc_insn_length returning 0. In error
652 cases return -1 rather than calling abort.
654 2019-08-07 Jan Beulich <jbeulich@suse.com>
656 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
657 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
659 * i386-tbl.h: Re-generate.
661 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
663 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
666 2019-07-30 Mel Chen <mel.chen@sifive.com>
668 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
669 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
671 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
674 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
676 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
677 and MPY class instructions.
678 (parse_option): Add nps400 option.
679 (print_arc_disassembler_options): Add nps400 info.
681 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
683 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
686 * arc-opc.c (RAD_CHK): Add.
687 * arc-tbl.h: Regenerate.
689 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
691 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
692 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
694 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
696 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
697 instructions as UNPREDICTABLE.
699 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
701 * bpf-desc.c: Regenerated.
703 2019-07-17 Jan Beulich <jbeulich@suse.com>
705 * i386-gen.c (static_assert): Define.
707 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
708 (Opcode_Modifier_Num): ... this.
711 2019-07-16 Jan Beulich <jbeulich@suse.com>
713 * i386-gen.c (operand_types): Move RegMem ...
714 (opcode_modifiers): ... here.
715 * i386-opc.h (RegMem): Move to opcode modifer enum.
716 (union i386_operand_type): Move regmem field ...
717 (struct i386_opcode_modifier): ... here.
718 * i386-opc.tbl (RegMem): Define.
719 (mov, movq): Move RegMem on segment, control, debug, and test
721 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
722 to non-SSE2AVX flavor.
723 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
724 Move RegMem on register only flavors. Drop IgnoreSize from
725 legacy encoding flavors.
726 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
728 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
729 register only flavors.
730 (vmovd): Move RegMem and drop IgnoreSize on register only
731 flavor. Change opcode and operand order to store form.
732 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
734 2019-07-16 Jan Beulich <jbeulich@suse.com>
736 * i386-gen.c (operand_type_init, operand_types): Replace SReg
738 * i386-opc.h (SReg2, SReg3): Replace by ...
740 (union i386_operand_type): Replace sreg fields.
741 * i386-opc.tbl (mov, ): Use SReg.
742 (push, pop): Likewies. Drop i386 and x86-64 specific segment
744 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
745 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
747 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
749 * bpf-desc.c: Regenerate.
750 * bpf-opc.c: Likewise.
751 * bpf-opc.h: Likewise.
753 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
755 * bpf-desc.c: Regenerate.
756 * bpf-opc.c: Likewise.
758 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
760 * arm-dis.c (print_insn_coprocessor): Rename index to
763 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
765 * riscv-opc.c (riscv_insn_types): Add r4 type.
767 * riscv-opc.c (riscv_insn_types): Add b and j type.
769 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
770 format for sb type and correct s type.
772 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
774 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
775 SVE FMOV alias of FCPY.
777 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
779 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
780 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
782 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
784 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
785 registers in an instruction prefixed by MOVPRFX.
787 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
789 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
790 sve_size_13 icode to account for variant behaviour of
792 * aarch64-dis-2.c: Regenerate.
793 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
794 sve_size_13 icode to account for variant behaviour of
796 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
797 (OP_SVE_VVV_Q_D): Add new qualifier.
798 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
799 (struct aarch64_opcode): Split pmull{t,b} into those requiring
802 2019-07-01 Jan Beulich <jbeulich@suse.com>
804 * opcodes/i386-gen.c (operand_type_init): Remove
805 OPERAND_TYPE_VEC_IMM4 entry.
806 (operand_types): Remove Vec_Imm4.
807 * opcodes/i386-opc.h (Vec_Imm4): Delete.
808 (union i386_operand_type): Remove vec_imm4.
809 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
810 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
812 2019-07-01 Jan Beulich <jbeulich@suse.com>
814 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
815 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
816 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
817 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
818 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
819 monitorx, mwaitx): Drop ImmExt from operand-less forms.
820 * i386-tbl.h: Re-generate.
822 2019-07-01 Jan Beulich <jbeulich@suse.com>
824 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
826 * i386-tbl.h: Re-generate.
828 2019-07-01 Jan Beulich <jbeulich@suse.com>
830 * i386-opc.tbl (C): New.
831 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
832 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
833 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
834 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
835 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
836 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
837 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
838 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
839 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
840 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
841 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
842 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
843 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
844 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
845 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
846 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
847 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
848 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
849 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
850 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
851 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
852 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
853 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
854 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
855 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
856 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
858 * i386-tbl.h: Re-generate.
860 2019-07-01 Jan Beulich <jbeulich@suse.com>
862 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
864 * i386-tbl.h: Re-generate.
866 2019-07-01 Jan Beulich <jbeulich@suse.com>
868 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
869 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
870 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
871 * i386-tbl.h: Re-generate.
873 2019-07-01 Jan Beulich <jbeulich@suse.com>
875 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
876 Disp8MemShift from register only templates.
877 * i386-tbl.h: Re-generate.
879 2019-07-01 Jan Beulich <jbeulich@suse.com>
881 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
882 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
883 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
884 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
885 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
886 EVEX_W_0F11_P_3_M_1): Delete.
887 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
888 EVEX_W_0F11_P_3): New.
889 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
890 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
891 MOD_EVEX_0F11_PREFIX_3 table entries.
892 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
893 PREFIX_EVEX_0F11 table entries.
894 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
895 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
896 EVEX_W_0F11_P_3_M_{0,1} table entries.
898 2019-07-01 Jan Beulich <jbeulich@suse.com>
900 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
903 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
906 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
907 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
908 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
909 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
910 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
911 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
912 EVEX_LEN_0F38C7_R_6_P_2_W_1.
913 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
914 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
915 PREFIX_EVEX_0F38C6_REG_6 entries.
916 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
917 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
918 EVEX_W_0F38C7_R_6_P_2 entries.
919 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
920 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
921 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
922 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
923 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
924 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
925 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
927 2019-06-27 Jan Beulich <jbeulich@suse.com>
929 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
930 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
931 VEX_LEN_0F2D_P_3): Delete.
932 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
933 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
934 (prefix_table): ... here.
936 2019-06-27 Jan Beulich <jbeulich@suse.com>
938 * i386-dis.c (Iq): Delete.
940 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
942 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
943 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
944 (OP_E_memory): Also honor needindex when deciding whether an
945 address size prefix needs printing.
946 (OP_I): Remove handling of q_mode. Add handling of d_mode.
948 2019-06-26 Jim Wilson <jimw@sifive.com>
951 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
952 Set info->display_endian to info->endian_code.
954 2019-06-25 Jan Beulich <jbeulich@suse.com>
956 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
957 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
958 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
959 OPERAND_TYPE_ACC64 entries.
960 * i386-init.h: Re-generate.
962 2019-06-25 Jan Beulich <jbeulich@suse.com>
964 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
966 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
968 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
970 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
971 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
973 2019-06-25 Jan Beulich <jbeulich@suse.com>
975 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
978 2019-06-25 Jan Beulich <jbeulich@suse.com>
980 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
981 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
983 * i386-opc.tbl (movnti): Add IgnoreSize.
984 * i386-tbl.h: Re-generate.
986 2019-06-25 Jan Beulich <jbeulich@suse.com>
988 * i386-opc.tbl (and): Mark Imm8S form for optimization.
989 * i386-tbl.h: Re-generate.
991 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
993 * i386-dis-evex.h: Break into ...
994 * i386-dis-evex-len.h: New file.
995 * i386-dis-evex-mod.h: Likewise.
996 * i386-dis-evex-prefix.h: Likewise.
997 * i386-dis-evex-reg.h: Likewise.
998 * i386-dis-evex-w.h: Likewise.
999 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1000 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1001 i386-dis-evex-mod.h.
1003 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1006 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1007 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1009 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1010 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1011 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1012 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1013 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1014 EVEX_LEN_0F385B_P_2_W_1.
1015 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1016 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1017 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1018 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1019 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1020 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1021 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1022 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1023 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1024 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1026 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1029 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1030 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1031 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1032 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1033 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1034 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1035 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1036 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1037 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1038 EVEX_LEN_0F3A43_P_2_W_1.
1039 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1040 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1041 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1042 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1043 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1044 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1045 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1046 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1047 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1048 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1049 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1050 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1052 2019-06-14 Nick Clifton <nickc@redhat.com>
1054 * po/fr.po; Updated French translation.
1056 2019-06-13 Stafford Horne <shorne@gmail.com>
1058 * or1k-asm.c: Regenerated.
1059 * or1k-desc.c: Regenerated.
1060 * or1k-desc.h: Regenerated.
1061 * or1k-dis.c: Regenerated.
1062 * or1k-ibld.c: Regenerated.
1063 * or1k-opc.c: Regenerated.
1064 * or1k-opc.h: Regenerated.
1065 * or1k-opinst.c: Regenerated.
1067 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1069 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1071 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1074 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1075 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1076 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1077 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1078 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1079 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1080 EVEX_LEN_0F3A1B_P_2_W_1.
1081 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1082 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1083 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1084 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1085 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1086 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1087 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1088 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1090 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1093 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1094 EVEX.vvvv when disassembling VEX and EVEX instructions.
1095 (OP_VEX): Set vex.register_specifier to 0 after readding
1096 vex.register_specifier.
1097 (OP_Vex_2src_1): Likewise.
1098 (OP_Vex_2src_2): Likewise.
1099 (OP_LWP_E): Likewise.
1100 (OP_EX_Vex): Don't check vex.register_specifier.
1101 (OP_XMM_Vex): Likewise.
1103 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1104 Lili Cui <lili.cui@intel.com>
1106 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1107 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1109 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1110 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1111 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1112 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1113 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1114 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1115 * i386-init.h: Regenerated.
1116 * i386-tbl.h: Likewise.
1118 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1119 Lili Cui <lili.cui@intel.com>
1121 * doc/c-i386.texi: Document enqcmd.
1122 * testsuite/gas/i386/enqcmd-intel.d: New file.
1123 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1124 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1125 * testsuite/gas/i386/enqcmd.d: Likewise.
1126 * testsuite/gas/i386/enqcmd.s: Likewise.
1127 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1128 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1129 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1130 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1131 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1132 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1133 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1136 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1138 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1140 2019-06-03 Alan Modra <amodra@gmail.com>
1142 * ppc-dis.c (prefix_opcd_indices): Correct size.
1144 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1149 * i386-tbl.h: Regenerated.
1151 2019-05-24 Alan Modra <amodra@gmail.com>
1153 * po/POTFILES.in: Regenerate.
1155 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1156 Alan Modra <amodra@gmail.com>
1158 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1159 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1160 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1161 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1162 XTOP>): Define and add entries.
1163 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1164 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1165 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1166 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1168 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1169 Alan Modra <amodra@gmail.com>
1171 * ppc-dis.c (ppc_opts): Add "future" entry.
1172 (PREFIX_OPCD_SEGS): Define.
1173 (prefix_opcd_indices): New array.
1174 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1175 (lookup_prefix): New function.
1176 (print_insn_powerpc): Handle 64-bit prefix instructions.
1177 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1178 (PMRR, POWERXX): Define.
1179 (prefix_opcodes): New instruction table.
1180 (prefix_num_opcodes): New constant.
1182 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1184 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1185 * configure: Regenerated.
1186 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1188 (HFILES): Add bpf-desc.h and bpf-opc.h.
1189 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1190 bpf-ibld.c and bpf-opc.c.
1192 * Makefile.in: Regenerated.
1193 * disassemble.c (ARCH_bpf): Define.
1194 (disassembler): Add case for bfd_arch_bpf.
1195 (disassemble_init_for_target): Likewise.
1196 (enum epbf_isa_attr): Define.
1197 * disassemble.h: extern print_insn_bpf.
1198 * bpf-asm.c: Generated.
1199 * bpf-opc.h: Likewise.
1200 * bpf-opc.c: Likewise.
1201 * bpf-ibld.c: Likewise.
1202 * bpf-dis.c: Likewise.
1203 * bpf-desc.h: Likewise.
1204 * bpf-desc.c: Likewise.
1206 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1208 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1209 and VMSR with the new operands.
1211 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1213 * arm-dis.c (enum mve_instructions): New enum
1214 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1216 (mve_opcodes): New instructions as above.
1217 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1219 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1221 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1223 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1224 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1225 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1226 uqshl, urshrl and urshr.
1227 (is_mve_okay_in_it): Add new instructions to TRUE list.
1228 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1229 (print_insn_mve): Updated to accept new %j,
1230 %<bitfield>m and %<bitfield>n patterns.
1232 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1234 * mips-opc.c (mips_builtin_opcodes): Change source register
1235 constraint for DAUI.
1237 2019-05-20 Nick Clifton <nickc@redhat.com>
1239 * po/fr.po: Updated French translation.
1241 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1242 Michael Collison <michael.collison@arm.com>
1244 * arm-dis.c (thumb32_opcodes): Add new instructions.
1245 (enum mve_instructions): Likewise.
1246 (enum mve_undefined): Add new reasons.
1247 (is_mve_encoding_conflict): Handle new instructions.
1248 (is_mve_undefined): Likewise.
1249 (is_mve_unpredictable): Likewise.
1250 (print_mve_undefined): Likewise.
1251 (print_mve_size): Likewise.
1253 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1254 Michael Collison <michael.collison@arm.com>
1256 * arm-dis.c (thumb32_opcodes): Add new instructions.
1257 (enum mve_instructions): Likewise.
1258 (is_mve_encoding_conflict): Handle new instructions.
1259 (is_mve_undefined): Likewise.
1260 (is_mve_unpredictable): Likewise.
1261 (print_mve_size): Likewise.
1263 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1264 Michael Collison <michael.collison@arm.com>
1266 * arm-dis.c (thumb32_opcodes): Add new instructions.
1267 (enum mve_instructions): Likewise.
1268 (is_mve_encoding_conflict): Likewise.
1269 (is_mve_unpredictable): Likewise.
1270 (print_mve_size): Likewise.
1272 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1273 Michael Collison <michael.collison@arm.com>
1275 * arm-dis.c (thumb32_opcodes): Add new instructions.
1276 (enum mve_instructions): Likewise.
1277 (is_mve_encoding_conflict): Handle new instructions.
1278 (is_mve_undefined): Likewise.
1279 (is_mve_unpredictable): Likewise.
1280 (print_mve_size): Likewise.
1282 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1283 Michael Collison <michael.collison@arm.com>
1285 * arm-dis.c (thumb32_opcodes): Add new instructions.
1286 (enum mve_instructions): Likewise.
1287 (is_mve_encoding_conflict): Handle new instructions.
1288 (is_mve_undefined): Likewise.
1289 (is_mve_unpredictable): Likewise.
1290 (print_mve_size): Likewise.
1291 (print_insn_mve): Likewise.
1293 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1294 Michael Collison <michael.collison@arm.com>
1296 * arm-dis.c (thumb32_opcodes): Add new instructions.
1297 (print_insn_thumb32): Handle new instructions.
1299 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1300 Michael Collison <michael.collison@arm.com>
1302 * arm-dis.c (enum mve_instructions): Add new instructions.
1303 (enum mve_undefined): Add new reasons.
1304 (is_mve_encoding_conflict): Handle new instructions.
1305 (is_mve_undefined): Likewise.
1306 (is_mve_unpredictable): Likewise.
1307 (print_mve_undefined): Likewise.
1308 (print_mve_size): Likewise.
1309 (print_mve_shift_n): Likewise.
1310 (print_insn_mve): Likewise.
1312 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1313 Michael Collison <michael.collison@arm.com>
1315 * arm-dis.c (enum mve_instructions): Add new instructions.
1316 (is_mve_encoding_conflict): Handle new instructions.
1317 (is_mve_unpredictable): Likewise.
1318 (print_mve_rotate): Likewise.
1319 (print_mve_size): Likewise.
1320 (print_insn_mve): Likewise.
1322 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1323 Michael Collison <michael.collison@arm.com>
1325 * arm-dis.c (enum mve_instructions): Add new instructions.
1326 (is_mve_encoding_conflict): Handle new instructions.
1327 (is_mve_unpredictable): Likewise.
1328 (print_mve_size): Likewise.
1329 (print_insn_mve): Likewise.
1331 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1332 Michael Collison <michael.collison@arm.com>
1334 * arm-dis.c (enum mve_instructions): Add new instructions.
1335 (enum mve_undefined): Add new reasons.
1336 (is_mve_encoding_conflict): Handle new instructions.
1337 (is_mve_undefined): Likewise.
1338 (is_mve_unpredictable): Likewise.
1339 (print_mve_undefined): Likewise.
1340 (print_mve_size): Likewise.
1341 (print_insn_mve): Likewise.
1343 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1344 Michael Collison <michael.collison@arm.com>
1346 * arm-dis.c (enum mve_instructions): Add new instructions.
1347 (is_mve_encoding_conflict): Handle new instructions.
1348 (is_mve_undefined): Likewise.
1349 (is_mve_unpredictable): Likewise.
1350 (print_mve_size): Likewise.
1351 (print_insn_mve): Likewise.
1353 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1354 Michael Collison <michael.collison@arm.com>
1356 * arm-dis.c (enum mve_instructions): Add new instructions.
1357 (enum mve_unpredictable): Add new reasons.
1358 (enum mve_undefined): Likewise.
1359 (is_mve_okay_in_it): Handle new isntructions.
1360 (is_mve_encoding_conflict): Likewise.
1361 (is_mve_undefined): Likewise.
1362 (is_mve_unpredictable): Likewise.
1363 (print_mve_vmov_index): Likewise.
1364 (print_simd_imm8): Likewise.
1365 (print_mve_undefined): Likewise.
1366 (print_mve_unpredictable): Likewise.
1367 (print_mve_size): Likewise.
1368 (print_insn_mve): Likewise.
1370 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1371 Michael Collison <michael.collison@arm.com>
1373 * arm-dis.c (enum mve_instructions): Add new instructions.
1374 (enum mve_unpredictable): Add new reasons.
1375 (enum mve_undefined): Likewise.
1376 (is_mve_encoding_conflict): Handle new instructions.
1377 (is_mve_undefined): Likewise.
1378 (is_mve_unpredictable): Likewise.
1379 (print_mve_undefined): Likewise.
1380 (print_mve_unpredictable): Likewise.
1381 (print_mve_rounding_mode): Likewise.
1382 (print_mve_vcvt_size): Likewise.
1383 (print_mve_size): Likewise.
1384 (print_insn_mve): Likewise.
1386 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1387 Michael Collison <michael.collison@arm.com>
1389 * arm-dis.c (enum mve_instructions): Add new instructions.
1390 (enum mve_unpredictable): Add new reasons.
1391 (enum mve_undefined): Likewise.
1392 (is_mve_undefined): Handle new instructions.
1393 (is_mve_unpredictable): Likewise.
1394 (print_mve_undefined): Likewise.
1395 (print_mve_unpredictable): Likewise.
1396 (print_mve_size): Likewise.
1397 (print_insn_mve): Likewise.
1399 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1400 Michael Collison <michael.collison@arm.com>
1402 * arm-dis.c (enum mve_instructions): Add new instructions.
1403 (enum mve_undefined): Add new reasons.
1404 (insns): Add new instructions.
1405 (is_mve_encoding_conflict):
1406 (print_mve_vld_str_addr): New print function.
1407 (is_mve_undefined): Handle new instructions.
1408 (is_mve_unpredictable): Likewise.
1409 (print_mve_undefined): Likewise.
1410 (print_mve_size): Likewise.
1411 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1412 (print_insn_mve): Handle new operands.
1414 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1415 Michael Collison <michael.collison@arm.com>
1417 * arm-dis.c (enum mve_instructions): Add new instructions.
1418 (enum mve_unpredictable): Add new reasons.
1419 (is_mve_encoding_conflict): Handle new instructions.
1420 (is_mve_unpredictable): Likewise.
1421 (mve_opcodes): Add new instructions.
1422 (print_mve_unpredictable): Handle new reasons.
1423 (print_mve_register_blocks): New print function.
1424 (print_mve_size): Handle new instructions.
1425 (print_insn_mve): Likewise.
1427 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1428 Michael Collison <michael.collison@arm.com>
1430 * arm-dis.c (enum mve_instructions): Add new instructions.
1431 (enum mve_unpredictable): Add new reasons.
1432 (enum mve_undefined): Likewise.
1433 (is_mve_encoding_conflict): Handle new instructions.
1434 (is_mve_undefined): Likewise.
1435 (is_mve_unpredictable): Likewise.
1436 (coprocessor_opcodes): Move NEON VDUP from here...
1437 (neon_opcodes): ... to here.
1438 (mve_opcodes): Add new instructions.
1439 (print_mve_undefined): Handle new reasons.
1440 (print_mve_unpredictable): Likewise.
1441 (print_mve_size): Handle new instructions.
1442 (print_insn_neon): Handle vdup.
1443 (print_insn_mve): Handle new operands.
1445 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1446 Michael Collison <michael.collison@arm.com>
1448 * arm-dis.c (enum mve_instructions): Add new instructions.
1449 (enum mve_unpredictable): Add new values.
1450 (mve_opcodes): Add new instructions.
1451 (vec_condnames): New array with vector conditions.
1452 (mve_predicatenames): New array with predicate suffixes.
1453 (mve_vec_sizename): New array with vector sizes.
1454 (enum vpt_pred_state): New enum with vector predication states.
1455 (struct vpt_block): New struct type for vpt blocks.
1456 (vpt_block_state): Global struct to keep track of state.
1457 (mve_extract_pred_mask): New helper function.
1458 (num_instructions_vpt_block): Likewise.
1459 (mark_outside_vpt_block): Likewise.
1460 (mark_inside_vpt_block): Likewise.
1461 (invert_next_predicate_state): Likewise.
1462 (update_next_predicate_state): Likewise.
1463 (update_vpt_block_state): Likewise.
1464 (is_vpt_instruction): Likewise.
1465 (is_mve_encoding_conflict): Add entries for new instructions.
1466 (is_mve_unpredictable): Likewise.
1467 (print_mve_unpredictable): Handle new cases.
1468 (print_instruction_predicate): Likewise.
1469 (print_mve_size): New function.
1470 (print_vec_condition): New function.
1471 (print_insn_mve): Handle vpt blocks and new print operands.
1473 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1475 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1476 8, 14 and 15 for Armv8.1-M Mainline.
1478 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1479 Michael Collison <michael.collison@arm.com>
1481 * arm-dis.c (enum mve_instructions): New enum.
1482 (enum mve_unpredictable): Likewise.
1483 (enum mve_undefined): Likewise.
1484 (struct mopcode32): New struct.
1485 (is_mve_okay_in_it): New function.
1486 (is_mve_architecture): Likewise.
1487 (arm_decode_field): Likewise.
1488 (arm_decode_field_multiple): Likewise.
1489 (is_mve_encoding_conflict): Likewise.
1490 (is_mve_undefined): Likewise.
1491 (is_mve_unpredictable): Likewise.
1492 (print_mve_undefined): Likewise.
1493 (print_mve_unpredictable): Likewise.
1494 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1495 (print_insn_mve): New function.
1496 (print_insn_thumb32): Handle MVE architecture.
1497 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1499 2019-05-10 Nick Clifton <nickc@redhat.com>
1502 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1503 end of the table prematurely.
1505 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1507 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1510 2019-05-11 Alan Modra <amodra@gmail.com>
1512 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1513 when -Mraw is in effect.
1515 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1517 * aarch64-dis-2.c: Regenerate.
1518 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1519 (OP_SVE_BBB): New variant set.
1520 (OP_SVE_DDDD): New variant set.
1521 (OP_SVE_HHH): New variant set.
1522 (OP_SVE_HHHU): New variant set.
1523 (OP_SVE_SSS): New variant set.
1524 (OP_SVE_SSSU): New variant set.
1525 (OP_SVE_SHH): New variant set.
1526 (OP_SVE_SBBU): New variant set.
1527 (OP_SVE_DSS): New variant set.
1528 (OP_SVE_DHHU): New variant set.
1529 (OP_SVE_VMV_HSD_BHS): New variant set.
1530 (OP_SVE_VVU_HSD_BHS): New variant set.
1531 (OP_SVE_VVVU_SD_BH): New variant set.
1532 (OP_SVE_VVVU_BHSD): New variant set.
1533 (OP_SVE_VVV_QHD_DBS): New variant set.
1534 (OP_SVE_VVV_HSD_BHS): New variant set.
1535 (OP_SVE_VVV_HSD_BHS2): New variant set.
1536 (OP_SVE_VVV_BHS_HSD): New variant set.
1537 (OP_SVE_VV_BHS_HSD): New variant set.
1538 (OP_SVE_VVV_SD): New variant set.
1539 (OP_SVE_VVU_BHS_HSD): New variant set.
1540 (OP_SVE_VZVV_SD): New variant set.
1541 (OP_SVE_VZVV_BH): New variant set.
1542 (OP_SVE_VZV_SD): New variant set.
1543 (aarch64_opcode_table): Add sve2 instructions.
1545 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1547 * aarch64-asm-2.c: Regenerated.
1548 * aarch64-dis-2.c: Regenerated.
1549 * aarch64-opc-2.c: Regenerated.
1550 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1551 for SVE_SHLIMM_UNPRED_22.
1552 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1553 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1556 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1558 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1559 sve_size_tsz_bhs iclass encode.
1560 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1561 sve_size_tsz_bhs iclass decode.
1563 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1565 * aarch64-asm-2.c: Regenerated.
1566 * aarch64-dis-2.c: Regenerated.
1567 * aarch64-opc-2.c: Regenerated.
1568 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1569 for SVE_Zm4_11_INDEX.
1570 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1571 (fields): Handle SVE_i2h field.
1572 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1573 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1575 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1577 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1578 sve_shift_tsz_bhsd iclass encode.
1579 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1580 sve_shift_tsz_bhsd iclass decode.
1582 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1584 * aarch64-asm-2.c: Regenerated.
1585 * aarch64-dis-2.c: Regenerated.
1586 * aarch64-opc-2.c: Regenerated.
1587 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1588 (aarch64_encode_variant_using_iclass): Handle
1589 sve_shift_tsz_hsd iclass encode.
1590 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1591 sve_shift_tsz_hsd iclass decode.
1592 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1593 for SVE_SHRIMM_UNPRED_22.
1594 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1595 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1598 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1600 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1601 sve_size_013 iclass encode.
1602 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1603 sve_size_013 iclass decode.
1605 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1607 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1608 sve_size_bh iclass encode.
1609 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1610 sve_size_bh iclass decode.
1612 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1614 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1615 sve_size_sd2 iclass encode.
1616 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1617 sve_size_sd2 iclass decode.
1618 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1619 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1621 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1623 * aarch64-asm-2.c: Regenerated.
1624 * aarch64-dis-2.c: Regenerated.
1625 * aarch64-opc-2.c: Regenerated.
1626 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1628 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1629 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1631 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1633 * aarch64-asm-2.c: Regenerated.
1634 * aarch64-dis-2.c: Regenerated.
1635 * aarch64-opc-2.c: Regenerated.
1636 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1637 for SVE_Zm3_11_INDEX.
1638 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1639 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1640 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1642 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1644 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1646 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1647 sve_size_hsd2 iclass encode.
1648 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1649 sve_size_hsd2 iclass decode.
1650 * aarch64-opc.c (fields): Handle SVE_size field.
1651 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1653 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1658 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1660 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1661 (fields): Handle SVE_rot3 field.
1662 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1663 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1665 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1667 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1670 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1673 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1674 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1675 aarch64_feature_sve2bitperm): New feature sets.
1676 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1677 for feature set addresses.
1678 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1679 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1681 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1682 Faraz Shahbazker <fshahbazker@wavecomp.com>
1684 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1685 argument and set ASE_EVA_R6 appropriately.
1686 (set_default_mips_dis_options): Pass ISA to above.
1687 (parse_mips_dis_option): Likewise.
1688 * mips-opc.c (EVAR6): New macro.
1689 (mips_builtin_opcodes): Add llwpe, scwpe.
1691 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1693 * aarch64-asm-2.c: Regenerated.
1694 * aarch64-dis-2.c: Regenerated.
1695 * aarch64-opc-2.c: Regenerated.
1696 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1697 AARCH64_OPND_TME_UIMM16.
1698 (aarch64_print_operand): Likewise.
1699 * aarch64-tbl.h (QL_IMM_NIL): New.
1702 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1704 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1706 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1708 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1709 Faraz Shahbazker <fshahbazker@wavecomp.com>
1711 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1713 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1715 * s12z-opc.h: Add extern "C" bracketing to help
1716 users who wish to use this interface in c++ code.
1718 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1720 * s12z-opc.c (bm_decode): Handle bit map operations with the
1723 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1725 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1726 specifier. Add entries for VLDR and VSTR of system registers.
1727 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1728 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1729 of %J and %K format specifier.
1731 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1733 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1734 Add new entries for VSCCLRM instruction.
1735 (print_insn_coprocessor): Handle new %C format control code.
1737 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1739 * arm-dis.c (enum isa): New enum.
1740 (struct sopcode32): New structure.
1741 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1742 set isa field of all current entries to ANY.
1743 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1744 Only match an entry if its isa field allows the current mode.
1746 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1748 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1750 (print_insn_thumb32): Add logic to print %n CLRM register list.
1752 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1754 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1757 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1759 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1760 (print_insn_thumb32): Edit the switch case for %Z.
1762 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1764 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1766 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1768 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1770 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1772 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1774 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1776 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1777 Arm register with r13 and r15 unpredictable.
1778 (thumb32_opcodes): New instructions for bfx and bflx.
1780 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1782 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1784 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1786 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1788 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1790 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1792 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1794 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1796 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1798 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1799 "optr". ("operator" is a reserved word in c++).
1801 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1803 * aarch64-opc.c (aarch64_print_operand): Add case for
1805 (verify_constraints): Likewise.
1806 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1807 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1808 to accept Rt|SP as first operand.
1809 (AARCH64_OPERANDS): Add new Rt_SP.
1810 * aarch64-asm-2.c: Regenerated.
1811 * aarch64-dis-2.c: Regenerated.
1812 * aarch64-opc-2.c: Regenerated.
1814 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1816 * aarch64-asm-2.c: Regenerated.
1817 * aarch64-dis-2.c: Likewise.
1818 * aarch64-opc-2.c: Likewise.
1819 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1821 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1823 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1825 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1827 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1828 * i386-init.h: Regenerated.
1830 2019-04-07 Alan Modra <amodra@gmail.com>
1832 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1833 op_separator to control printing of spaces, comma and parens
1834 rather than need_comma, need_paren and spaces vars.
1836 2019-04-07 Alan Modra <amodra@gmail.com>
1839 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1840 (print_insn_neon, print_insn_arm): Likewise.
1842 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1844 * i386-dis-evex.h (evex_table): Updated to support BF16
1846 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1847 and EVEX_W_0F3872_P_3.
1848 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1849 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1850 * i386-opc.h (enum): Add CpuAVX512_BF16.
1851 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1852 * i386-opc.tbl: Add AVX512 BF16 instructions.
1853 * i386-init.h: Regenerated.
1854 * i386-tbl.h: Likewise.
1856 2019-04-05 Alan Modra <amodra@gmail.com>
1858 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1859 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1860 to favour printing of "-" branch hint when using the "y" bit.
1861 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1863 2019-04-05 Alan Modra <amodra@gmail.com>
1865 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1866 opcode until first operand is output.
1868 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1871 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1872 (valid_bo_post_v2): Add support for 'at' branch hints.
1873 (insert_bo): Only error on branch on ctr.
1874 (get_bo_hint_mask): New function.
1875 (insert_boe): Add new 'branch_taken' formal argument. Add support
1876 for inserting 'at' branch hints.
1877 (extract_boe): Add new 'branch_taken' formal argument. Add support
1878 for extracting 'at' branch hints.
1879 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1880 (BOE): Delete operand.
1881 (BOM, BOP): New operands.
1883 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1884 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1885 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1886 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1887 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1888 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1889 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1890 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1891 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1892 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1893 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1894 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1895 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1896 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1897 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1898 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1899 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1900 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1901 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1902 bttarl+>: New extended mnemonics.
1904 2019-03-28 Alan Modra <amodra@gmail.com>
1907 * ppc-opc.c (BTF): Define.
1908 (powerpc_opcodes): Use for mtfsb*.
1909 * ppc-dis.c (print_insn_powerpc): Print fields with both
1910 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1912 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1914 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1915 (mapping_symbol_for_insn): Implement new algorithm.
1916 (print_insn): Remove duplicate code.
1918 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1920 * aarch64-dis.c (print_insn_aarch64):
1923 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1925 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1928 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1930 * aarch64-dis.c (last_stop_offset): New.
1931 (print_insn_aarch64): Use stop_offset.
1933 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1936 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1938 * i386-init.h: Regenerated.
1940 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1943 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1944 vmovdqu16, vmovdqu32 and vmovdqu64.
1945 * i386-tbl.h: Regenerated.
1947 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1949 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1950 from vstrszb, vstrszh, and vstrszf.
1952 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1954 * s390-opc.txt: Add instruction descriptions.
1956 2019-02-08 Jim Wilson <jimw@sifive.com>
1958 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1961 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1963 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1965 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1968 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1969 * aarch64-opc.c (verify_elem_sd): New.
1970 (fields): Add FLD_sz entr.
1971 * aarch64-tbl.h (_SIMD_INSN): New.
1972 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1973 fmulx scalar and vector by element isns.
1975 2019-02-07 Nick Clifton <nickc@redhat.com>
1977 * po/sv.po: Updated Swedish translation.
1979 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1981 * s390-mkopc.c (main): Accept arch13 as cpu string.
1982 * s390-opc.c: Add new instruction formats and instruction opcode
1984 * s390-opc.txt: Add new arch13 instructions.
1986 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1988 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1989 (aarch64_opcode): Change encoding for stg, stzg
1991 * aarch64-asm-2.c: Regenerated.
1992 * aarch64-dis-2.c: Regenerated.
1993 * aarch64-opc-2.c: Regenerated.
1995 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1997 * aarch64-asm-2.c: Regenerated.
1998 * aarch64-dis-2.c: Likewise.
1999 * aarch64-opc-2.c: Likewise.
2000 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2002 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2003 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2005 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2006 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2007 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2008 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2009 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2010 case for ldstgv_indexed.
2011 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2012 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2013 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2014 * aarch64-asm-2.c: Regenerated.
2015 * aarch64-dis-2.c: Regenerated.
2016 * aarch64-opc-2.c: Regenerated.
2018 2019-01-23 Nick Clifton <nickc@redhat.com>
2020 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2022 2019-01-21 Nick Clifton <nickc@redhat.com>
2024 * po/de.po: Updated German translation.
2025 * po/uk.po: Updated Ukranian translation.
2027 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2028 * mips-dis.c (mips_arch_choices): Fix typo in
2029 gs464, gs464e and gs264e descriptors.
2031 2019-01-19 Nick Clifton <nickc@redhat.com>
2033 * configure: Regenerate.
2034 * po/opcodes.pot: Regenerate.
2036 2018-06-24 Nick Clifton <nickc@redhat.com>
2038 2.32 branch created.
2040 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2042 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2044 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2047 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2049 * configure: Regenerate.
2051 2019-01-07 Alan Modra <amodra@gmail.com>
2053 * configure: Regenerate.
2054 * po/POTFILES.in: Regenerate.
2056 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2058 * s12z-opc.c: New file.
2059 * s12z-opc.h: New file.
2060 * s12z-dis.c: Removed all code not directly related to display
2061 of instructions. Used the interface provided by the new files
2063 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2064 * Makefile.in: Regenerate.
2065 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2066 * configure: Regenerate.
2068 2019-01-01 Alan Modra <amodra@gmail.com>
2070 Update year range in copyright notice of all files.
2072 For older changes see ChangeLog-2018
2074 Copyright (C) 2019 Free Software Foundation, Inc.
2076 Copying and distribution of this file, with or without modification,
2077 are permitted in any medium without royalty provided the copyright
2078 notice and this notice are preserved.
2084 version-control: never