opcodes/ChangeLog

   1 2016-12-12  Yao Qi  <yao.qi@linaro.org>
   2
   3         * rl78-dis.c: Include <setjmp.h>.
   4         (struct private): New.
   5         (rl78_get_byte): Check return value of read_memory_func, and
   6         call memory_error_func and OPCODES_SIGLONGJMP on error.
   7         (print_insn_rl78_common): Call OPCODES_SIGJMP.
   8
   9 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  10
  11         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  12
  13 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  14
  15         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  16         than UINT.
  17
  18 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  19
  20         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
  21         to separate `extend' and its uninterpreted argument output.
  22         Separate hexadecimal halves of undecoded extended instructions
  23         output.
  24
  25 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  26
  27         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  28         indentation space across.
  29
  30 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  31
  32         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  33         adjustment for PC-relative operations following MIPS16e compact
  34         jumps or undefined RR/J(AL)R(C) encodings.
  35
  36 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  37
  38         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
  39         variable to `reglane_index'.
  40
  41 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
  42
  43         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
  44
  45 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  46
  47         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
  48
  49 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  50
  51         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  52         members.
  53
  54 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  55
  56         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  57
  58 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  59
  60         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  61         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  62
  63 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  64
  65         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  66
  67 2016-12-01  Nick Clifton  <nickc@redhat.com>
  68
  69         PR binutils/20893
  70         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  71         opcode designator.
  72
  73 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  74
  75         * arc-opc.c (insert_ra_chk): New function.
  76         (insert_rb_chk): Likewise.
  77         (insert_rad): Update text error message.
  78         (insert_rcd): Likewise.
  79         (insert_rhv2): Likewise.
  80         (insert_r0): Likewise.
  81         (insert_r1): Likewise.
  82         (insert_r2): Likewise.
  83         (insert_r3): Likewise.
  84         (insert_sp): Likewise.
  85         (insert_gp): Likewise.
  86         (insert_pcl): Likewise.
  87         (insert_blink): Likewise.
  88         (insert_ilink1): Likewise.
  89         (insert_ilink2): Likewise.
  90         (insert_ras): Likewise.
  91         (insert_rbs): Likewise.
  92         (insert_rcs): Likewise.
  93         (insert_simm3s): Likewise.
  94         (insert_rrange): Likewise.
  95         (insert_fpel): Likewise.
  96         (insert_blinkel): Likewise.
  97         (insert_pcel): Likewise.
  98         (insert_nps_3bit_dst): Likewise.
  99         (insert_nps_3bit_dst_short): Likewise.
 100         (insert_nps_3bit_src2_short): Likewise.
 101         (insert_nps_bitop_size_2b): Likewise.
 102         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 103         (RA_CHK): Define.
 104         (RB): Adjust.
 105         (RB_CHK): Define.
 106         (RC): Adjust.
 107         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 108         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 109         Change first insn argument to check for LP_COUNT usage.
 110         (rem): Likewise.
 111         (ld, ldd): All instructions are LOAD class.  Change first insn
 112         argument to check for LP_COUNT usage.
 113         (st, std): All instructions are STORE class.
 114         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 115         Change first insn argument to check for LP_COUNT usage.
 116         (mov): All instructions are MOVE class.  Change first insn
 117         argument to check for LP_COUNT usage.
 118
 119 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 120
 121         * arc-dis.c (is_compatible_p): Remove function.
 122         (skip_this_opcode): Don't add any decoding class to decode list.
 123         Remove warning.
 124         (find_format_from_table): Go through all opcodes, and warn if we
 125         use a guessed mnemonic.
 126
 127 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 128             Amit Pawar  <amit.pawar@amd.com>
 129
 130         PR binutils/20637
 131         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 132         instructions.
 133
 134 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 135
 136         * configure: Regenerate.
 137
 138 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 139
 140         * sparc-opc.c (HWS_V8): Definition moved from
 141         gas/config/tc-sparc.c.
 142         (HWS_V9): Likewise.
 143         (HWS_VA): Likewise.
 144         (HWS_VB): Likewise.
 145         (HWS_VC): Likewise.
 146         (HWS_VD): Likewise.
 147         (HWS_VE): Likewise.
 148         (HWS_VV): Likewise.
 149         (HWS_VM): Likewise.
 150         (HWS2_VM): Likewise.
 151         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 152         existing entries.
 153
 154 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 155
 156         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 157         instructions.
 158
 159 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 160
 161         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 162         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 163         (aarch64_opcode_table): Add fcmla and fcadd.
 164         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 165         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 166         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 167         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 168         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 169         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 170         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 171         (operand_general_constraint_met_p): Rotate and index range check.
 172         (aarch64_print_operand): Handle rotate operand.
 173         * aarch64-asm-2.c: Regenerate.
 174         * aarch64-dis-2.c: Likewise.
 175         * aarch64-opc-2.c: Likewise.
 176
 177 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 178
 179         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 180         * aarch64-asm-2.c: Regenerate.
 181         * aarch64-dis-2.c: Regenerate.
 182         * aarch64-opc-2.c: Regenerate.
 183
 184 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 185
 186         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 187         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 188         * aarch64-asm-2.c: Regenerate.
 189         * aarch64-dis-2.c: Regenerate.
 190         * aarch64-opc-2.c: Regenerate.
 191
 192 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 193
 194         * aarch64-tbl.h (QL_X1NIL): New.
 195         (arch64_opcode_table): Add ldraa, ldrab.
 196         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 197         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 198         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 199         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 200         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 201         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 202         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 203         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 204         (aarch64_print_operand): Likewise.
 205         * aarch64-asm-2.c: Regenerate.
 206         * aarch64-dis-2.c: Regenerate.
 207         * aarch64-opc-2.c: Regenerate.
 208
 209 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 210
 211         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 212         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 213         * aarch64-asm-2.c: Regenerate.
 214         * aarch64-dis-2.c: Regenerate.
 215         * aarch64-opc-2.c: Regenerate.
 216
 217 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 218
 219         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 220         (AARCH64_OPERANDS): Add Rm_SP.
 221         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 222         * aarch64-asm-2.c: Regenerate.
 223         * aarch64-dis-2.c: Regenerate.
 224         * aarch64-opc-2.c: Regenerate.
 225
 226 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 227
 228         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 229         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 230         autdzb, xpaci, xpacd.
 231         * aarch64-asm-2.c: Regenerate.
 232         * aarch64-dis-2.c: Regenerate.
 233         * aarch64-opc-2.c: Regenerate.
 234
 235 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 236
 237         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 238         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 239         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 240         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 241
 242 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 243
 244         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 245         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 246         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 247         autibsp.
 248         * aarch64-asm-2.c: Regenerate.
 249         * aarch64-dis-2.c: Regenerate.
 250
 251 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 252
 253         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 254
 255 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 256
 257         PR binutils/20799
 258         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 259         * i386-dis.c (EdqwS): Removed.
 260         (dqw_swap_mode): Likewise.
 261         (intel_operand_size): Don't check dqw_swap_mode.
 262         (OP_E_register): Likewise.
 263         (OP_E_memory): Likewise.
 264         (OP_G): Likewise.
 265         (OP_EX): Likewise.
 266         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 267         * i386-tbl.h: Regerated.
 268
 269 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         * i386-opc.tbl: Merge AVX512F vmovq.
 272         * i386-tbl.h: Regerated.
 273
 274 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 275
 276         PR binutils/20701
 277         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 278         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 279         (three_byte_table): Remove THREE_BYTE_0F7A.
 280
 281 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 282
 283         PR binutils/20775
 284         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 285         (FGRPd9_4): Replace 1 with 2.
 286         (FGRPd9_5): Replace 2 with 3.
 287         (FGRPd9_6): Replace 3 with 4.
 288         (FGRPd9_7): Replace 4 with 5.
 289         (FGRPda_5): Replace 5 with 6.
 290         (FGRPdb_4): Replace 6 with 7.
 291         (FGRPde_3): Replace 7 with 8.
 292         (FGRPdf_4): Replace 8 with 9.
 293         (fgrps): Add an entry for Bad_Opcode.
 294
 295 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 296
 297         * arc-opc.c (arc_flag_operands): Add F_DI14.
 298         (arc_flag_classes): Add C_DI14.
 299         * arc-nps400-tbl.h: Add new exc instructions.
 300
 301 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 302
 303         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 304         major opcode 0xa.
 305         * arc-nps-400-tbl.h: Add dcmac instruction.
 306         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 307         (insert_nps_rbdouble_64): Added.
 308         (extract_nps_rbdouble_64): Added.
 309         (insert_nps_proto_size): Added.
 310         (extract_nps_proto_size): Added.
 311
 312 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 313
 314         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 315         relating to long instruction processing, add new limm field.
 316         (OPCODE): Rename to...
 317         (OPCODE_32BIT_INSN): ...this.
 318         (OPCODE_AC): Delete.
 319         (skip_this_opcode): Handle different instruction lengths, update
 320         macro name.
 321         (special_flag_p): Update parameter type.
 322         (find_format_from_table): Update for more instruction lengths.
 323         (find_format_long_instructions): Delete.
 324         (find_format): Update for more instruction lengths.
 325         (arc_insn_length): Likewise.
 326         (extract_operand_value): Update for more instruction lengths.
 327         (operand_iterator_next): Remove code relating to long
 328         instructions.
 329         (arc_opcode_to_insn_type): New function.
 330         (print_insn_arc):Update for more instructions lengths.
 331         * arc-ext.c (extInstruction_t): Change argument type.
 332         * arc-ext.h (extInstruction_t): Change argument type.
 333         * arc-fxi.h: Change type unsigned to unsigned long long
 334         extensively throughout.
 335         * arc-nps400-tbl.h: Add long instructions taken from
 336         arc_long_opcodes table in arc-opc.c.
 337         * arc-opc.c: Update parameter types on insert/extract handlers.
 338         (arc_long_opcodes): Delete.
 339         (arc_num_long_opcodes): Delete.
 340         (arc_opcode_len): Update for more instruction lengths.
 341
 342 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 343
 344         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 345
 346 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 347
 348         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 349         with arc_opcode_len.
 350         (find_format_long_instructions): Likewise.
 351         * arc-opc.c (arc_opcode_len): New function.
 352
 353 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 354
 355         * arc-nps400-tbl.h: Fix some instruction masks.
 356
 357 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         * i386-dis.c (REG_82): Removed.
 360         (X86_64_82_REG_0): Likewise.
 361         (X86_64_82_REG_1): Likewise.
 362         (X86_64_82_REG_2): Likewise.
 363         (X86_64_82_REG_3): Likewise.
 364         (X86_64_82_REG_4): Likewise.
 365         (X86_64_82_REG_5): Likewise.
 366         (X86_64_82_REG_6): Likewise.
 367         (X86_64_82_REG_7): Likewise.
 368         (X86_64_82): New.
 369         (dis386): Use X86_64_82 instead of REG_82.
 370         (reg_table): Remove REG_82.
 371         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 372         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 373         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 374         X86_64_82_REG_7.
 375
 376 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 377
 378         PR binutils/20754
 379         * i386-dis.c (REG_82): New.
 380         (X86_64_82_REG_0): Likewise.
 381         (X86_64_82_REG_1): Likewise.
 382         (X86_64_82_REG_2): Likewise.
 383         (X86_64_82_REG_3): Likewise.
 384         (X86_64_82_REG_4): Likewise.
 385         (X86_64_82_REG_5): Likewise.
 386         (X86_64_82_REG_6): Likewise.
 387         (X86_64_82_REG_7): Likewise.
 388         (dis386): Use REG_82.
 389         (reg_table): Add REG_82.
 390         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 391         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 392         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 393
 394 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 395
 396         * i386-dis.c (REG_82): Renamed to ...
 397         (REG_83): This.
 398         (dis386): Updated.
 399         (reg_table): Likewise.
 400
 401 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 402
 403         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 404         * i386-dis-evex.h (evex_table): Updated.
 405         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 406         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 407         (cpu_flags): Add CpuAVX512_4VNNIW.
 408         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 409         (i386_cpu_flags): Add cpuavx512_4vnniw.
 410         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 411         * i386-init.h: Regenerate.
 412         * i386-tbl.h: Ditto.
 413
 414 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 415
 416         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 417         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 418         * i386-dis-evex.h (evex_table): Updated.
 419         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 420         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 421         (cpu_flags): Add CpuAVX512_4FMAPS.
 422         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 423         * i386-opc.h (AVX512_4FMAP): New.
 424         (i386_cpu_flags): Add cpuavx512_4fmaps.
 425         (ImplicitQuadGroup): New.
 426         (i386_opcode_modifier): Add implicitquadgroup.
 427         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 428         * i386-init.h: Regenerate.
 429         * i386-tbl.h: Ditto.
 430
 431 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 432             Andrew Waterman <andrew@sifive.com>
 433
 434         Add support for RISC-V architecture.
 435         * configure.ac: Add entry for bfd_riscv_arch.
 436         * configure: Regenerate.
 437         * disassemble.c (disassembler): Add support for riscv.
 438         (disassembler_usage): Likewise.
 439         * riscv-dis.c: New file.
 440         * riscv-opc.c: New file.
 441
 442 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 445         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 446         (rm_table): Update the RM_0FAE_REG_7 entry.
 447         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 448         (cpu_flags): Remove CpuPCOMMIT.
 449         * i386-opc.h (CpuPCOMMIT): Removed.
 450         (i386_cpu_flags): Remove cpupcommit.
 451         * i386-opc.tbl: Remove pcommit.
 452         * i386-init.h: Regenerated.
 453         * i386-tbl.h: Likewise.
 454
 455 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         PR binutis/20705
 458         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 459         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 460         32-bit mode.  Don't check vex.register_specifier in 32-bit
 461         mode.
 462         (OP_VEX): Check for invalid mask registers.
 463
 464 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         PR binutis/20699
 467         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 468         sizeflag.
 469
 470 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         PR binutis/20704
 473         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 474
 475 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 476
 477         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 478         local variable to `index_regno'.
 479
 480 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 481
 482         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 483
 484 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 485
 486         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 487         usage on ISA basis.
 488
 489 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 490
 491         PR target/20666
 492         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 493
 494 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 495
 496         PR target/20667
 497         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 498         available.
 499
 500 2016-10-07  Alan Modra  <amodra@gmail.com>
 501
 502         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 503
 504 2016-10-06  Alan Modra  <amodra@gmail.com>
 505
 506         * aarch64-opc.c: Spell fall through comments consistently.
 507         * i386-dis.c: Likewise.
 508         * aarch64-dis.c: Add missing fall through comments.
 509         * aarch64-opc.c: Likewise.
 510         * arc-dis.c: Likewise.
 511         * arm-dis.c: Likewise.
 512         * i386-dis.c: Likewise.
 513         * m68k-dis.c: Likewise.
 514         * mep-asm.c: Likewise.
 515         * ns32k-dis.c: Likewise.
 516         * sh-dis.c: Likewise.
 517         * tic4x-dis.c: Likewise.
 518         * tic6x-dis.c: Likewise.
 519         * vax-dis.c: Likewise.
 520
 521 2016-10-06  Alan Modra  <amodra@gmail.com>
 522
 523         * arc-ext.c (create_map): Add missing break.
 524         * msp430-decode.opc (encode_as): Likewise.
 525         * msp430-decode.c: Regenerate.
 526
 527 2016-10-06  Alan Modra  <amodra@gmail.com>
 528
 529         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 530         * crx-dis.c (print_insn_crx): Likewise.
 531
 532 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 533
 534         PR binutils/20657
 535         * i386-dis.c (putop): Don't assign alt twice.
 536
 537 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 538
 539         PR target/20553
 540         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 541
 542 2016-09-29  Alan Modra  <amodra@gmail.com>
 543
 544         * ppc-opc.c (L): Make compulsory.
 545         (LOPT): New, optional form of L.
 546         (HTM_R): Define as LOPT.
 547         (L0, L1): Delete.
 548         (L32OPT): New, optional for 32-bit L.
 549         (L2OPT): New, 2-bit L for dcbf.
 550         (SVC_LEC): Update.
 551         (L2): Define.
 552         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 553         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 554         <dcbf>: Use L2OPT.
 555         <tlbiel, tlbie>: Use LOPT.
 556         <wclr, wclrall>: Use L2.
 557
 558 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 559
 560         * Makefile.in: Regenerate.
 561         * configure: Likewise.
 562
 563 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 564
 565         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 566         (EXTINSN2OP): Use EXTINSN2OPF.
 567         (bspeekm, bspop, modapp): New extension instructions.
 568         * arc-opc.c (F_DNZ_ND): Define.
 569         (F_DNZ_D): Likewise.
 570         (F_SIZEB1): Changed.
 571         (C_DNZ_D): Define.
 572         (C_HARD): Changed.
 573         * arc-tbl.h (dbnz): New instruction.
 574         (prealloc): Allow it for ARC EM.
 575         (xbfu): Likewise.
 576
 577 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 578
 579         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 580         after commas in addresses.
 581         (aarch64_print_operand): Likewise.
 582
 583 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 584
 585         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 586         rather than "should be" or "expected to be" in error messages.
 587
 588 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 589
 590         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 591         (print_mnemonic_name): ...here.
 592         (print_comment): New function.
 593         (print_aarch64_insn): Call it.
 594         * aarch64-opc.c (aarch64_conds): Add SVE names.
 595         (aarch64_print_operand): Print alternative condition names in
 596         a comment.
 597
 598 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 599
 600         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 601         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 602         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 603         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 604         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 605         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 606         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 607         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 608         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 609         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 610         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 611         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 612         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 613         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 614         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 615         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 616         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 617         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 618         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 619         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 620         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 621         (aarch64_feature_sve): New variable.
 622         (SVE): New macro.
 623         (_SVE_INSN): Likewise.
 624         (aarch64_opcode_table): Add SVE instructions.
 625         * aarch64-opc.h (extract_fields): Declare.
 626         * aarch64-opc-2.c: Regenerate.
 627         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 628         * aarch64-asm-2.c: Regenerate.
 629         * aarch64-dis.c (extract_fields): Make global.
 630         (do_misc_decoding): Handle the new SVE aarch64_ops.
 631         * aarch64-dis-2.c: Regenerate.
 632
 633 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 634
 635         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 636         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 637         aarch64_field_kinds.
 638         * aarch64-opc.c (fields): Add corresponding entries.
 639         * aarch64-asm.c (aarch64_get_variant): New function.
 640         (aarch64_encode_variant_using_iclass): Likewise.
 641         (aarch64_opcode_encode): Call it.
 642         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 643         (aarch64_opcode_decode): Call it.
 644
 645 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 646
 647         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 648         and FP register operands.
 649         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 650         (FLD_SVE_Vn): New aarch64_field_kinds.
 651         * aarch64-opc.c (fields): Add corresponding entries.
 652         (aarch64_print_operand): Handle the new SVE core and FP register
 653         operands.
 654         * aarch64-opc-2.c: Regenerate.
 655         * aarch64-asm-2.c: Likewise.
 656         * aarch64-dis-2.c: Likewise.
 657
 658 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 659
 660         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 661         immediate operands.
 662         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 663         * aarch64-opc.c (fields): Add corresponding entry.
 664         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 665         operands.
 666         (aarch64_print_operand): Likewise.
 667         * aarch64-opc-2.c: Regenerate.
 668         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 669         (ins_sve_float_zero_one): New inserters.
 670         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 671         (aarch64_ins_sve_float_half_two): Likewise.
 672         (aarch64_ins_sve_float_zero_one): Likewise.
 673         * aarch64-asm-2.c: Regenerate.
 674         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 675         (ext_sve_float_zero_one): New extractors.
 676         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 677         (aarch64_ext_sve_float_half_two): Likewise.
 678         (aarch64_ext_sve_float_zero_one): Likewise.
 679         * aarch64-dis-2.c: Regenerate.
 680
 681 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 682
 683         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 684         integer immediate operands.
 685         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 686         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 687         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 688         * aarch64-opc.c (fields): Add corresponding entries.
 689         (operand_general_constraint_met_p): Handle the new SVE integer
 690         immediate operands.
 691         (aarch64_print_operand): Likewise.
 692         (aarch64_sve_dupm_mov_immediate_p): New function.
 693         * aarch64-opc-2.c: Regenerate.
 694         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 695         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 696         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 697         (aarch64_ins_limm): ...here.
 698         (aarch64_ins_inv_limm): New function.
 699         (aarch64_ins_sve_aimm): Likewise.
 700         (aarch64_ins_sve_asimm): Likewise.
 701         (aarch64_ins_sve_limm_mov): Likewise.
 702         (aarch64_ins_sve_shlimm): Likewise.
 703         (aarch64_ins_sve_shrimm): Likewise.
 704         * aarch64-asm-2.c: Regenerate.
 705         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 706         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 707         * aarch64-dis.c (decode_limm): New function, split out from...
 708         (aarch64_ext_limm): ...here.
 709         (aarch64_ext_inv_limm): New function.
 710         (decode_sve_aimm): Likewise.
 711         (aarch64_ext_sve_aimm): Likewise.
 712         (aarch64_ext_sve_asimm): Likewise.
 713         (aarch64_ext_sve_limm_mov): Likewise.
 714         (aarch64_top_bit): Likewise.
 715         (aarch64_ext_sve_shlimm): Likewise.
 716         (aarch64_ext_sve_shrimm): Likewise.
 717         * aarch64-dis-2.c: Regenerate.
 718
 719 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 720
 721         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 722         operands.
 723         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 724         the AARCH64_MOD_MUL_VL entry.
 725         (value_aligned_p): Cope with non-power-of-two alignments.
 726         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 727         (print_immediate_offset_address): Likewise.
 728         (aarch64_print_operand): Likewise.
 729         * aarch64-opc-2.c: Regenerate.
 730         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 731         (ins_sve_addr_ri_s9xvl): New inserters.
 732         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 733         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 734         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 735         * aarch64-asm-2.c: Regenerate.
 736         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 737         (ext_sve_addr_ri_s9xvl): New extractors.
 738         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 739         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 740         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 741         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 742         * aarch64-dis-2.c: Regenerate.
 743
 744 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 745
 746         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 747         address operands.
 748         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 749         (FLD_SVE_xs_22): New aarch64_field_kinds.
 750         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 751         (get_operand_specific_data): New function.
 752         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 753         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 754         (operand_general_constraint_met_p): Handle the new SVE address
 755         operands.
 756         (sve_reg): New array.
 757         (get_addr_sve_reg_name): New function.
 758         (aarch64_print_operand): Handle the new SVE address operands.
 759         * aarch64-opc-2.c: Regenerate.
 760         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 761         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 762         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 763         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 764         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 765         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 766         (aarch64_ins_sve_addr_zi_u5): Likewise.
 767         (aarch64_ins_sve_addr_zz): Likewise.
 768         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 769         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 770         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 771         * aarch64-asm-2.c: Regenerate.
 772         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 773         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 774         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 775         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 776         (aarch64_ext_sve_addr_ri_u6): Likewise.
 777         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 778         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 779         (aarch64_ext_sve_addr_zi_u5): Likewise.
 780         (aarch64_ext_sve_addr_zz): Likewise.
 781         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 782         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 783         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 784         * aarch64-dis-2.c: Regenerate.
 785
 786 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 787
 788         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 789         AARCH64_OPND_SVE_PATTERN_SCALED.
 790         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 791         * aarch64-opc.c (fields): Add a corresponding entry.
 792         (set_multiplier_out_of_range_error): New function.
 793         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 794         (operand_general_constraint_met_p): Handle
 795         AARCH64_OPND_SVE_PATTERN_SCALED.
 796         (print_register_offset_address): Use PRIi64 to print the
 797         shift amount.
 798         (aarch64_print_operand): Likewise.  Handle
 799         AARCH64_OPND_SVE_PATTERN_SCALED.
 800         * aarch64-opc-2.c: Regenerate.
 801         * aarch64-asm.h (ins_sve_scale): New inserter.
 802         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 803         * aarch64-asm-2.c: Regenerate.
 804         * aarch64-dis.h (ext_sve_scale): New inserter.
 805         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 806         * aarch64-dis-2.c: Regenerate.
 807
 808 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 809
 810         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 811         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 812         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 813         (FLD_SVE_prfop): Likewise.
 814         * aarch64-opc.c: Include libiberty.h.
 815         (aarch64_sve_pattern_array): New variable.
 816         (aarch64_sve_prfop_array): Likewise.
 817         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 818         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 819         AARCH64_OPND_SVE_PRFOP.
 820         * aarch64-asm-2.c: Regenerate.
 821         * aarch64-dis-2.c: Likewise.
 822         * aarch64-opc-2.c: Likewise.
 823
 824 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 825
 826         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 827         AARCH64_OPND_QLF_P_[ZM].
 828         (aarch64_print_operand): Print /z and /m where appropriate.
 829
 830 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 831
 832         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 833         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 834         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 835         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 836         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 837         * aarch64-opc.c (fields): Add corresponding entries here.
 838         (operand_general_constraint_met_p): Check that SVE register lists
 839         have the correct length.  Check the ranges of SVE index registers.
 840         Check for cases where p8-p15 are used in 3-bit predicate fields.
 841         (aarch64_print_operand): Handle the new SVE operands.
 842         * aarch64-opc-2.c: Regenerate.
 843         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 844         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 845         (aarch64_ins_sve_reglist): Likewise.
 846         * aarch64-asm-2.c: Regenerate.
 847         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 848         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 849         (aarch64_ext_sve_reglist): Likewise.
 850         * aarch64-dis-2.c: Regenerate.
 851
 852 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 855         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 856         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 857         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 858         tied operands.
 859
 860 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 861
 862         * aarch64-opc.c (get_offset_int_reg_name): New function.
 863         (print_immediate_offset_address): Likewise.
 864         (print_register_offset_address): Take the base and offset
 865         registers as parameters.
 866         (aarch64_print_operand): Update caller accordingly.  Use
 867         print_immediate_offset_address.
 868
 869 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 870
 871         * aarch64-opc.c (BANK): New macro.
 872         (R32, R64): Take a register number as argument
 873         (int_reg): Use BANK.
 874
 875 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 876
 877         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 878         (aarch64_print_operand): Update accordingly.
 879
 880 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 881
 882         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 883         for FPIMM.
 884         * aarch64-asm.h (ins_fpimm): New inserter.
 885         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 886         * aarch64-asm-2.c: Regenerate.
 887         * aarch64-dis.h (ext_fpimm): New extractor.
 888         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 889         (aarch64_ext_fpimm): New function.
 890         * aarch64-dis-2.c: Regenerate.
 891
 892 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 893
 894         * aarch64-asm.c: Include libiberty.h.
 895         (insert_fields): New function.
 896         (aarch64_ins_imm): Use it.
 897         * aarch64-dis.c (extract_fields): New function.
 898         (aarch64_ext_imm): Use it.
 899
 900 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 901
 902         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 903         with an esize parameter.
 904         (operand_general_constraint_met_p): Update accordingly.
 905         Fix misindented code.
 906         * aarch64-asm.c (aarch64_ins_limm): Update call to
 907         aarch64_logical_immediate_p.
 908
 909 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 910
 911         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 912
 913 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 914
 915         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 916
 917 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 918
 919         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 920
 921 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 922
 923         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 924         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 925         xor3>: Delete mnemonics.
 926         <cp_abort>: Rename mnemonic from ...
 927         <cpabort>: ...to this.
 928         <setb>: Change to a X form instruction.
 929         <sync>: Change to 1 operand form.
 930         <copy>: Delete mnemonic.
 931         <copy_first>: Rename mnemonic from ...
 932         <copy>: ...to this.
 933         <paste, paste.>: Delete mnemonics.
 934         <paste_last>: Rename mnemonic from ...
 935         <paste.>: ...to this.
 936
 937 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 938
 939         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 940
 941 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 942
 943         * s390-mkopc.c (main): Support alternate arch strings.
 944
 945 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 946
 947         * s390-opc.txt: Fix kmctr instruction type.
 948
 949 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 950
 951         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 952         * i386-init.h: Regenerated.
 953
 954 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 955
 956         * opcodes/arc-dis.c (print_insn_arc): Changed.
 957
 958 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 959
 960         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 961         camellia_fl.
 962
 963 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 964
 965         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 966         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 967         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 968
 969 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 970
 971         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 972         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 973         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 974         PREFIX_MOD_3_0FAE_REG_4.
 975         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 976         PREFIX_MOD_3_0FAE_REG_4.
 977         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 978         (cpu_flags): Add CpuPTWRITE.
 979         * i386-opc.h (CpuPTWRITE): New.
 980         (i386_cpu_flags): Add cpuptwrite.
 981         * i386-opc.tbl: Add ptwrite instruction.
 982         * i386-init.h: Regenerated.
 983         * i386-tbl.h: Likewise.
 984
 985 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 986
 987         * arc-dis.h: Wrap around in extern "C".
 988
 989 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 990
 991         * aarch64-tbl.h (V8_2_INSN): New macro.
 992         (aarch64_opcode_table): Use it.
 993
 994 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 995
 996         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 997         CORE_INSN, __FP_INSN and SIMD_INSN.
 998
 999 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1000
1001         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1002         (aarch64_opcode_table): Update uses accordingly.
1003
1004 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1005         Kwok Cheung Yeung  <kcy@codesourcery.com>
1006
1007         opcodes/
1008         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1009         'e_cmplwi' to 'e_cmpli' instead.
1010         (OPVUPRT, OPVUPRT_MASK): Define.
1011         (powerpc_opcodes): Add E200Z4 insns.
1012         (vle_opcodes): Add context save/restore insns.
1013
1014 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1015
1016         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1017         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1018         "j".
1019
1020 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1021
1022         * arc-nps400-tbl.h: Change block comments to GNU format.
1023         * arc-dis.c: Add new globals addrtypenames,
1024         addrtypenames_max, and addtypeunknown.
1025         (get_addrtype): New function.
1026         (print_insn_arc): Print colons and address types when
1027         required.
1028         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1029         define insert and extract functions for all address types.
1030         (arc_operands): Add operands for colon and all address
1031         types.
1032         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1033         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1034         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1035         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1036         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1037         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1038
1039 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1040
1041         * configure: Regenerated.
1042
1043 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1044
1045         * arc-dis.c (skipclass): New structure.
1046         (decodelist): New variable.
1047         (is_compatible_p): New function.
1048         (new_element): Likewise.
1049         (skip_class_p): Likewise.
1050         (find_format_from_table): Use skip_class_p function.
1051         (find_format): Decode first the extension instructions.
1052         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1053         e_flags.
1054         (parse_option): New function.
1055         (parse_disassembler_options): Likewise.
1056         (print_arc_disassembler_options): Likewise.
1057         (print_insn_arc): Use parse_disassembler_options function.  Proper
1058         select ARCv2 cpu variant.
1059         * disassemble.c (disassembler_usage): Add ARC disassembler
1060         options.
1061
1062 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1063
1064         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1065         annotation from the "nal" entry and reorder it beyond "bltzal".
1066
1067 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1068
1069         * sparc-opc.c (ldtxa): New macro.
1070         (sparc_opcodes): Use the macro defined above to add entries for
1071         the LDTXA instructions.
1072         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1073         instruction.
1074
1075 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1076
1077         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1078         and "jmpc".
1079
1080 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1083         (movzb): Adjust to cover all permitted suffixes.
1084         (movzw): New.
1085         * i386-tbl.h: Re-generate.
1086
1087 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1090         (lgdt): Remove Tbyte from non-64-bit variant.
1091         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1092         xsaves64, xsavec64): Remove Disp16.
1093         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1094         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1095         64-bit variants.
1096         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1097         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1098         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1099         64-bit variants.
1100         * i386-tbl.h: Re-generate.
1101
1102 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1105         * i386-tbl.h: Re-generate.
1106
1107 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1108
1109         * arm-dis.c (print_insn): Fix typo in comment.
1110
1111 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1112
1113         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1114         range of ldst_elemlist operands.
1115         (print_register_list): Use PRIi64 to print the index.
1116         (aarch64_print_operand): Likewise.
1117
1118 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1119
1120         * mcore-opc.h: Remove sentinal.
1121         * mcore-dis.c (print_insn_mcore): Adjust.
1122
1123 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1124
1125         * arc-opc.c: Correct description of availability of NPS400
1126         features.
1127
1128 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1129
1130         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1131         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1132         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1133         xor3>: New mnemonics.
1134         <setb>: Change to a VX form instruction.
1135         (insert_sh6): Add support for rldixor.
1136         (extract_sh6): Likewise.
1137
1138 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1139
1140         * arc-ext.h: Wrap in extern C.
1141
1142 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1143
1144         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1145         Use same method for determining instruction length on ARC700 and
1146         NPS-400.
1147         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1148         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1149         with the NPS400 subclass.
1150         * arc-opc.c: Likewise.
1151
1152 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1153
1154         * sparc-opc.c (rdasr): New macro.
1155         (wrasr): Likewise.
1156         (rdpr): Likewise.
1157         (wrpr): Likewise.
1158         (rdhpr): Likewise.
1159         (wrhpr): Likewise.
1160         (sparc_opcodes): Use the macros above to fix and expand the
1161         definition of read/write instructions from/to
1162         asr/privileged/hyperprivileged instructions.
1163         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1164         %hva_mask_nz.  Prefer softint_set and softint_clear over
1165         set_softint and clear_softint.
1166         (print_insn_sparc): Support %ver in Rd.
1167
1168 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1169
1170         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1171         architecture according to the hardware capabilities they require.
1172
1173 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1174
1175         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1176         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1177         bfd_mach_sparc_v9{c,d,e,v,m}.
1178         * sparc-opc.c (MASK_V9C): Define.
1179         (MASK_V9D): Likewise.
1180         (MASK_V9E): Likewise.
1181         (MASK_V9V): Likewise.
1182         (MASK_V9M): Likewise.
1183         (v6): Add MASK_V9{C,D,E,V,M}.
1184         (v6notlet): Likewise.
1185         (v7): Likewise.
1186         (v8): Likewise.
1187         (v9): Likewise.
1188         (v9andleon): Likewise.
1189         (v9a): Likewise.
1190         (v9b): Likewise.
1191         (v9c): Define.
1192         (v9d): Likewise.
1193         (v9e): Likewise.
1194         (v9v): Likewise.
1195         (v9m): Likewise.
1196         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1197
1198 2016-06-15  Nick Clifton  <nickc@redhat.com>
1199
1200         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1201         constants to match expected behaviour.
1202         (nds32_parse_opcode): Likewise.  Also for whitespace.
1203
1204 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1205
1206         * arc-opc.c (extract_rhv1): Extract value from insn.
1207
1208 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1209
1210         * arc-nps400-tbl.h: Add ldbit instruction.
1211         * arc-opc.c: Add flag classes required for ldbit.
1212
1213 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1214
1215         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1216         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1217         support the above instructions.
1218
1219 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1220
1221         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1222         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1223         csma, cbba, zncv, and hofs.
1224         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1225         support the above instructions.
1226
1227 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1228
1229         * arc-nps400-tbl.h: Add andab and orab instructions.
1230
1231 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1232
1233         * arc-nps400-tbl.h: Add addl-like instructions.
1234
1235 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1236
1237         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1238
1239 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1240
1241         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1242         instructions.
1243
1244 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1245
1246         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1247         variable.
1248         (init_disasm): Handle new command line option "insnlength".
1249         (print_s390_disassembler_options): Mention new option in help
1250         output.
1251         (print_insn_s390): Use the encoded insn length when dumping
1252         unknown instructions.
1253
1254 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1255
1256         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1257          to the address and set as symbol address for LDS/ STS immediate operands.
1258
1259 2016-06-07  Alan Modra  <amodra@gmail.com>
1260
1261         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1262         cpu for "vle" to e500.
1263         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1264         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1265         (PPCNONE): Delete, substitute throughout.
1266         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1267         except for major opcode 4 and 31.
1268         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1269
1270 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1271
1272         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1273         ARM_EXT_RAS in relevant entries.
1274
1275 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1276
1277         PR binutils/20196
1278         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1279         opcodes for E6500.
1280
1281 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1282
1283         PR binutis/18386
1284         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1285         (indir_v_mode): New.
1286         Add comments for '&'.
1287         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1288         (putop): Handle '&'.
1289         (intel_operand_size): Handle indir_v_mode.
1290         (OP_E_register): Likewise.
1291         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1292         64-bit indirect call/jmp for AMD64.
1293         * i386-tbl.h: Regenerated
1294
1295 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1296
1297         * arc-dis.c (struct arc_operand_iterator): New structure.
1298         (find_format_from_table): All the old content from find_format,
1299         with some minor adjustments, and parameter renaming.
1300         (find_format_long_instructions): New function.
1301         (find_format): Rewritten.
1302         (arc_insn_length): Add LSB parameter.
1303         (extract_operand_value): New function.
1304         (operand_iterator_next): New function.
1305         (print_insn_arc): Use new functions to find opcode, and iterator
1306         over operands.
1307         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1308         (extract_nps_3bit_dst_short): New function.
1309         (insert_nps_3bit_src2_short): New function.
1310         (extract_nps_3bit_src2_short): New function.
1311         (insert_nps_bitop1_size): New function.
1312         (extract_nps_bitop1_size): New function.
1313         (insert_nps_bitop2_size): New function.
1314         (extract_nps_bitop2_size): New function.
1315         (insert_nps_bitop_mod4_msb): New function.
1316         (extract_nps_bitop_mod4_msb): New function.
1317         (insert_nps_bitop_mod4_lsb): New function.
1318         (extract_nps_bitop_mod4_lsb): New function.
1319         (insert_nps_bitop_dst_pos3_pos4): New function.
1320         (extract_nps_bitop_dst_pos3_pos4): New function.
1321         (insert_nps_bitop_ins_ext): New function.
1322         (extract_nps_bitop_ins_ext): New function.
1323         (arc_operands): Add new operands.
1324         (arc_long_opcodes): New global array.
1325         (arc_num_long_opcodes): New global.
1326         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1327
1328 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1329
1330         * nds32-asm.h: Add extern "C".
1331         * sh-opc.h: Likewise.
1332
1333 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1334
1335         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1336         0,b,limm to the rflt instruction.
1337
1338 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1339
1340         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1341         constant.
1342
1343 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1344
1345         PR gas/20145
1346         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1347         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1348         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1349         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1350         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1351         * i386-init.h: Regenerated.
1352
1353 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1354
1355         PR gas/20145
1356         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1357         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1358         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1359         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1360         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1361         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1362         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1363         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1364         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1365         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1366         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1367         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1368         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1369         CpuRegMask for AVX512.
1370         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1371         and CpuRegMask.
1372         (set_bitfield_from_cpu_flag_init): New function.
1373         (set_bitfield): Remove const on f.  Call
1374         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1375         * i386-opc.h (CpuRegMMX): New.
1376         (CpuRegXMM): Likewise.
1377         (CpuRegYMM): Likewise.
1378         (CpuRegZMM): Likewise.
1379         (CpuRegMask): Likewise.
1380         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1381         and cpuregmask.
1382         * i386-init.h: Regenerated.
1383         * i386-tbl.h: Likewise.
1384
1385 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1386
1387         PR gas/20154
1388         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1389         (opcode_modifiers): Add AMD64 and Intel64.
1390         (main): Properly verify CpuMax.
1391         * i386-opc.h (CpuAMD64): Removed.
1392         (CpuIntel64): Likewise.
1393         (CpuMax): Set to CpuNo64.
1394         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1395         (AMD64): New.
1396         (Intel64): Likewise.
1397         (i386_opcode_modifier): Add amd64 and intel64.
1398         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1399         on call and jmp.
1400         * i386-init.h: Regenerated.
1401         * i386-tbl.h: Likewise.
1402
1403 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1404
1405         PR gas/20154
1406         * i386-gen.c (main): Fail if CpuMax is incorrect.
1407         * i386-opc.h (CpuMax): Set to CpuIntel64.
1408         * i386-tbl.h: Regenerated.
1409
1410 2016-05-27  Nick Clifton  <nickc@redhat.com>
1411
1412         PR target/20150
1413         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1414         (msp430dis_opcode_unsigned): New function.
1415         (msp430dis_opcode_signed): New function.
1416         (msp430_singleoperand): Use the new opcode reading functions.
1417         Only disassenmble bytes if they were successfully read.
1418         (msp430_doubleoperand): Likewise.
1419         (msp430_branchinstr): Likewise.
1420         (msp430x_callx_instr): Likewise.
1421         (print_insn_msp430): Check that it is safe to read bytes before
1422         attempting disassembly.  Use the new opcode reading functions.
1423
1424 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1425
1426         * ppc-opc.c (CY): New define.  Document it.
1427         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1428
1429 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1430
1431         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1432         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1433         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1434         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1435         CPU_ANY_AVX_FLAGS.
1436         * i386-init.h: Regenerated.
1437
1438 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1439
1440         PR gas/20141
1441         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1442         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1443         * i386-init.h: Regenerated.
1444
1445 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1446
1447         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1448         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1449         * i386-init.h: Regenerated.
1450
1451 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1452
1453         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1454         information.
1455         (print_insn_arc): Set insn_type information.
1456         * arc-opc.c (C_CC): Add F_CLASS_COND.
1457         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1458         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1459         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1460         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1461         (brne, brne_s, jeq_s, jne_s): Likewise.
1462
1463 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1464
1465         * arc-tbl.h (neg): New instruction variant.
1466
1467 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1468
1469         * arc-dis.c (find_format, find_format, get_auxreg)
1470         (print_insn_arc): Changed.
1471         * arc-ext.h (INSERT_XOP): Likewise.
1472
1473 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1474
1475         * tic54x-dis.c (sprint_mmr): Adjust.
1476         * tic54x-opc.c: Likewise.
1477
1478 2016-05-19  Alan Modra  <amodra@gmail.com>
1479
1480         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1481
1482 2016-05-19  Alan Modra  <amodra@gmail.com>
1483
1484         * ppc-opc.c: Formatting.
1485         (NSISIGNOPT): Define.
1486         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1487
1488 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1489
1490         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1491         replacing references to `micromips_ase' throughout.
1492         (_print_insn_mips): Don't use file-level microMIPS annotation to
1493         determine the disassembly mode with the symbol table.
1494
1495 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1496
1497         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1498
1499 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1500
1501         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1502         mips64r6.
1503         * mips-opc.c (D34): New macro.
1504         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1505
1506 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1507
1508         * i386-dis.c (prefix_table): Add RDPID instruction.
1509         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1510         (cpu_flags): Add RDPID bitfield.
1511         * i386-opc.h (enum): Add RDPID element.
1512         (i386_cpu_flags): Add RDPID field.
1513         * i386-opc.tbl: Add RDPID instruction.
1514         * i386-init.h: Regenerate.
1515         * i386-tbl.h: Regenerate.
1516
1517 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1518
1519         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1520         branch type of a symbol.
1521         (print_insn): Likewise.
1522
1523 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1524
1525         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1526         Mainline Security Extensions instructions.
1527         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1528         Extensions instructions.
1529         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1530         instructions.
1531         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1532         special registers.
1533
1534 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1535
1536         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1537
1538 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1539
1540         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1541         (arcExtMap_genOpcode): Likewise.
1542         * arc-opc.c (arg_32bit_rc): Define new variable.
1543         (arg_32bit_u6): Likewise.
1544         (arg_32bit_limm): Likewise.
1545
1546 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1547
1548         * aarch64-gen.c (VERIFIER): Define.
1549         * aarch64-opc.c (VERIFIER): Define.
1550         (verify_ldpsw): Use static linkage.
1551         * aarch64-opc.h (verify_ldpsw): Remove.
1552         * aarch64-tbl.h: Use VERIFIER for verifiers.
1553
1554 2016-04-28  Nick Clifton  <nickc@redhat.com>
1555
1556         PR target/19722
1557         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1558         * aarch64-opc.c (verify_ldpsw): New function.
1559         * aarch64-opc.h (verify_ldpsw): New prototype.
1560         * aarch64-tbl.h: Add initialiser for verifier field.
1561         (LDPSW): Set verifier to verify_ldpsw.
1562
1563 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1564
1565         PR binutils/19983
1566         PR binutils/19984
1567         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1568         smaller than address size.
1569
1570 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1571
1572         * alpha-dis.c: Regenerate.
1573         * crx-dis.c: Likewise.
1574         * disassemble.c: Likewise.
1575         * epiphany-opc.c: Likewise.
1576         * fr30-opc.c: Likewise.
1577         * frv-opc.c: Likewise.
1578         * ip2k-opc.c: Likewise.
1579         * iq2000-opc.c: Likewise.
1580         * lm32-opc.c: Likewise.
1581         * lm32-opinst.c: Likewise.
1582         * m32c-opc.c: Likewise.
1583         * m32r-opc.c: Likewise.
1584         * m32r-opinst.c: Likewise.
1585         * mep-opc.c: Likewise.
1586         * mt-opc.c: Likewise.
1587         * or1k-opc.c: Likewise.
1588         * or1k-opinst.c: Likewise.
1589         * tic80-opc.c: Likewise.
1590         * xc16x-opc.c: Likewise.
1591         * xstormy16-opc.c: Likewise.
1592
1593 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1594
1595         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1596         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1597         calcsd, and calcxd instructions.
1598         * arc-opc.c (insert_nps_bitop_size): Delete.
1599         (extract_nps_bitop_size): Delete.
1600         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1601         (extract_nps_qcmp_m3): Define.
1602         (extract_nps_qcmp_m2): Define.
1603         (extract_nps_qcmp_m1): Define.
1604         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1605         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1606         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1607         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1608         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1609         NPS_QCMP_M3.
1610
1611 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1612
1613         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1614
1615 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1616
1617         * Makefile.in: Regenerated with automake 1.11.6.
1618         * aclocal.m4: Likewise.
1619
1620 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1621
1622         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1623         instructions.
1624         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1625         (extract_nps_cmem_uimm16): New function.
1626         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1627
1628 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1629
1630         * arc-dis.c (arc_insn_length): New function.
1631         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1632         (find_format): Change insnLen parameter to unsigned.
1633
1634 2016-04-13  Nick Clifton  <nickc@redhat.com>
1635
1636         PR target/19937
1637         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1638         the LD.B and LD.BU instructions.
1639
1640 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1641
1642         * arc-dis.c (find_format): Check for extension flags.
1643         (print_flags): New function.
1644         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1645         .extAuxRegister.
1646         * arc-ext.c (arcExtMap_coreRegName): Use
1647         LAST_EXTENSION_CORE_REGISTER.
1648         (arcExtMap_coreReadWrite): Likewise.
1649         (dump_ARC_extmap): Update printing.
1650         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1651         (arc_aux_regs): Add cpu field.
1652         * arc-regs.h: Add cpu field, lower case name aux registers.
1653
1654 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1655
1656         * arc-tbl.h: Add rtsc, sleep with no arguments.
1657
1658 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1659
1660         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1661         Initialize.
1662         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1663         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1664         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1665         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1666         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1667         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1668         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1669         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1670         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1671         (arc_opcode arc_opcodes): Null terminate the array.
1672         (arc_num_opcodes): Remove.
1673         * arc-ext.h (INSERT_XOP): Define.
1674         (extInstruction_t): Likewise.
1675         (arcExtMap_instName): Delete.
1676         (arcExtMap_insn): New function.
1677         (arcExtMap_genOpcode): Likewise.
1678         * arc-ext.c (ExtInstruction): Remove.
1679         (create_map): Zero initialize instruction fields.
1680         (arcExtMap_instName): Remove.
1681         (arcExtMap_insn): New function.
1682         (dump_ARC_extmap): More info while debuging.
1683         (arcExtMap_genOpcode): New function.
1684         * arc-dis.c (find_format): New function.
1685         (print_insn_arc): Use find_format.
1686         (arc_get_disassembler): Enable dump_ARC_extmap only when
1687         debugging.
1688
1689 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1690
1691         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1692         instruction bits out.
1693
1694 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1695
1696         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1697         * arc-opc.c (arc_flag_operands): Add new flags.
1698         (arc_flag_classes): Add new classes.
1699
1700 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1701
1702         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1703
1704 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1705
1706         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1707         encode1, rflt, crc16, and crc32 instructions.
1708         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1709         (arc_flag_classes): Add C_NPS_R.
1710         (insert_nps_bitop_size_2b): New function.
1711         (extract_nps_bitop_size_2b): Likewise.
1712         (insert_nps_bitop_uimm8): Likewise.
1713         (extract_nps_bitop_uimm8): Likewise.
1714         (arc_operands): Add new operand entries.
1715
1716 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1717
1718         * arc-regs.h: Add a new subclass field.  Add double assist
1719         accumulator register values.
1720         * arc-tbl.h: Use DPA subclass to mark the double assist
1721         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1722         * arc-opc.c (RSP): Define instead of SP.
1723         (arc_aux_regs): Add the subclass field.
1724
1725 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1726
1727         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1728
1729 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1730
1731         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1732         NPS_R_SRC1.
1733
1734 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1735
1736         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1737         issues.  No functional changes.
1738
1739 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1740
1741         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1742         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1743         (RTT): Remove duplicate.
1744         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1745         (PCT_CONFIG*): Remove.
1746         (D1L, D1H, D2H, D2L): Define.
1747
1748 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1749
1750         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1751
1752 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1753
1754         * arc-tbl.h (invld07): Remove.
1755         * arc-ext-tbl.h: New file.
1756         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1757         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1758
1759 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1760
1761         Fix -Wstack-usage warnings.
1762         * aarch64-dis.c (print_operands): Substitute size.
1763         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1764
1765 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1766
1767         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1768         to get a proper diagnostic when an invalid ASR register is used.
1769
1770 2016-03-22  Nick Clifton  <nickc@redhat.com>
1771
1772         * configure: Regenerate.
1773
1774 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1775
1776         * arc-nps400-tbl.h: New file.
1777         * arc-opc.c: Add top level comment.
1778         (insert_nps_3bit_dst): New function.
1779         (extract_nps_3bit_dst): New function.
1780         (insert_nps_3bit_src2): New function.
1781         (extract_nps_3bit_src2): New function.
1782         (insert_nps_bitop_size): New function.
1783         (extract_nps_bitop_size): New function.
1784         (arc_flag_operands): Add nps400 entries.
1785         (arc_flag_classes): Add nps400 entries.
1786         (arc_operands): Add nps400 entries.
1787         (arc_opcodes): Add nps400 include.
1788
1789 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1790
1791         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1792         the new class enum values.
1793
1794 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1795
1796         * arc-dis.c (print_insn_arc): Handle nps400.
1797
1798 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1799
1800         * arc-opc.c (BASE): Delete.
1801
1802 2016-03-18  Nick Clifton  <nickc@redhat.com>
1803
1804         PR target/19721
1805         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1806         of MOV insn that aliases an ORR insn.
1807
1808 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1809
1810         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1811
1812 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1813
1814         * mcore-opc.h: Add const qualifiers.
1815         * microblaze-opc.h (struct op_code_struct): Likewise.
1816         * sh-opc.h: Likewise.
1817         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1818         (tic4x_print_op): Likewise.
1819
1820 2016-03-02  Alan Modra  <amodra@gmail.com>
1821
1822         * or1k-desc.h: Regenerate.
1823         * fr30-ibld.c: Regenerate.
1824         * rl78-decode.c: Regenerate.
1825
1826 2016-03-01  Nick Clifton  <nickc@redhat.com>
1827
1828         PR target/19747
1829         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1830
1831 2016-02-24  Renlin Li  <renlin.li@arm.com>
1832
1833         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1834         (print_insn_coprocessor): Support fp16 instructions.
1835
1836 2016-02-24  Renlin Li  <renlin.li@arm.com>
1837
1838         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1839         vminnm, vrint(mpna).
1840
1841 2016-02-24  Renlin Li  <renlin.li@arm.com>
1842
1843         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1844         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1845
1846 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1847
1848         * i386-dis.c (print_insn): Parenthesize expression to prevent
1849         truncated addresses.
1850         (OP_J): Likewise.
1851
1852 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1853             Janek van Oirschot  <jvanoirs@synopsys.com>
1854
1855         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1856         variable.
1857
1858 2016-02-04  Nick Clifton  <nickc@redhat.com>
1859
1860         PR target/19561
1861         * msp430-dis.c (print_insn_msp430): Add a special case for
1862         decoding an RRC instruction with the ZC bit set in the extension
1863         word.
1864
1865 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1866
1867         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1868         * epiphany-ibld.c: Regenerate.
1869         * fr30-ibld.c: Regenerate.
1870         * frv-ibld.c: Regenerate.
1871         * ip2k-ibld.c: Regenerate.
1872         * iq2000-ibld.c: Regenerate.
1873         * lm32-ibld.c: Regenerate.
1874         * m32c-ibld.c: Regenerate.
1875         * m32r-ibld.c: Regenerate.
1876         * mep-ibld.c: Regenerate.
1877         * mt-ibld.c: Regenerate.
1878         * or1k-ibld.c: Regenerate.
1879         * xc16x-ibld.c: Regenerate.
1880         * xstormy16-ibld.c: Regenerate.
1881
1882 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1883
1884         * epiphany-dis.c: Regenerated from latest cpu files.
1885
1886 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1887
1888         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1889         test bit.
1890
1891 2016-01-25  Renlin Li  <renlin.li@arm.com>
1892
1893         * arm-dis.c (mapping_symbol_for_insn): New function.
1894         (find_ifthen_state): Call mapping_symbol_for_insn().
1895
1896 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1897
1898         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1899         of MSR UAO immediate operand.
1900
1901 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1902
1903         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1904         instruction support.
1905
1906 2016-01-17  Alan Modra  <amodra@gmail.com>
1907
1908         * configure: Regenerate.
1909
1910 2016-01-14  Nick Clifton  <nickc@redhat.com>
1911
1912         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1913         instructions that can support stack pointer operations.
1914         * rl78-decode.c: Regenerate.
1915         * rl78-dis.c: Fix display of stack pointer in MOVW based
1916         instructions.
1917
1918 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1919
1920         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1921         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1922         erxtatus_el1 and erxaddr_el1.
1923
1924 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1925
1926         * arm-dis.c (arm_opcodes): Add "esb".
1927         (thumb_opcodes): Likewise.
1928
1929 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1930
1931         * ppc-opc.c <xscmpnedp>: Delete.
1932         <xvcmpnedp>: Likewise.
1933         <xvcmpnedp.>: Likewise.
1934         <xvcmpnesp>: Likewise.
1935         <xvcmpnesp.>: Likewise.
1936
1937 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1938
1939         PR gas/13050
1940         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1941         addition to ISA_A.
1942
1943 2016-01-01  Alan Modra  <amodra@gmail.com>
1944
1945         Update year range in copyright notice of all files.
1946
1947 For older changes see ChangeLog-2015
1948 \f
1949 Copyright (C) 2016 Free Software Foundation, Inc.
1950
1951 Copying and distribution of this file, with or without modification,
1952 are permitted in any medium without royalty provided the copyright
1953 notice and this notice are preserved.
1954
1955 Local Variables:
1956 mode: change-log
1957 left-margin: 8
1958 fill-column: 74
1959 version-control: never
1960 End: