1 2018-10-09 Sudakshina Das <sudi.das@arm.com>
3 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
4 (aarch64_sys_ins_reg_supported_p): New check for above.
6 2018-10-09 Sudakshina Das <sudi.das@arm.com>
8 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
9 AARCH64_OPND_SYSREG_SR.
10 * aarch64-opc.c (aarch64_print_operand): Likewise.
11 (aarch64_sys_regs_sr): Define table.
12 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
13 AARCH64_FEATURE_PREDRES.
14 * aarch64-tbl.h (aarch64_feature_predres): New.
15 (PREDRES, PREDRES_INSN): New.
16 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
17 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
18 * aarch64-asm-2.c: Regenerate.
19 * aarch64-dis-2.c: Regenerate.
20 * aarch64-opc-2.c: Regenerate.
22 2018-10-09 Sudakshina Das <sudi.das@arm.com>
24 * aarch64-tbl.h (aarch64_feature_sb): New.
26 (aarch64_opcode_table): Add entry for sb.
27 * aarch64-asm-2.c: Regenerate.
28 * aarch64-dis-2.c: Regenerate.
29 * aarch64-opc-2.c: Regenerate.
31 2018-10-09 Sudakshina Das <sudi.das@arm.com>
33 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
34 (aarch64_feature_frintts): New.
35 (FLAGMANIP, FRINTTS): New.
36 (aarch64_opcode_table): Add entries for xaflag, axflag
37 and frint[32,64][x,z] instructions.
38 * aarch64-asm-2.c: Regenerate.
39 * aarch64-dis-2.c: Regenerate.
40 * aarch64-opc-2.c: Regenerate.
42 2018-10-09 Sudakshina Das <sudi.das@arm.com>
44 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
45 (ARMV8_5, V8_5_INSN): New.
47 2018-10-08 Tamar Christina <tamar.christina@arm.com>
49 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
51 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
53 * i386-dis.c (rm_table): Add enclv.
54 * i386-opc.tbl: Add enclv.
55 * i386-tbl.h: Regenerated.
57 2018-10-05 Sudakshina Das <sudi.das@arm.com>
59 * arm-dis.c (arm_opcodes): Add sb.
60 (thumb32_opcodes): Likewise.
62 2018-10-05 Richard Henderson <rth@twiddle.net>
63 Stafford Horne <shorne@gmail.com>
65 * or1k-desc.c: Regenerate.
66 * or1k-desc.h: Regenerate.
67 * or1k-opc.c: Regenerate.
68 * or1k-opc.h: Regenerate.
69 * or1k-opinst.c: Regenerate.
71 2018-10-05 Richard Henderson <rth@twiddle.net>
73 * or1k-asm.c: Regenerated.
74 * or1k-desc.c: Regenerated.
75 * or1k-desc.h: Regenerated.
76 * or1k-dis.c: Regenerated.
77 * or1k-ibld.c: Regenerated.
78 * or1k-opc.c: Regenerated.
79 * or1k-opc.h: Regenerated.
80 * or1k-opinst.c: Regenerated.
82 2018-10-05 Richard Henderson <rth@twiddle.net>
84 * or1k-asm.c: Regenerate.
86 2018-10-03 Tamar Christina <tamar.christina@arm.com>
88 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
89 * aarch64-dis.c (print_operands): Refactor to take notes.
90 (print_verifier_notes): New.
91 (print_aarch64_insn): Apply constraint verifier.
92 (print_insn_aarch64_word): Update call to print_aarch64_insn.
93 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
95 2018-10-03 Tamar Christina <tamar.christina@arm.com>
97 * aarch64-opc.c (init_insn_block): New.
98 (verify_constraints, aarch64_is_destructive_by_operands): New.
99 * aarch64-opc.h (verify_constraints): New.
101 2018-10-03 Tamar Christina <tamar.christina@arm.com>
103 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
104 * aarch64-opc.c (verify_ldpsw): Update arguments.
106 2018-10-03 Tamar Christina <tamar.christina@arm.com>
108 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
109 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
111 2018-10-03 Tamar Christina <tamar.christina@arm.com>
113 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
114 * aarch64-dis.c (insn_sequence): New.
116 2018-10-03 Tamar Christina <tamar.christina@arm.com>
118 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
119 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
120 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
121 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
124 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
126 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
128 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
129 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
130 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
131 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
132 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
133 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
134 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
136 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
138 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
140 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
142 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
143 are used when extracting signed fields and converting them to
144 potentially 64-bit types.
146 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
148 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
149 * Makefile.in: Re-generate.
150 * aclocal.m4: Re-generate.
151 * configure: Re-generate.
152 * configure.ac: Remove check for -Wno-missing-field-initializers.
153 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
154 (csky_v2_opcodes): Likewise.
156 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
158 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
160 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
162 * nds32-asm.c (operand_fields): Remove the unused fields.
163 (nds32_opcodes): Remove the unused instructions.
164 * nds32-dis.c (nds32_ex9_info): Removed.
165 (nds32_parse_opcode): Updated.
166 (print_insn_nds32): Likewise.
167 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
168 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
169 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
170 build_opcode_hash_table): New functions.
171 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
172 nds32_opcode_table): New.
173 (hw_ktabs): Declare it to a pointer rather than an array.
174 (build_hash_table): Removed.
175 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
176 SYN_ROPT and upadte HW_GPR and HW_INT.
177 * nds32-dis.c (keywords): Remove const.
178 (match_field): New function.
179 (nds32_parse_opcode): Updated.
180 * disassemble.c (disassemble_init_for_target):
181 Add disassemble_init_nds32.
182 * nds32-dis.c (eum map_type): New.
183 (nds32_private_data): Likewise.
184 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
185 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
186 (print_insn_nds32): Updated.
187 * nds32-asm.c (parse_aext_reg): Add new parameter.
188 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
191 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
192 (operand_fields): Add new fields.
193 (nds32_opcodes): Add new instructions.
194 (keyword_aridxi_mx): New keyword.
195 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
197 (ALU2_1, ALU2_2, ALU2_3): New macros.
198 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
200 2018-09-17 Kito Cheng <kito@andestech.com>
202 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
204 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
207 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
208 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
209 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
210 (EVEX_LEN_0F7E_P_1): Likewise.
211 (EVEX_LEN_0F7E_P_2): Likewise.
212 (EVEX_LEN_0FD6_P_2): Likewise.
213 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
214 (EVEX_LEN_TABLE): Likewise.
215 (EVEX_LEN_0F6E_P_2): New enum.
216 (EVEX_LEN_0F7E_P_1): Likewise.
217 (EVEX_LEN_0F7E_P_2): Likewise.
218 (EVEX_LEN_0FD6_P_2): Likewise.
219 (evex_len_table): New.
220 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
221 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
222 * i386-tbl.h: Regenerated.
224 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
227 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
228 VEX_LEN_0F7E_P_2 entries.
229 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
230 * i386-tbl.h: Regenerated.
232 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
234 * i386-dis.c (VZERO_Fixup): Removed.
236 (VEX_LEN_0F10_P_1): Likewise.
237 (VEX_LEN_0F10_P_3): Likewise.
238 (VEX_LEN_0F11_P_1): Likewise.
239 (VEX_LEN_0F11_P_3): Likewise.
240 (VEX_LEN_0F2E_P_0): Likewise.
241 (VEX_LEN_0F2E_P_2): Likewise.
242 (VEX_LEN_0F2F_P_0): Likewise.
243 (VEX_LEN_0F2F_P_2): Likewise.
244 (VEX_LEN_0F51_P_1): Likewise.
245 (VEX_LEN_0F51_P_3): Likewise.
246 (VEX_LEN_0F52_P_1): Likewise.
247 (VEX_LEN_0F53_P_1): Likewise.
248 (VEX_LEN_0F58_P_1): Likewise.
249 (VEX_LEN_0F58_P_3): Likewise.
250 (VEX_LEN_0F59_P_1): Likewise.
251 (VEX_LEN_0F59_P_3): Likewise.
252 (VEX_LEN_0F5A_P_1): Likewise.
253 (VEX_LEN_0F5A_P_3): Likewise.
254 (VEX_LEN_0F5C_P_1): Likewise.
255 (VEX_LEN_0F5C_P_3): Likewise.
256 (VEX_LEN_0F5D_P_1): Likewise.
257 (VEX_LEN_0F5D_P_3): Likewise.
258 (VEX_LEN_0F5E_P_1): Likewise.
259 (VEX_LEN_0F5E_P_3): Likewise.
260 (VEX_LEN_0F5F_P_1): Likewise.
261 (VEX_LEN_0F5F_P_3): Likewise.
262 (VEX_LEN_0FC2_P_1): Likewise.
263 (VEX_LEN_0FC2_P_3): Likewise.
264 (VEX_LEN_0F3A0A_P_2): Likewise.
265 (VEX_LEN_0F3A0B_P_2): Likewise.
266 (VEX_W_0F10_P_0): Likewise.
267 (VEX_W_0F10_P_1): Likewise.
268 (VEX_W_0F10_P_2): Likewise.
269 (VEX_W_0F10_P_3): Likewise.
270 (VEX_W_0F11_P_0): Likewise.
271 (VEX_W_0F11_P_1): Likewise.
272 (VEX_W_0F11_P_2): Likewise.
273 (VEX_W_0F11_P_3): Likewise.
274 (VEX_W_0F12_P_0_M_0): Likewise.
275 (VEX_W_0F12_P_0_M_1): Likewise.
276 (VEX_W_0F12_P_1): Likewise.
277 (VEX_W_0F12_P_2): Likewise.
278 (VEX_W_0F12_P_3): Likewise.
279 (VEX_W_0F13_M_0): Likewise.
280 (VEX_W_0F14): Likewise.
281 (VEX_W_0F15): Likewise.
282 (VEX_W_0F16_P_0_M_0): Likewise.
283 (VEX_W_0F16_P_0_M_1): Likewise.
284 (VEX_W_0F16_P_1): Likewise.
285 (VEX_W_0F16_P_2): Likewise.
286 (VEX_W_0F17_M_0): Likewise.
287 (VEX_W_0F28): Likewise.
288 (VEX_W_0F29): Likewise.
289 (VEX_W_0F2B_M_0): Likewise.
290 (VEX_W_0F2E_P_0): Likewise.
291 (VEX_W_0F2E_P_2): Likewise.
292 (VEX_W_0F2F_P_0): Likewise.
293 (VEX_W_0F2F_P_2): Likewise.
294 (VEX_W_0F50_M_0): Likewise.
295 (VEX_W_0F51_P_0): Likewise.
296 (VEX_W_0F51_P_1): Likewise.
297 (VEX_W_0F51_P_2): Likewise.
298 (VEX_W_0F51_P_3): Likewise.
299 (VEX_W_0F52_P_0): Likewise.
300 (VEX_W_0F52_P_1): Likewise.
301 (VEX_W_0F53_P_0): Likewise.
302 (VEX_W_0F53_P_1): Likewise.
303 (VEX_W_0F58_P_0): Likewise.
304 (VEX_W_0F58_P_1): Likewise.
305 (VEX_W_0F58_P_2): Likewise.
306 (VEX_W_0F58_P_3): Likewise.
307 (VEX_W_0F59_P_0): Likewise.
308 (VEX_W_0F59_P_1): Likewise.
309 (VEX_W_0F59_P_2): Likewise.
310 (VEX_W_0F59_P_3): Likewise.
311 (VEX_W_0F5A_P_0): Likewise.
312 (VEX_W_0F5A_P_1): Likewise.
313 (VEX_W_0F5A_P_3): Likewise.
314 (VEX_W_0F5B_P_0): Likewise.
315 (VEX_W_0F5B_P_1): Likewise.
316 (VEX_W_0F5B_P_2): Likewise.
317 (VEX_W_0F5C_P_0): Likewise.
318 (VEX_W_0F5C_P_1): Likewise.
319 (VEX_W_0F5C_P_2): Likewise.
320 (VEX_W_0F5C_P_3): Likewise.
321 (VEX_W_0F5D_P_0): Likewise.
322 (VEX_W_0F5D_P_1): Likewise.
323 (VEX_W_0F5D_P_2): Likewise.
324 (VEX_W_0F5D_P_3): Likewise.
325 (VEX_W_0F5E_P_0): Likewise.
326 (VEX_W_0F5E_P_1): Likewise.
327 (VEX_W_0F5E_P_2): Likewise.
328 (VEX_W_0F5E_P_3): Likewise.
329 (VEX_W_0F5F_P_0): Likewise.
330 (VEX_W_0F5F_P_1): Likewise.
331 (VEX_W_0F5F_P_2): Likewise.
332 (VEX_W_0F5F_P_3): Likewise.
333 (VEX_W_0F60_P_2): Likewise.
334 (VEX_W_0F61_P_2): Likewise.
335 (VEX_W_0F62_P_2): Likewise.
336 (VEX_W_0F63_P_2): Likewise.
337 (VEX_W_0F64_P_2): Likewise.
338 (VEX_W_0F65_P_2): Likewise.
339 (VEX_W_0F66_P_2): Likewise.
340 (VEX_W_0F67_P_2): Likewise.
341 (VEX_W_0F68_P_2): Likewise.
342 (VEX_W_0F69_P_2): Likewise.
343 (VEX_W_0F6A_P_2): Likewise.
344 (VEX_W_0F6B_P_2): Likewise.
345 (VEX_W_0F6C_P_2): Likewise.
346 (VEX_W_0F6D_P_2): Likewise.
347 (VEX_W_0F6F_P_1): Likewise.
348 (VEX_W_0F6F_P_2): Likewise.
349 (VEX_W_0F70_P_1): Likewise.
350 (VEX_W_0F70_P_2): Likewise.
351 (VEX_W_0F70_P_3): Likewise.
352 (VEX_W_0F71_R_2_P_2): Likewise.
353 (VEX_W_0F71_R_4_P_2): Likewise.
354 (VEX_W_0F71_R_6_P_2): Likewise.
355 (VEX_W_0F72_R_2_P_2): Likewise.
356 (VEX_W_0F72_R_4_P_2): Likewise.
357 (VEX_W_0F72_R_6_P_2): Likewise.
358 (VEX_W_0F73_R_2_P_2): Likewise.
359 (VEX_W_0F73_R_3_P_2): Likewise.
360 (VEX_W_0F73_R_6_P_2): Likewise.
361 (VEX_W_0F73_R_7_P_2): Likewise.
362 (VEX_W_0F74_P_2): Likewise.
363 (VEX_W_0F75_P_2): Likewise.
364 (VEX_W_0F76_P_2): Likewise.
365 (VEX_W_0F77_P_0): Likewise.
366 (VEX_W_0F7C_P_2): Likewise.
367 (VEX_W_0F7C_P_3): Likewise.
368 (VEX_W_0F7D_P_2): Likewise.
369 (VEX_W_0F7D_P_3): Likewise.
370 (VEX_W_0F7E_P_1): Likewise.
371 (VEX_W_0F7F_P_1): Likewise.
372 (VEX_W_0F7F_P_2): Likewise.
373 (VEX_W_0FAE_R_2_M_0): Likewise.
374 (VEX_W_0FAE_R_3_M_0): Likewise.
375 (VEX_W_0FC2_P_0): Likewise.
376 (VEX_W_0FC2_P_1): Likewise.
377 (VEX_W_0FC2_P_2): Likewise.
378 (VEX_W_0FC2_P_3): Likewise.
379 (VEX_W_0FD0_P_2): Likewise.
380 (VEX_W_0FD0_P_3): Likewise.
381 (VEX_W_0FD1_P_2): Likewise.
382 (VEX_W_0FD2_P_2): Likewise.
383 (VEX_W_0FD3_P_2): Likewise.
384 (VEX_W_0FD4_P_2): Likewise.
385 (VEX_W_0FD5_P_2): Likewise.
386 (VEX_W_0FD6_P_2): Likewise.
387 (VEX_W_0FD7_P_2_M_1): Likewise.
388 (VEX_W_0FD8_P_2): Likewise.
389 (VEX_W_0FD9_P_2): Likewise.
390 (VEX_W_0FDA_P_2): Likewise.
391 (VEX_W_0FDB_P_2): Likewise.
392 (VEX_W_0FDC_P_2): Likewise.
393 (VEX_W_0FDD_P_2): Likewise.
394 (VEX_W_0FDE_P_2): Likewise.
395 (VEX_W_0FDF_P_2): Likewise.
396 (VEX_W_0FE0_P_2): Likewise.
397 (VEX_W_0FE1_P_2): Likewise.
398 (VEX_W_0FE2_P_2): Likewise.
399 (VEX_W_0FE3_P_2): Likewise.
400 (VEX_W_0FE4_P_2): Likewise.
401 (VEX_W_0FE5_P_2): Likewise.
402 (VEX_W_0FE6_P_1): Likewise.
403 (VEX_W_0FE6_P_2): Likewise.
404 (VEX_W_0FE6_P_3): Likewise.
405 (VEX_W_0FE7_P_2_M_0): Likewise.
406 (VEX_W_0FE8_P_2): Likewise.
407 (VEX_W_0FE9_P_2): Likewise.
408 (VEX_W_0FEA_P_2): Likewise.
409 (VEX_W_0FEB_P_2): Likewise.
410 (VEX_W_0FEC_P_2): Likewise.
411 (VEX_W_0FED_P_2): Likewise.
412 (VEX_W_0FEE_P_2): Likewise.
413 (VEX_W_0FEF_P_2): Likewise.
414 (VEX_W_0FF0_P_3_M_0): Likewise.
415 (VEX_W_0FF1_P_2): Likewise.
416 (VEX_W_0FF2_P_2): Likewise.
417 (VEX_W_0FF3_P_2): Likewise.
418 (VEX_W_0FF4_P_2): Likewise.
419 (VEX_W_0FF5_P_2): Likewise.
420 (VEX_W_0FF6_P_2): Likewise.
421 (VEX_W_0FF7_P_2): Likewise.
422 (VEX_W_0FF8_P_2): Likewise.
423 (VEX_W_0FF9_P_2): Likewise.
424 (VEX_W_0FFA_P_2): Likewise.
425 (VEX_W_0FFB_P_2): Likewise.
426 (VEX_W_0FFC_P_2): Likewise.
427 (VEX_W_0FFD_P_2): Likewise.
428 (VEX_W_0FFE_P_2): Likewise.
429 (VEX_W_0F3800_P_2): Likewise.
430 (VEX_W_0F3801_P_2): Likewise.
431 (VEX_W_0F3802_P_2): Likewise.
432 (VEX_W_0F3803_P_2): Likewise.
433 (VEX_W_0F3804_P_2): Likewise.
434 (VEX_W_0F3805_P_2): Likewise.
435 (VEX_W_0F3806_P_2): Likewise.
436 (VEX_W_0F3807_P_2): Likewise.
437 (VEX_W_0F3808_P_2): Likewise.
438 (VEX_W_0F3809_P_2): Likewise.
439 (VEX_W_0F380A_P_2): Likewise.
440 (VEX_W_0F380B_P_2): Likewise.
441 (VEX_W_0F3817_P_2): Likewise.
442 (VEX_W_0F381C_P_2): Likewise.
443 (VEX_W_0F381D_P_2): Likewise.
444 (VEX_W_0F381E_P_2): Likewise.
445 (VEX_W_0F3820_P_2): Likewise.
446 (VEX_W_0F3821_P_2): Likewise.
447 (VEX_W_0F3822_P_2): Likewise.
448 (VEX_W_0F3823_P_2): Likewise.
449 (VEX_W_0F3824_P_2): Likewise.
450 (VEX_W_0F3825_P_2): Likewise.
451 (VEX_W_0F3828_P_2): Likewise.
452 (VEX_W_0F3829_P_2): Likewise.
453 (VEX_W_0F382A_P_2_M_0): Likewise.
454 (VEX_W_0F382B_P_2): Likewise.
455 (VEX_W_0F3830_P_2): Likewise.
456 (VEX_W_0F3831_P_2): Likewise.
457 (VEX_W_0F3832_P_2): Likewise.
458 (VEX_W_0F3833_P_2): Likewise.
459 (VEX_W_0F3834_P_2): Likewise.
460 (VEX_W_0F3835_P_2): Likewise.
461 (VEX_W_0F3837_P_2): Likewise.
462 (VEX_W_0F3838_P_2): Likewise.
463 (VEX_W_0F3839_P_2): Likewise.
464 (VEX_W_0F383A_P_2): Likewise.
465 (VEX_W_0F383B_P_2): Likewise.
466 (VEX_W_0F383C_P_2): Likewise.
467 (VEX_W_0F383D_P_2): Likewise.
468 (VEX_W_0F383E_P_2): Likewise.
469 (VEX_W_0F383F_P_2): Likewise.
470 (VEX_W_0F3840_P_2): Likewise.
471 (VEX_W_0F3841_P_2): Likewise.
472 (VEX_W_0F38DB_P_2): Likewise.
473 (VEX_W_0F3A08_P_2): Likewise.
474 (VEX_W_0F3A09_P_2): Likewise.
475 (VEX_W_0F3A0A_P_2): Likewise.
476 (VEX_W_0F3A0B_P_2): Likewise.
477 (VEX_W_0F3A0C_P_2): Likewise.
478 (VEX_W_0F3A0D_P_2): Likewise.
479 (VEX_W_0F3A0E_P_2): Likewise.
480 (VEX_W_0F3A0F_P_2): Likewise.
481 (VEX_W_0F3A21_P_2): Likewise.
482 (VEX_W_0F3A40_P_2): Likewise.
483 (VEX_W_0F3A41_P_2): Likewise.
484 (VEX_W_0F3A42_P_2): Likewise.
485 (VEX_W_0F3A62_P_2): Likewise.
486 (VEX_W_0F3A63_P_2): Likewise.
487 (VEX_W_0F3ADF_P_2): Likewise.
488 (VEX_LEN_0F77_P_0): New.
489 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
490 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
491 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
492 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
493 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
494 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
495 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
496 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
497 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
498 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
499 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
500 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
501 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
502 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
503 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
504 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
505 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
506 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
507 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
508 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
509 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
510 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
511 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
512 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
513 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
514 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
515 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
516 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
517 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
518 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
519 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
520 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
521 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
522 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
523 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
524 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
525 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
526 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
527 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
528 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
529 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
530 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
531 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
532 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
533 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
534 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
535 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
536 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
537 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
538 (vex_table): Update VEX 0F28 and 0F29 entries.
539 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
540 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
541 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
542 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
543 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
544 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
545 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
546 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
547 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
548 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
549 VEX_LEN_0F3A0B_P_2 entries.
550 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
551 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
552 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
553 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
554 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
555 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
556 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
557 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
558 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
559 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
560 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
561 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
562 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
563 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
564 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
565 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
566 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
567 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
568 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
569 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
570 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
571 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
572 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
573 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
574 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
575 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
576 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
577 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
578 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
579 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
580 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
581 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
582 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
583 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
584 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
585 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
586 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
587 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
588 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
589 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
590 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
591 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
592 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
593 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
594 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
595 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
596 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
597 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
598 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
599 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
600 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
601 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
602 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
603 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
604 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
605 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
606 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
607 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
608 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
609 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
610 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
611 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
612 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
613 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
614 VEX_W_0F3ADF_P_2 entries.
615 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
616 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
617 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
619 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
621 * i386-opc.tbl (VexWIG): New.
622 Replace VexW=3 with VexWIG.
624 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
627 * i386-tbl.h: Regenerated.
629 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
632 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
633 VEX_LEN_0FD6_P_2 entries.
634 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
635 * i386-tbl.h: Regenerated.
637 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
640 * i386-opc.h (VEXWIG): New.
641 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
642 * i386-tbl.h: Regenerated.
644 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
647 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
648 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
649 * i386-dis.c (EXxEVexR64): New.
650 (evex_rounding_64_mode): Likewise.
651 (OP_Rounding): Handle evex_rounding_64_mode.
653 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
656 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
657 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
658 * i386-dis.c (Edqa): New.
659 (dqa_mode): Likewise.
660 (intel_operand_size): Handle dqa_mode as m_mode.
661 (OP_E_register): Handle dqa_mode as dq_mode.
662 (OP_E_memory): Set shift for dqa_mode based on address_mode.
664 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
666 * i386-dis.c (OP_E_memory): Reformat.
668 2018-09-14 Jan Beulich <jbeulich@suse.com>
670 * i386-opc.tbl (crc32): Fold byte and word forms.
671 * i386-tbl.h: Re-generate.
673 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
675 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
676 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
677 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
678 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
679 * i386-tbl.h: Regenerated.
681 2018-09-13 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
685 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
686 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
687 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
688 * i386-tbl.h: Re-generate.
690 2018-09-13 Jan Beulich <jbeulich@suse.com>
692 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
694 * i386-tbl.h: Re-generate.
696 2018-09-13 Jan Beulich <jbeulich@suse.com>
698 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
700 * i386-tbl.h: Re-generate.
702 2018-09-13 Jan Beulich <jbeulich@suse.com>
704 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
706 * i386-tbl.h: Re-generate.
708 2018-09-13 Jan Beulich <jbeulich@suse.com>
710 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
712 * i386-tbl.h: Re-generate.
714 2018-09-13 Jan Beulich <jbeulich@suse.com>
716 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
718 * i386-tbl.h: Re-generate.
720 2018-09-13 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
724 * i386-tbl.h: Re-generate.
726 2018-09-13 Jan Beulich <jbeulich@suse.com>
728 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
729 * i386-tbl.h: Re-generate.
731 2018-09-13 Jan Beulich <jbeulich@suse.com>
733 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
734 * i386-tbl.h: Re-generate.
736 2018-09-13 Jan Beulich <jbeulich@suse.com>
738 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
740 * i386-tbl.h: Re-generate.
742 2018-09-13 Jan Beulich <jbeulich@suse.com>
744 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
746 * i386-tbl.h: Re-generate.
748 2018-09-13 Jan Beulich <jbeulich@suse.com>
750 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
751 * i386-tbl.h: Re-generate.
753 2018-09-13 Jan Beulich <jbeulich@suse.com>
755 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
756 * i386-tbl.h: Re-generate.
758 2018-09-13 Jan Beulich <jbeulich@suse.com>
760 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
761 * i386-tbl.h: Re-generate.
763 2018-09-13 Jan Beulich <jbeulich@suse.com>
765 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
767 * i386-tbl.h: Re-generate.
769 2018-09-13 Jan Beulich <jbeulich@suse.com>
771 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
773 * i386-tbl.h: Re-generate.
775 2018-09-13 Jan Beulich <jbeulich@suse.com>
777 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
779 * i386-tbl.h: Re-generate.
781 2018-09-13 Jan Beulich <jbeulich@suse.com>
783 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
784 * i386-tbl.h: Re-generate.
786 2018-09-13 Jan Beulich <jbeulich@suse.com>
788 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
789 * i386-tbl.h: Re-generate.
791 2018-09-13 Jan Beulich <jbeulich@suse.com>
793 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
794 * i386-tbl.h: Re-generate.
796 2018-09-13 Jan Beulich <jbeulich@suse.com>
798 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
799 (vpbroadcastw, rdpid): Drop NoRex64.
800 * i386-tbl.h: Re-generate.
802 2018-09-13 Jan Beulich <jbeulich@suse.com>
804 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
805 store templates, adding D.
806 * i386-tbl.h: Re-generate.
808 2018-09-13 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
811 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
812 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
813 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
814 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
815 Fold load and store templates where possible, adding D. Drop
816 IgnoreSize where it was pointlessly present. Drop redundant
818 * i386-tbl.h: Re-generate.
820 2018-09-13 Jan Beulich <jbeulich@suse.com>
822 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
823 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
824 (intel_operand_size): Handle v_bndmk_mode.
825 (OP_E_memory): Likewise. Produce (bad) when also riprel.
827 2018-09-08 John Darrington <john@darrington.wattle.id.au>
829 * disassemble.c (ARCH_s12z): Define if ARCH_all.
831 2018-08-31 Kito Cheng <kito@andestech.com>
833 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
834 compressed floating point instructions.
836 2018-08-30 Kito Cheng <kito@andestech.com>
838 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
839 riscv_opcode.xlen_requirement.
840 * riscv-opc.c (riscv_opcodes): Update for struct change.
842 2018-08-29 Martin Aberg <maberg@gaisler.com>
844 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
845 psr (PWRPSR) instruction.
847 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
849 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
851 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
853 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
855 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
857 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
858 loongson3a as an alias of gs464 for compatibility.
859 * mips-opc.c (mips_opcodes): Change Comments.
861 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
863 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
865 (print_mips_disassembler_options): Document -M loongson-ext.
866 * mips-opc.c (LEXT2): New macro.
867 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
869 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
871 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
873 (parse_mips_ase_option): Handle -M loongson-ext option.
874 (print_mips_disassembler_options): Document -M loongson-ext.
875 * mips-opc.c (IL3A): Delete.
876 * mips-opc.c (LEXT): New macro.
877 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
880 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
882 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
884 (parse_mips_ase_option): Handle -M loongson-cam option.
885 (print_mips_disassembler_options): Document -M loongson-cam.
886 * mips-opc.c (LCAM): New macro.
887 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
890 2018-08-21 Alan Modra <amodra@gmail.com>
892 * ppc-dis.c (operand_value_powerpc): Init "invalid".
893 (skip_optional_operands): Count optional operands, and update
894 ppc_optional_operand_value call.
895 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
896 (extract_vlensi): Likewise.
897 (extract_fxm): Return default value for missing optional operand.
898 (extract_ls, extract_raq, extract_tbr): Likewise.
899 (insert_sxl, extract_sxl): New functions.
900 (insert_esync, extract_esync): Remove Power9 handling and simplify.
901 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
902 flag and extra entry.
903 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
906 2018-08-20 Alan Modra <amodra@gmail.com>
908 * sh-opc.h (MASK): Simplify.
910 2018-08-18 John Darrington <john@darrington.wattle.id.au>
912 * s12z-dis.c (bm_decode): Deal with cases where the mode is
913 BM_RESERVED0 or BM_RESERVED1
914 (bm_rel_decode, bm_n_bytes): Ditto.
916 2018-08-18 John Darrington <john@darrington.wattle.id.au>
920 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
922 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
923 address with the addr32 prefix and without base nor index
926 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
928 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
929 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
930 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
931 (cpu_flags): Add CpuCMOV and CpuFXSR.
932 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
933 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
934 * i386-init.h: Regenerated.
935 * i386-tbl.h: Likewise.
937 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
939 * arc-regs.h: Update auxiliary registers.
941 2018-08-06 Jan Beulich <jbeulich@suse.com>
943 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
944 (RegIP, RegIZ): Define.
945 * i386-reg.tbl: Adjust comments.
946 (rip): Use Qword instead of BaseIndex. Use RegIP.
947 (eip): Use Dword instead of BaseIndex. Use RegIP.
948 (riz): Add Qword. Use RegIZ.
949 (eiz): Add Dword. Use RegIZ.
950 * i386-tbl.h: Re-generate.
952 2018-08-03 Jan Beulich <jbeulich@suse.com>
954 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
955 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
956 vpmovzxdq, vpmovzxwd): Remove NoRex64.
957 * i386-tbl.h: Re-generate.
959 2018-08-03 Jan Beulich <jbeulich@suse.com>
961 * i386-gen.c (operand_types): Remove Mem field.
962 * i386-opc.h (union i386_operand_type): Remove mem field.
963 * i386-init.h, i386-tbl.h: Re-generate.
965 2018-08-01 Alan Modra <amodra@gmail.com>
967 * po/POTFILES.in: Regenerate.
969 2018-07-31 Nick Clifton <nickc@redhat.com>
971 * po/sv.po: Updated Swedish translation.
973 2018-07-31 Jan Beulich <jbeulich@suse.com>
975 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
976 * i386-init.h, i386-tbl.h: Re-generate.
978 2018-07-31 Jan Beulich <jbeulich@suse.com>
980 * i386-opc.h (ZEROING_MASKING) Rename to ...
981 (DYNAMIC_MASKING): ... this. Adjust comment.
982 * i386-opc.tbl (MaskingMorZ): Define.
983 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
984 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
985 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
986 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
987 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
988 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
989 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
990 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
991 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
993 2018-07-31 Jan Beulich <jbeulich@suse.com>
995 * i386-opc.tbl: Use element rather than vector size for AVX512*
996 scatter/gather insns.
997 * i386-tbl.h: Re-generate.
999 2018-07-31 Jan Beulich <jbeulich@suse.com>
1001 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1002 (cpu_flags): Drop CpuVREX.
1003 * i386-opc.h (CpuVREX): Delete.
1004 (union i386_cpu_flags): Remove cpuvrex.
1005 * i386-init.h, i386-tbl.h: Re-generate.
1007 2018-07-30 Jim Wilson <jimw@sifive.com>
1009 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1011 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1013 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1015 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1016 * Makefile.in: Regenerated.
1017 * configure.ac: Add C-SKY.
1018 * configure: Regenerated.
1019 * csky-dis.c: New file.
1020 * csky-opc.h: New file.
1021 * disassemble.c (ARCH_csky): Define.
1022 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1023 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1025 2018-07-27 Alan Modra <amodra@gmail.com>
1027 * ppc-opc.c (insert_sprbat): Correct function parameter and
1029 (extract_sprbat): Likewise, variable too.
1031 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1032 Alan Modra <amodra@gmail.com>
1034 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1035 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1036 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1037 support disjointed BAT.
1038 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1039 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1040 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1042 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1043 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1045 * i386-gen.c (adjust_broadcast_modifier): New function.
1046 (process_i386_opcode_modifier): Add an argument for operands.
1047 Adjust the Broadcast value based on operands.
1048 (output_i386_opcode): Pass operand_types to
1049 process_i386_opcode_modifier.
1050 (process_i386_opcodes): Pass NULL as operands to
1051 process_i386_opcode_modifier.
1052 * i386-opc.h (BYTE_BROADCAST): New.
1053 (WORD_BROADCAST): Likewise.
1054 (DWORD_BROADCAST): Likewise.
1055 (QWORD_BROADCAST): Likewise.
1056 (i386_opcode_modifier): Expand broadcast to 3 bits.
1057 * i386-tbl.h: Regenerated.
1059 2018-07-24 Alan Modra <amodra@gmail.com>
1062 * or1k-desc.h: Regenerate.
1064 2018-07-24 Jan Beulich <jbeulich@suse.com>
1066 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1067 vcvtusi2ss, and vcvtusi2sd.
1068 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1069 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1070 * i386-tbl.h: Re-generate.
1072 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1074 * arc-opc.c (extract_w6): Fix extending the sign.
1076 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1078 * arc-tbl.h (vewt): Allow it for ARC EM family.
1080 2018-07-23 Alan Modra <amodra@gmail.com>
1083 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1084 opcode variants for mtspr/mfspr encodings.
1086 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1087 Maciej W. Rozycki <macro@mips.com>
1089 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1090 loongson3a descriptors.
1091 (parse_mips_ase_option): Handle -M loongson-mmi option.
1092 (print_mips_disassembler_options): Document -M loongson-mmi.
1093 * mips-opc.c (LMMI): New macro.
1094 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1097 2018-07-19 Jan Beulich <jbeulich@suse.com>
1099 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1100 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1101 IgnoreSize and [XYZ]MMword where applicable.
1102 * i386-tbl.h: Re-generate.
1104 2018-07-19 Jan Beulich <jbeulich@suse.com>
1106 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1107 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1108 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1109 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1110 * i386-tbl.h: Re-generate.
1112 2018-07-19 Jan Beulich <jbeulich@suse.com>
1114 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1115 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1116 VPCLMULQDQ templates into their respective AVX512VL counterparts
1117 where possible, using Disp8ShiftVL and CheckRegSize instead of
1118 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1119 * i386-tbl.h: Re-generate.
1121 2018-07-19 Jan Beulich <jbeulich@suse.com>
1123 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1124 AVX512VL counterparts where possible, using Disp8ShiftVL and
1125 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1126 IgnoreSize) as appropriate.
1127 * i386-tbl.h: Re-generate.
1129 2018-07-19 Jan Beulich <jbeulich@suse.com>
1131 * i386-opc.tbl: Fold AVX512BW templates into their respective
1132 AVX512VL counterparts where possible, using Disp8ShiftVL and
1133 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1134 IgnoreSize) as appropriate.
1135 * i386-tbl.h: Re-generate.
1137 2018-07-19 Jan Beulich <jbeulich@suse.com>
1139 * i386-opc.tbl: Fold AVX512CD templates into their respective
1140 AVX512VL counterparts where possible, using Disp8ShiftVL and
1141 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1142 IgnoreSize) as appropriate.
1143 * i386-tbl.h: Re-generate.
1145 2018-07-19 Jan Beulich <jbeulich@suse.com>
1147 * i386-opc.h (DISP8_SHIFT_VL): New.
1148 * i386-opc.tbl (Disp8ShiftVL): Define.
1149 (various): Fold AVX512VL templates into their respective
1150 AVX512F counterparts where possible, using Disp8ShiftVL and
1151 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1152 IgnoreSize) as appropriate.
1153 * i386-tbl.h: Re-generate.
1155 2018-07-19 Jan Beulich <jbeulich@suse.com>
1157 * Makefile.am: Change dependencies and rule for
1158 $(srcdir)/i386-init.h.
1159 * Makefile.in: Re-generate.
1160 * i386-gen.c (process_i386_opcodes): New local variable
1161 "marker". Drop opening of input file. Recognize marker and line
1163 * i386-opc.tbl (OPCODE_I386_H): Define.
1164 (i386-opc.h): Include it.
1167 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1170 * i386-opc.h (Byte): Update comments.
1176 (Xmmword): Likewise.
1177 (Ymmword): Likewise.
1178 (Zmmword): Likewise.
1179 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1181 * i386-tbl.h: Regenerated.
1183 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1185 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1186 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1187 * aarch64-asm-2.c: Regenerate.
1188 * aarch64-dis-2.c: Regenerate.
1189 * aarch64-opc-2.c: Regenerate.
1191 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1194 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1195 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1196 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1197 sqdmulh, sqrdmulh): Use Em16.
1199 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1201 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1202 csdb together with them.
1203 (thumb32_opcodes): Likewise.
1205 2018-07-11 Jan Beulich <jbeulich@suse.com>
1207 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1208 requiring 32-bit registers as operands 2 and 3. Improve
1210 (mwait, mwaitx): Fold templates. Improve comments.
1211 OPERAND_TYPE_INOUTPORTREG.
1212 * i386-tbl.h: Re-generate.
1214 2018-07-11 Jan Beulich <jbeulich@suse.com>
1216 * i386-gen.c (operand_type_init): Remove
1217 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1218 OPERAND_TYPE_INOUTPORTREG.
1219 * i386-init.h: Re-generate.
1221 2018-07-11 Jan Beulich <jbeulich@suse.com>
1223 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1224 (wrssq, wrussq): Add Qword.
1225 * i386-tbl.h: Re-generate.
1227 2018-07-11 Jan Beulich <jbeulich@suse.com>
1229 * i386-opc.h: Rename OTMax to OTNum.
1230 (OTNumOfUints): Adjust calculation.
1231 (OTUnused): Directly alias to OTNum.
1233 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1235 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1237 (lea_reg_xys): Likewise.
1238 (print_insn_loop_primitive): Rename `reg' local variable to
1241 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1244 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1246 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1249 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1250 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1252 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1255 * mips-dis.c (mips_option_arg_t): New enumeration.
1256 (mips_options): New variable.
1257 (disassembler_options_mips): New function.
1258 (print_mips_disassembler_options): Reimplement in terms of
1259 `disassembler_options_mips'.
1260 * arm-dis.c (disassembler_options_arm): Adapt to using the
1261 `disasm_options_and_args_t' structure.
1262 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1263 * s390-dis.c (disassembler_options_s390): Likewise.
1265 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1267 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1269 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1270 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1271 * testsuite/ld-arm/tls-longplt.d: Likewise.
1273 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1276 * aarch64-asm-2.c: Regenerate.
1277 * aarch64-dis-2.c: Likewise.
1278 * aarch64-opc-2.c: Likewise.
1279 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1280 * aarch64-opc.c (operand_general_constraint_met_p,
1281 aarch64_print_operand): Likewise.
1282 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1283 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1285 (AARCH64_OPERANDS): Add Em2.
1287 2018-06-26 Nick Clifton <nickc@redhat.com>
1289 * po/uk.po: Updated Ukranian translation.
1290 * po/de.po: Updated German translation.
1291 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1293 2018-06-26 Nick Clifton <nickc@redhat.com>
1295 * nfp-dis.c: Fix spelling mistake.
1297 2018-06-24 Nick Clifton <nickc@redhat.com>
1299 * configure: Regenerate.
1300 * po/opcodes.pot: Regenerate.
1302 2018-06-24 Nick Clifton <nickc@redhat.com>
1304 2.31 branch created.
1306 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1308 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1309 * aarch64-asm-2.c: Regenerate.
1310 * aarch64-dis-2.c: Likewise.
1312 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1314 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1315 `-M ginv' option description.
1317 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1320 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1323 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1325 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1326 * configure.ac: Remove AC_PREREQ.
1327 * Makefile.in: Re-generate.
1328 * aclocal.m4: Re-generate.
1329 * configure: Re-generate.
1331 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1333 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1334 mips64r6 descriptors.
1335 (parse_mips_ase_option): Handle -Mginv option.
1336 (print_mips_disassembler_options): Document -Mginv.
1337 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1339 (mips_opcodes): Define ginvi and ginvt.
1341 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1342 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1344 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1345 * mips-opc.c (CRC, CRC64): New macros.
1346 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1347 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1350 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1353 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1354 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1356 2018-06-06 Alan Modra <amodra@gmail.com>
1358 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1359 setjmp. Move init for some other vars later too.
1361 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1363 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1364 (dis_private): Add new fields for property section tracking.
1365 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1366 (xtensa_instruction_fits): New functions.
1367 (fetch_data): Bump minimal fetch size to 4.
1368 (print_insn_xtensa): Make struct dis_private static.
1369 Load and prepare property table on section change.
1370 Don't disassemble literals. Don't disassemble instructions that
1371 cross property table boundaries.
1373 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1375 * configure: Regenerated.
1377 2018-06-01 Jan Beulich <jbeulich@suse.com>
1379 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1380 * i386-tbl.h: Re-generate.
1382 2018-06-01 Jan Beulich <jbeulich@suse.com>
1384 * i386-opc.tbl (sldt, str): Add NoRex64.
1385 * i386-tbl.h: Re-generate.
1387 2018-06-01 Jan Beulich <jbeulich@suse.com>
1389 * i386-opc.tbl (invpcid): Add Oword.
1390 * i386-tbl.h: Re-generate.
1392 2018-06-01 Alan Modra <amodra@gmail.com>
1394 * sysdep.h (_bfd_error_handler): Don't declare.
1395 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1396 * rl78-decode.opc: Likewise.
1397 * msp430-decode.c: Regenerate.
1398 * rl78-decode.c: Regenerate.
1400 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1402 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1403 * i386-init.h : Regenerated.
1405 2018-05-25 Alan Modra <amodra@gmail.com>
1407 * Makefile.in: Regenerate.
1408 * po/POTFILES.in: Regenerate.
1410 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1412 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1413 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1414 (insert_bab, extract_bab, insert_btab, extract_btab,
1415 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1416 (BAT, BBA VBA RBS XB6S): Delete macros.
1417 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1418 (BB, BD, RBX, XC6): Update for new macros.
1419 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1420 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1421 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1422 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1424 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1426 * Makefile.am: Add support for s12z architecture.
1427 * configure.ac: Likewise.
1428 * disassemble.c: Likewise.
1429 * disassemble.h: Likewise.
1430 * Makefile.in: Regenerate.
1431 * configure: Regenerate.
1432 * s12z-dis.c: New file.
1435 2018-05-18 Alan Modra <amodra@gmail.com>
1437 * nfp-dis.c: Don't #include libbfd.h.
1438 (init_nfp3200_priv): Use bfd_get_section_contents.
1439 (nit_nfp6000_mecsr_sec): Likewise.
1441 2018-05-17 Nick Clifton <nickc@redhat.com>
1443 * po/zh_CN.po: Updated simplified Chinese translation.
1445 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1448 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1449 * aarch64-dis-2.c: Regenerate.
1451 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1454 * aarch64-asm.c (opintl.h): Include.
1455 (aarch64_ins_sysreg): Enforce read/write constraints.
1456 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1457 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1458 (F_REG_READ, F_REG_WRITE): New.
1459 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1460 AARCH64_OPND_SYSREG.
1461 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1462 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1463 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1464 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1465 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1466 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1467 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1468 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1469 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1470 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1471 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1472 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1473 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1474 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1475 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1476 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1477 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1479 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1482 * aarch64-dis.c (no_notes: New.
1483 (parse_aarch64_dis_option): Support notes.
1484 (aarch64_decode_insn, print_operands): Likewise.
1485 (print_aarch64_disassembler_options): Document notes.
1486 * aarch64-opc.c (aarch64_print_operand): Support notes.
1488 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1491 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1492 and take error struct.
1493 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1494 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1495 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1496 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1497 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1498 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1499 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1500 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1501 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1502 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1503 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1504 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1505 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1506 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1507 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1508 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1509 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1510 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1511 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1512 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1513 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1514 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1515 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1516 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1517 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1518 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1519 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1520 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1521 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1522 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1523 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1524 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1525 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1526 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1527 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1528 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1529 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1530 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1531 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1532 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1533 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1534 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1535 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1536 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1537 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1538 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1539 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1540 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1541 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1542 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1543 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1544 (determine_disassembling_preference, aarch64_decode_insn,
1545 print_insn_aarch64_word, print_insn_data): Take errors struct.
1546 (print_insn_aarch64): Use errors.
1547 * aarch64-asm-2.c: Regenerate.
1548 * aarch64-dis-2.c: Regenerate.
1549 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1550 boolean in aarch64_insert_operan.
1551 (print_operand_extractor): Likewise.
1552 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1554 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1556 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1558 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1560 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1562 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1564 * cr16-opc.c (cr16_instruction): Comment typo fix.
1565 * hppa-dis.c (print_insn_hppa): Likewise.
1567 2018-05-08 Jim Wilson <jimw@sifive.com>
1569 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1570 (match_c_slli64, match_srxi_as_c_srxi): New.
1571 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1572 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1573 <c.slli, c.srli, c.srai>: Use match_s_slli.
1574 <c.slli64, c.srli64, c.srai64>: New.
1576 2018-05-08 Alan Modra <amodra@gmail.com>
1578 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1579 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1580 partition opcode space for index lookup.
1582 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1584 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1585 <insn_length>: ...with this. Update usage.
1586 Remove duplicate call to *info->memory_error_func.
1588 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1589 H.J. Lu <hongjiu.lu@intel.com>
1591 * i386-dis.c (Gva): New.
1592 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1593 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1594 (prefix_table): New instructions (see prefix above).
1595 (mod_table): New instructions (see prefix above).
1596 (OP_G): Handle va_mode.
1597 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1598 CPU_MOVDIR64B_FLAGS.
1599 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1600 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1601 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1602 * i386-opc.tbl: Add movidir{i,64b}.
1603 * i386-init.h: Regenerated.
1604 * i386-tbl.h: Likewise.
1606 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1608 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1610 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1611 (AddrPrefixOpReg): This.
1612 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1613 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1615 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1617 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1618 (vle_num_opcodes): Likewise.
1619 (spe2_num_opcodes): Likewise.
1620 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1621 initialization loop.
1622 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1623 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1626 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1628 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1630 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1632 Makefile.am: Added nfp-dis.c.
1633 configure.ac: Added bfd_nfp_arch.
1634 disassemble.h: Added print_insn_nfp prototype.
1635 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1636 nfp-dis.c: New, for NFP support.
1637 po/POTFILES.in: Added nfp-dis.c to the list.
1638 Makefile.in: Regenerate.
1639 configure: Regenerate.
1641 2018-04-26 Jan Beulich <jbeulich@suse.com>
1643 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1644 templates into their base ones.
1645 * i386-tlb.h: Re-generate.
1647 2018-04-26 Jan Beulich <jbeulich@suse.com>
1649 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1650 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1651 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1652 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1653 * i386-init.h: Re-generate.
1655 2018-04-26 Jan Beulich <jbeulich@suse.com>
1657 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1658 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1659 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1660 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1662 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1664 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1666 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1667 cpuregzmm, and cpuregmask.
1668 * i386-init.h: Re-generate.
1669 * i386-tbl.h: Re-generate.
1671 2018-04-26 Jan Beulich <jbeulich@suse.com>
1673 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1674 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1675 * i386-init.h: Re-generate.
1677 2018-04-26 Jan Beulich <jbeulich@suse.com>
1679 * i386-gen.c (VexImmExt): Delete.
1680 * i386-opc.h (VexImmExt, veximmext): Delete.
1681 * i386-opc.tbl: Drop all VexImmExt uses.
1682 * i386-tlb.h: Re-generate.
1684 2018-04-25 Jan Beulich <jbeulich@suse.com>
1686 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1687 register-only forms.
1688 * i386-tlb.h: Re-generate.
1690 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1692 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1694 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1696 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1698 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1699 (cpu_flags): Add CpuCLDEMOTE.
1700 * i386-init.h: Regenerate.
1701 * i386-opc.h (enum): Add CpuCLDEMOTE,
1702 (i386_cpu_flags): Add cpucldemote.
1703 * i386-opc.tbl: Add cldemote.
1704 * i386-tbl.h: Regenerate.
1706 2018-04-16 Alan Modra <amodra@gmail.com>
1708 * Makefile.am: Remove sh5 and sh64 support.
1709 * configure.ac: Likewise.
1710 * disassemble.c: Likewise.
1711 * disassemble.h: Likewise.
1712 * sh-dis.c: Likewise.
1713 * sh64-dis.c: Delete.
1714 * sh64-opc.c: Delete.
1715 * sh64-opc.h: Delete.
1716 * Makefile.in: Regenerate.
1717 * configure: Regenerate.
1718 * po/POTFILES.in: Regenerate.
1720 2018-04-16 Alan Modra <amodra@gmail.com>
1722 * Makefile.am: Remove w65 support.
1723 * configure.ac: Likewise.
1724 * disassemble.c: Likewise.
1725 * disassemble.h: Likewise.
1726 * w65-dis.c: Delete.
1727 * w65-opc.h: Delete.
1728 * Makefile.in: Regenerate.
1729 * configure: Regenerate.
1730 * po/POTFILES.in: Regenerate.
1732 2018-04-16 Alan Modra <amodra@gmail.com>
1734 * configure.ac: Remove we32k support.
1735 * configure: Regenerate.
1737 2018-04-16 Alan Modra <amodra@gmail.com>
1739 * Makefile.am: Remove m88k support.
1740 * configure.ac: Likewise.
1741 * disassemble.c: Likewise.
1742 * disassemble.h: Likewise.
1743 * m88k-dis.c: Delete.
1744 * Makefile.in: Regenerate.
1745 * configure: Regenerate.
1746 * po/POTFILES.in: Regenerate.
1748 2018-04-16 Alan Modra <amodra@gmail.com>
1750 * Makefile.am: Remove i370 support.
1751 * configure.ac: Likewise.
1752 * disassemble.c: Likewise.
1753 * disassemble.h: Likewise.
1754 * i370-dis.c: Delete.
1755 * i370-opc.c: Delete.
1756 * Makefile.in: Regenerate.
1757 * configure: Regenerate.
1758 * po/POTFILES.in: Regenerate.
1760 2018-04-16 Alan Modra <amodra@gmail.com>
1762 * Makefile.am: Remove h8500 support.
1763 * configure.ac: Likewise.
1764 * disassemble.c: Likewise.
1765 * disassemble.h: Likewise.
1766 * h8500-dis.c: Delete.
1767 * h8500-opc.h: Delete.
1768 * Makefile.in: Regenerate.
1769 * configure: Regenerate.
1770 * po/POTFILES.in: Regenerate.
1772 2018-04-16 Alan Modra <amodra@gmail.com>
1774 * configure.ac: Remove tahoe support.
1775 * configure: Regenerate.
1777 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1779 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1781 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1783 * i386-tbl.h: Regenerated.
1785 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1787 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1788 PREFIX_MOD_1_0FAE_REG_6.
1790 (OP_E_register): Use va_mode.
1791 * i386-dis-evex.h (prefix_table):
1792 New instructions (see prefixes above).
1793 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1794 (cpu_flags): Likewise.
1795 * i386-opc.h (enum): Likewise.
1796 (i386_cpu_flags): Likewise.
1797 * i386-opc.tbl: Add umonitor, umwait, tpause.
1798 * i386-init.h: Regenerate.
1799 * i386-tbl.h: Likewise.
1801 2018-04-11 Alan Modra <amodra@gmail.com>
1803 * opcodes/i860-dis.c: Delete.
1804 * opcodes/i960-dis.c: Delete.
1805 * Makefile.am: Remove i860 and i960 support.
1806 * configure.ac: Likewise.
1807 * disassemble.c: Likewise.
1808 * disassemble.h: Likewise.
1809 * Makefile.in: Regenerate.
1810 * configure: Regenerate.
1811 * po/POTFILES.in: Regenerate.
1813 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1816 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1818 (print_insn): Clear vex instead of vex.evex.
1820 2018-04-04 Nick Clifton <nickc@redhat.com>
1822 * po/es.po: Updated Spanish translation.
1824 2018-03-28 Jan Beulich <jbeulich@suse.com>
1826 * i386-gen.c (opcode_modifiers): Delete VecESize.
1827 * i386-opc.h (VecESize): Delete.
1828 (struct i386_opcode_modifier): Delete vecesize.
1829 * i386-opc.tbl: Drop VecESize.
1830 * i386-tlb.h: Re-generate.
1832 2018-03-28 Jan Beulich <jbeulich@suse.com>
1834 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1835 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1836 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1837 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1838 * i386-tlb.h: Re-generate.
1840 2018-03-28 Jan Beulich <jbeulich@suse.com>
1842 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1844 * i386-tlb.h: Re-generate.
1846 2018-03-28 Jan Beulich <jbeulich@suse.com>
1848 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1849 (vex_len_table): Drop Y for vcvt*2si.
1850 (putop): Replace plain 'Y' handling by abort().
1852 2018-03-28 Nick Clifton <nickc@redhat.com>
1855 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1856 instructions with only a base address register.
1857 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1858 handle AARHC64_OPND_SVE_ADDR_R.
1859 (aarch64_print_operand): Likewise.
1860 * aarch64-asm-2.c: Regenerate.
1861 * aarch64_dis-2.c: Regenerate.
1862 * aarch64-opc-2.c: Regenerate.
1864 2018-03-22 Jan Beulich <jbeulich@suse.com>
1866 * i386-opc.tbl: Drop VecESize from register only insn forms and
1867 memory forms not allowing broadcast.
1868 * i386-tlb.h: Re-generate.
1870 2018-03-22 Jan Beulich <jbeulich@suse.com>
1872 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1873 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1874 sha256*): Drop Disp<N>.
1876 2018-03-22 Jan Beulich <jbeulich@suse.com>
1878 * i386-dis.c (EbndS, bnd_swap_mode): New.
1879 (prefix_table): Use EbndS.
1880 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1881 * i386-opc.tbl (bndmov): Move misplaced Load.
1882 * i386-tlb.h: Re-generate.
1884 2018-03-22 Jan Beulich <jbeulich@suse.com>
1886 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1887 templates allowing memory operands and folded ones for register
1889 * i386-tlb.h: Re-generate.
1891 2018-03-22 Jan Beulich <jbeulich@suse.com>
1893 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1894 256-bit templates. Drop redundant leftover Disp<N>.
1895 * i386-tlb.h: Re-generate.
1897 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1899 * riscv-opc.c (riscv_insn_types): New.
1901 2018-03-13 Nick Clifton <nickc@redhat.com>
1903 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1905 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1907 * i386-opc.tbl: Add Optimize to clr.
1908 * i386-tbl.h: Regenerated.
1910 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1912 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1913 * i386-opc.h (OldGcc): Removed.
1914 (i386_opcode_modifier): Remove oldgcc.
1915 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1916 instructions for old (<= 2.8.1) versions of gcc.
1917 * i386-tbl.h: Regenerated.
1919 2018-03-08 Jan Beulich <jbeulich@suse.com>
1921 * i386-opc.h (EVEXDYN): New.
1922 * i386-opc.tbl: Fold various AVX512VL templates.
1923 * i386-tlb.h: Re-generate.
1925 2018-03-08 Jan Beulich <jbeulich@suse.com>
1927 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1928 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1929 vpexpandd, vpexpandq): Fold AFX512VF templates.
1930 * i386-tlb.h: Re-generate.
1932 2018-03-08 Jan Beulich <jbeulich@suse.com>
1934 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1935 Fold 128- and 256-bit VEX-encoded templates.
1936 * i386-tlb.h: Re-generate.
1938 2018-03-08 Jan Beulich <jbeulich@suse.com>
1940 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1941 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1942 vpexpandd, vpexpandq): Fold AVX512F templates.
1943 * i386-tlb.h: Re-generate.
1945 2018-03-08 Jan Beulich <jbeulich@suse.com>
1947 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1948 64-bit templates. Drop Disp<N>.
1949 * i386-tlb.h: Re-generate.
1951 2018-03-08 Jan Beulich <jbeulich@suse.com>
1953 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1954 and 256-bit templates.
1955 * i386-tlb.h: Re-generate.
1957 2018-03-08 Jan Beulich <jbeulich@suse.com>
1959 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1960 * i386-tlb.h: Re-generate.
1962 2018-03-08 Jan Beulich <jbeulich@suse.com>
1964 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1966 * i386-tlb.h: Re-generate.
1968 2018-03-08 Jan Beulich <jbeulich@suse.com>
1970 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1971 * i386-tlb.h: Re-generate.
1973 2018-03-08 Jan Beulich <jbeulich@suse.com>
1975 * i386-gen.c (opcode_modifiers): Delete FloatD.
1976 * i386-opc.h (FloatD): Delete.
1977 (struct i386_opcode_modifier): Delete floatd.
1978 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1980 * i386-tlb.h: Re-generate.
1982 2018-03-08 Jan Beulich <jbeulich@suse.com>
1984 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1986 2018-03-08 Jan Beulich <jbeulich@suse.com>
1988 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1989 * i386-tlb.h: Re-generate.
1991 2018-03-08 Jan Beulich <jbeulich@suse.com>
1993 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1995 * i386-tlb.h: Re-generate.
1997 2018-03-07 Alan Modra <amodra@gmail.com>
1999 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2001 * disassemble.h (print_insn_rs6000): Delete.
2002 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2003 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2004 (print_insn_rs6000): Delete.
2006 2018-03-03 Alan Modra <amodra@gmail.com>
2008 * sysdep.h (opcodes_error_handler): Define.
2009 (_bfd_error_handler): Declare.
2010 * Makefile.am: Remove stray #.
2011 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2013 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2014 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2015 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2016 opcodes_error_handler to print errors. Standardize error messages.
2017 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2018 and include opintl.h.
2019 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2020 * i386-gen.c: Standardize error messages.
2021 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2022 * Makefile.in: Regenerate.
2023 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2024 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2025 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2026 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2027 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2028 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2029 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2030 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2031 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2032 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2033 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2034 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2035 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2037 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2039 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2040 vpsub[bwdq] instructions.
2041 * i386-tbl.h: Regenerated.
2043 2018-03-01 Alan Modra <amodra@gmail.com>
2045 * configure.ac (ALL_LINGUAS): Sort.
2046 * configure: Regenerate.
2048 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2050 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2051 macro by assignements.
2053 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2056 * i386-gen.c (opcode_modifiers): Add Optimize.
2057 * i386-opc.h (Optimize): New enum.
2058 (i386_opcode_modifier): Add optimize.
2059 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2060 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2061 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2062 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2063 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2065 * i386-tbl.h: Regenerated.
2067 2018-02-26 Alan Modra <amodra@gmail.com>
2069 * crx-dis.c (getregliststring): Allocate a large enough buffer
2070 to silence false positive gcc8 warning.
2072 2018-02-22 Shea Levy <shea@shealevy.com>
2074 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2076 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2078 * i386-opc.tbl: Add {rex},
2079 * i386-tbl.h: Regenerated.
2081 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2083 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2084 (mips16_opcodes): Replace `M' with `m' for "restore".
2086 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2088 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2090 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2092 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2093 variable to `function_index'.
2095 2018-02-13 Nick Clifton <nickc@redhat.com>
2098 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2099 about truncation of printing.
2101 2018-02-12 Henry Wong <henry@stuffedcow.net>
2103 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2105 2018-02-05 Nick Clifton <nickc@redhat.com>
2107 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2109 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2111 * i386-dis.c (enum): Add pconfig.
2112 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2113 (cpu_flags): Add CpuPCONFIG.
2114 * i386-opc.h (enum): Add CpuPCONFIG.
2115 (i386_cpu_flags): Add cpupconfig.
2116 * i386-opc.tbl: Add PCONFIG instruction.
2117 * i386-init.h: Regenerate.
2118 * i386-tbl.h: Likewise.
2120 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2122 * i386-dis.c (enum): Add PREFIX_0F09.
2123 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2124 (cpu_flags): Add CpuWBNOINVD.
2125 * i386-opc.h (enum): Add CpuWBNOINVD.
2126 (i386_cpu_flags): Add cpuwbnoinvd.
2127 * i386-opc.tbl: Add WBNOINVD instruction.
2128 * i386-init.h: Regenerate.
2129 * i386-tbl.h: Likewise.
2131 2018-01-17 Jim Wilson <jimw@sifive.com>
2133 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2135 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2137 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2138 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2139 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2140 (cpu_flags): Add CpuIBT, CpuSHSTK.
2141 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2142 (i386_cpu_flags): Add cpuibt, cpushstk.
2143 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2144 * i386-init.h: Regenerate.
2145 * i386-tbl.h: Likewise.
2147 2018-01-16 Nick Clifton <nickc@redhat.com>
2149 * po/pt_BR.po: Updated Brazilian Portugese translation.
2150 * po/de.po: Updated German translation.
2152 2018-01-15 Jim Wilson <jimw@sifive.com>
2154 * riscv-opc.c (match_c_nop): New.
2155 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2157 2018-01-15 Nick Clifton <nickc@redhat.com>
2159 * po/uk.po: Updated Ukranian translation.
2161 2018-01-13 Nick Clifton <nickc@redhat.com>
2163 * po/opcodes.pot: Regenerated.
2165 2018-01-13 Nick Clifton <nickc@redhat.com>
2167 * configure: Regenerate.
2169 2018-01-13 Nick Clifton <nickc@redhat.com>
2171 2.30 branch created.
2173 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2175 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2176 * i386-tbl.h: Regenerate.
2178 2018-01-10 Jan Beulich <jbeulich@suse.com>
2180 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2181 * i386-tbl.h: Re-generate.
2183 2018-01-10 Jan Beulich <jbeulich@suse.com>
2185 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2186 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2187 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2188 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2189 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2190 Disp8MemShift of AVX512VL forms.
2191 * i386-tbl.h: Re-generate.
2193 2018-01-09 Jim Wilson <jimw@sifive.com>
2195 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2196 then the hi_addr value is zero.
2198 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2200 * arm-dis.c (arm_opcodes): Add csdb.
2201 (thumb32_opcodes): Add csdb.
2203 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2205 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2206 * aarch64-asm-2.c: Regenerate.
2207 * aarch64-dis-2.c: Regenerate.
2208 * aarch64-opc-2.c: Regenerate.
2210 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2213 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2214 Remove AVX512 vmovd with 64-bit operands.
2215 * i386-tbl.h: Regenerated.
2217 2018-01-05 Jim Wilson <jimw@sifive.com>
2219 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2222 2018-01-03 Alan Modra <amodra@gmail.com>
2224 Update year range in copyright notice of all files.
2226 2018-01-02 Jan Beulich <jbeulich@suse.com>
2228 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2229 and OPERAND_TYPE_REGZMM entries.
2231 For older changes see ChangeLog-2017
2233 Copyright (C) 2018 Free Software Foundation, Inc.
2235 Copying and distribution of this file, with or without modification,
2236 are permitted in any medium without royalty provided the copyright
2237 notice and this notice are preserved.
2243 version-control: never